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authorJiri Gaisler <jiri@gaisler.se>2019-11-05 17:45:01 +0100
committerJiri Gaisler <jiri@gaisler.se>2019-11-08 22:33:22 +0100
commit8828fb20a0df7f0747d5c6678328d261f310fc64 (patch)
tree1402f18a68786214439b2ef772905e5ff9746527 /interf.c
parent88b545002e553f1e21fab1aff854a3e325976ad3 (diff)
Replaced windows flushing with reg cache
Diffstat (limited to 'interf.c')
-rw-r--r--interf.c7
1 files changed, 6 insertions, 1 deletions
diff --git a/interf.c b/interf.c
index 259e793..d23d3a0 100644
--- a/interf.c
+++ b/interf.c
@@ -98,6 +98,11 @@ sim_read (uint32 mem, char *buf, int length)
{
int i, len;
+ if (sis_gdb_break && (cputype <= CPU_LEON3) && (length >= 4))
+ {
+ if (gdb_sp_read (mem, buf, length))
+ return length;
+ }
for (i = 0; i < length; i++)
{
ms->sis_memory_read ((mem + i) ^ arch->endian, &buf[i], 1);
@@ -124,7 +129,7 @@ sim_resume (int step)
simstat = run_sim_gdb (UINT64_MAX / 2, 0);
if (sis_gdb_break && (cputype != CPU_RISCV))
- flush_windows (&sregs[cpu]);
+ save_sp (&sregs[cpu]);
}
int