diff options
Diffstat (limited to 'cpukit/score/cpu/arm/armv7m-exception-default.c')
| -rw-r--r-- | cpukit/score/cpu/arm/armv7m-exception-default.c | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/cpukit/score/cpu/arm/armv7m-exception-default.c b/cpukit/score/cpu/arm/armv7m-exception-default.c index 35dde50dc3..6d3eb49ea0 100644 --- a/cpukit/score/cpu/arm/armv7m-exception-default.c +++ b/cpukit/score/cpu/arm/armv7m-exception-default.c @@ -42,21 +42,21 @@ #ifdef ARM_MULTILIB_ARCH_V7M -void __attribute__((naked)) _ARMV7M_Exception_default( void ) +void __attribute__((naked)) _ARMV7M_Exception_default(void) { - /* On exception entry, ARMv7M saves context state onto a stack pointed to - * by either MSP or PSP. The value stored in LR indicates whether we were - * in Thread or Handler mode, whether we were using the FPU (if any), - * and which stack pointer we were using. - * In particular, bit 2 of LR will be 0 if we were using MSP. - * - * For a more detailed explanation, see the Exception Entry Behavior - * section of the ARMv7M Architecture Reference Manual. - */ + /* On exception entry, ARMv7M saves context state onto a stack pointed to + * by either MSP or PSP. The value stored in LR indicates whether we were + * in Thread or Handler mode, whether we were using the FPU (if any), + * and which stack pointer we were using. + * In particular, bit 2 of LR will be 0 if we were using MSP. + * + * For a more detailed explanation, see the Exception Entry Behavior + * section of the ARMv7M Architecture Reference Manual. + */ - /* As we're in Handler mode here, we'll always operate on MSP. - * However, we need to store the right SP in our CPU_Exception_frame. - */ + /* As we're in Handler mode here, we'll always operate on MSP. + * However, we need to store the right SP in our CPU_Exception_frame. + */ __asm__ volatile ( "sub sp, %[cpufsz]\n" /* Allocate space for a CPU_Exception_frame. */ "stm sp, {r0-r12}\n" |