diff options
Diffstat (limited to 'c/src/lib/libcpu')
| -rw-r--r-- | c/src/lib/libcpu/i386/idt.c | 288 | ||||
| -rw-r--r-- | c/src/lib/libcpu/m68k/shared/misc/memcpy.c | 87 | ||||
| -rw-r--r-- | c/src/lib/libcpu/mips/clock/ckinit.c | 249 | ||||
| -rw-r--r-- | c/src/lib/libcpu/mips/clock/clock.S | 45 | ||||
| -rw-r--r-- | c/src/lib/libcpu/mips/clock/clock.h | 25 | ||||
| -rw-r--r-- | c/src/lib/libcpu/mips/timer/gettime.S | 35 | ||||
| -rw-r--r-- | c/src/lib/libcpu/mips/timer/timer.c | 140 | ||||
| -rw-r--r-- | c/src/lib/libcpu/sh/sh7032/score/cpu_asm.c | 311 | ||||
| -rw-r--r-- | c/src/lib/libcpu/sh/sh7032/score/ispsh7032.c | 252 | ||||
| -rw-r--r-- | c/src/lib/libcpu/sh/sh7045/score/cpu_asm.c | 311 | ||||
| -rw-r--r-- | c/src/lib/libcpu/sparc/include/erc32.h | 521 |
11 files changed, 0 insertions, 2264 deletions
diff --git a/c/src/lib/libcpu/i386/idt.c b/c/src/lib/libcpu/i386/idt.c deleted file mode 100644 index 5f44bd0d2b..0000000000 --- a/c/src/lib/libcpu/i386/idt.c +++ /dev/null @@ -1,288 +0,0 @@ -/* - * cpu.c - This file contains implementation of C function to - * Instanciate IDT entries. More detailled information can be found - * on Intel site and more precisely in the following book : - * - * Pentium Processor familly - * Developper's Manual - * - * Volume 3 : Architecture and Programming Manual - * - * Copyright (C) 1998 Eric Valette (valette@crf.canon.fr) - * Canon Centre Recherche France. - * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <libcpu/cpu.h> -#include <irq.h> - -static rtems_raw_irq_connect_data* raw_irq_table; -static rtems_raw_irq_connect_data default_raw_irq_entry; -static interrupt_gate_descriptor default_idt_entry; -static rtems_raw_irq_global_settings* local_settings; - -void create_interrupt_gate_descriptor (interrupt_gate_descriptor* idtEntry, - rtems_raw_irq_hdl hdl) -{ - idtEntry->low_offsets_bits = (((unsigned) hdl) & 0xffff); - idtEntry->segment_selector = i386_get_cs(); - idtEntry->fixed_value_bits = 0; - idtEntry->gate_type = 0xe; - idtEntry->privilege = 0; - idtEntry->present = 1; - idtEntry->high_offsets_bits = ((((unsigned) hdl) >> 16) & 0xffff); -} - -rtems_raw_irq_hdl get_hdl_from_vector(rtems_vector_offset index) -{ - rtems_raw_irq_hdl hdl; - interrupt_gate_descriptor* idt_entry_tbl; - unsigned limit; - - i386_get_info_from_IDTR (&idt_entry_tbl, &limit); - - /* Convert limit into number of entries */ - limit = (limit + 1) / sizeof(interrupt_gate_descriptor); - - if(index >= limit) { - return 0; - } - - * ((unsigned int*) &hdl) = (idt_entry_tbl[index].low_offsets_bits | - (idt_entry_tbl[index].high_offsets_bits << 16)); - return hdl; -} - -int i386_set_idt_entry (const rtems_raw_irq_connect_data* irq) -{ - interrupt_gate_descriptor* idt_entry_tbl; - unsigned limit; - unsigned int level; - - - i386_get_info_from_IDTR (&idt_entry_tbl, &limit); - - /* Convert limit into number of entries */ - limit = (limit + 1) / sizeof(interrupt_gate_descriptor); - - if (irq->idtIndex >= limit) { - return 0; - } - /* - * Check if default handler is actually connected. If not issue an error. - * You must first get the current handler via i386_get_current_idt_entry - * and then disconnect it using i386_delete_idt_entry. - * RATIONALE : to always have the same transition by forcing the user - * to get the previous handler before accepting to disconnect. - */ - if (get_hdl_from_vector(irq->idtIndex) != default_raw_irq_entry.hdl) { - return 0; - } - - _CPU_ISR_Disable(level); - - raw_irq_table [irq->idtIndex] = *irq; - create_interrupt_gate_descriptor (&idt_entry_tbl[irq->idtIndex], irq->hdl); - irq->on(irq); - - _CPU_ISR_Enable(level); - return 1; -} - -void _CPU_ISR_install_vector (unsigned vector, - void* hdl, - void** oldHdl) -{ - interrupt_gate_descriptor* idt_entry_tbl; - unsigned limit; - interrupt_gate_descriptor new; - unsigned int level; - - i386_get_info_from_IDTR (&idt_entry_tbl, &limit); - - /* Convert limit into number of entries */ - limit = (limit + 1) / sizeof(interrupt_gate_descriptor); - - if (vector >= limit) { - return; - } - _CPU_ISR_Disable(level) - * ((unsigned int *) oldHdl) = idt_entry_tbl[vector].low_offsets_bits | - (idt_entry_tbl[vector].high_offsets_bits << 16); - - create_interrupt_gate_descriptor(&new, hdl); - idt_entry_tbl[vector] = new; - - _CPU_ISR_Enable(level); -} - -int i386_get_current_idt_entry (rtems_raw_irq_connect_data* irq) -{ - interrupt_gate_descriptor* idt_entry_tbl; - unsigned limit; - - i386_get_info_from_IDTR (&idt_entry_tbl, &limit); - - /* Convert limit into number of entries */ - limit = (limit + 1) / sizeof(interrupt_gate_descriptor); - - if (irq->idtIndex >= limit) { - return 0; - } - raw_irq_table [irq->idtIndex].hdl = get_hdl_from_vector(irq->idtIndex); - - *irq = raw_irq_table [irq->idtIndex]; - - return 1; -} - -int i386_delete_idt_entry (const rtems_raw_irq_connect_data* irq) -{ - interrupt_gate_descriptor* idt_entry_tbl; - unsigned limit; - unsigned int level; - - i386_get_info_from_IDTR (&idt_entry_tbl, &limit); - - /* Convert limit into number of entries */ - limit = (limit + 1) / sizeof(interrupt_gate_descriptor); - - if (irq->idtIndex >= limit) { - return 0; - } - /* - * Check if handler passed is actually connected. If not issue an error. - * You must first get the current handler via i386_get_current_idt_entry - * and then disconnect it using i386_delete_idt_entry. - * RATIONALE : to always have the same transition by forcing the user - * to get the previous handler before accepting to disconnect. - */ - if (get_hdl_from_vector(irq->idtIndex) != irq->hdl){ - return 0; - } - _CPU_ISR_Disable(level); - - idt_entry_tbl[irq->idtIndex] = default_idt_entry; - - irq->off(irq); - - raw_irq_table[irq->idtIndex] = default_raw_irq_entry; - raw_irq_table[irq->idtIndex].idtIndex = irq->idtIndex; - - _CPU_ISR_Enable(level); - - return 1; -} - -/* - * Caution this function assumes the IDTR has been already set. - */ -int i386_init_idt (rtems_raw_irq_global_settings* config) -{ - unsigned limit; - unsigned i; - unsigned level; - interrupt_gate_descriptor* idt_entry_tbl; - - i386_get_info_from_IDTR (&idt_entry_tbl, &limit); - - /* Convert limit into number of entries */ - limit = (limit + 1) / sizeof(interrupt_gate_descriptor); - - if (config->idtSize != limit) { - return 0; - } - /* - * store various accelarators - */ - raw_irq_table = config->rawIrqHdlTbl; - local_settings = config; - default_raw_irq_entry = config->defaultRawEntry; - - _CPU_ISR_Disable(level); - - create_interrupt_gate_descriptor (&default_idt_entry, default_raw_irq_entry.hdl); - - for (i=0; i < limit; i++) { - interrupt_gate_descriptor new; - create_interrupt_gate_descriptor (&new, raw_irq_table[i].hdl); - idt_entry_tbl[i] = new; - if (raw_irq_table[i].hdl != default_raw_irq_entry.hdl) { - raw_irq_table[i].on(&raw_irq_table[i]); - } - else { - raw_irq_table[i].off(&raw_irq_table[i]); - } - } - _CPU_ISR_Enable(level); - - return 1; -} - -int i386_get_idt_config (rtems_raw_irq_global_settings** config) -{ - *config = local_settings; - return 1; -} - -/* - * Caution this function assumes the GDTR has been already set. - */ -int i386_set_gdt_entry (unsigned short segment_selector, unsigned base, - unsigned limit) -{ - unsigned gdt_limit; - unsigned short tmp_segment = 0; - unsigned int limit_adjusted; - segment_descriptors* gdt_entry_tbl; - - - i386_get_info_from_GDTR (&gdt_entry_tbl, &gdt_limit); - - if (segment_selector > limit) { - return 0; - } - /* - * set up limit first - */ - limit_adjusted = limit; - if ( limit > 4095 ) { - gdt_entry_tbl[segment_selector].granularity = 1; - limit_adjusted /= 4096; - } - gdt_entry_tbl[segment_selector].limit_15_0 = limit_adjusted & 0xffff; - gdt_entry_tbl[segment_selector].limit_19_16 = (limit_adjusted >> 16) & 0xf; - /* - * set up base - */ - gdt_entry_tbl[segment_selector].base_address_15_0 = base & 0xffff; - gdt_entry_tbl[segment_selector].base_address_23_16 = (base >> 16) & 0xff; - gdt_entry_tbl[segment_selector].base_address_31_24 = (base >> 24) & 0xff; - /* - * set up descriptor type (this may well becomes a parameter if needed) - */ - gdt_entry_tbl[segment_selector].type = 2; /* Data R/W */ - gdt_entry_tbl[segment_selector].descriptor_type = 1; /* Code or Data */ - gdt_entry_tbl[segment_selector].privilege = 0; /* ring 0 */ - gdt_entry_tbl[segment_selector].present = 1; /* not present */ - - /* - * Now, reload all segment registers so the limit takes effect. - */ - - asm volatile( "movw %%ds,%0 ; movw %0,%%ds - movw %%es,%0 ; movw %0,%%es - movw %%fs,%0 ; movw %0,%%fs - movw %%gs,%0 ; movw %0,%%gs - movw %%ss,%0 ; movw %0,%%ss" - : "=r" (tmp_segment) - : "0" (tmp_segment) - ); - - return 1; -} diff --git a/c/src/lib/libcpu/m68k/shared/misc/memcpy.c b/c/src/lib/libcpu/m68k/shared/misc/memcpy.c deleted file mode 100644 index 3948411f4b..0000000000 --- a/c/src/lib/libcpu/m68k/shared/misc/memcpy.c +++ /dev/null @@ -1,87 +0,0 @@ -/* - * C library memcpy routine - * - * This routine has code to optimize performance on the CPU32+ - * and another version for other 68k machines. - * - * It could be optimized more for machines with MOVE16 instructions. - * - * The routine is placed in this source directory to ensure that it - * is picked up by all applications. - * - * W. Eric Norum - * Saskatchewan Accelerator Laboratory - * University of Saskatchewan - * Saskatoon, Saskatchewan, CANADA - * eric@skatter.usask.ca - */ - -#include <string.h> -#include <rtems/score/m68k.h> - -#if defined(__mcpu32__) -#define COPYSETUP(n) n-- -#define COPY(to,from,n,size) \ - asm volatile ("1:\n" \ - "\tmove." size " (%0)+,(%1)+\n" \ - "\tdbf %2,1b\n" \ - "\tsub.l #0x10000,%2\n" \ - "\tbpl.b 1b\n" : \ - "=a" (from), "=a" (to), "=d" (n) :\ - "0" (from), "1" (to), "2" (n) : \ - "cc", "memory") -#else -#define COPYSETUP(n) -#define COPY(to,from,n,size) \ - asm volatile ("1:\n" \ - "\tmove." size " (%0)+,(%1)+\n" \ - "\tsubq.l #1,%2\n\tbne.b 1b\n" : \ - "=a" (from), "=a" (to), "=d" (n) :\ - "0" (from), "1" (to), "2" (n) : \ - "cc", "memory") -#endif - -void * -memcpy(void *s1, const void *s2, size_t n) -{ - char *p1 = s1; - const char *p2 = s2; - - if (n) { - if (n < 16) { - COPYSETUP (n); - COPY (p1, p2, n, "b"); - } - else { - int nbyte; - int nl; - nbyte = (int)p1 & 0x3; - if (nbyte) { - nbyte = 4 - nbyte; - n -= nbyte; - COPYSETUP (nbyte); - COPY (p1, p2, nbyte, "b"); - } -#if (M68K_HAS_MISALIGNED == 0) - /* - * Take care of machines that can't - * handle misaligned references. - */ - if ((int)p2 & 0x1) { - COPYSETUP (n); - COPY (p1, p2, n, "b"); - return s1; - } -#endif - nl = (unsigned int)n >> 2; - COPYSETUP (nl); - COPY (p1, p2, nl, "l"); - nbyte = (int)n & 0x3; - if (nbyte) { - COPYSETUP (nbyte); - COPY (p1, p2, nbyte, "b"); - } - } - } - return s1; -} diff --git a/c/src/lib/libcpu/mips/clock/ckinit.c b/c/src/lib/libcpu/mips/clock/ckinit.c deleted file mode 100644 index 60b3187223..0000000000 --- a/c/src/lib/libcpu/mips/clock/ckinit.c +++ /dev/null @@ -1,249 +0,0 @@ - -/* ckinit.c - * - * This file contains the clock driver initialization for the IDT 4650. - * - * Author: Craig Lebakken <craigl@transition.com> - * - * COPYRIGHT (c) 1996 by Transition Networks Inc. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of Transition Networks not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * Transition Networks makes no representations about the suitability - * of this software for any purpose. - * - * Derived from c/src/lib/libbsp/no_cpu/no_bsp/clock/ckinit.c: - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * Copyright assigned to U.S. Government, 1994. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -/* - * Rather than deleting this, it is commented out to (hopefully) help - * the submitter send updates. - * - * static char _sccsid[] = "@(#)ckinit.c 08/20/96 1.3\n"; - */ - - -#include <stdlib.h> - -#include <rtems.h> -#include <rtems/libio.h> -#include <bsp.h> - -#define EXT_INT5 0x8000 /* external interrupt 5 */ - -#include "clock.h" - -#define CLOCKS_PER_MICROSECOND ( CPU_CLOCK_RATE_MHZ ) /* equivalent to CPU clock speed in MHz */ - -void Clock_exit( void ); -rtems_isr Clock_isr( rtems_vector_number vector ); - - -/* - * The interrupt vector number associated with the clock tick device - * driver. - */ - -#define CLOCK_VECTOR_MASK EXT_INT5 -#define CLOCK_VECTOR 0x7 - -/* - * Clock_driver_ticks is a monotonically increasing counter of the - * number of clock ticks since the driver was initialized. - */ - -volatile rtems_unsigned32 Clock_driver_ticks; - -/* - * Clock_isrs is the number of clock ISRs until the next invocation of - * the RTEMS clock tick routine. The clock tick device driver - * gets an interrupt once a millisecond and counts down until the - * length of time between the user configured microseconds per tick - * has passed. - */ - -rtems_unsigned32 Clock_isrs; /* ISRs until next tick */ - -/* - * These are set by clock driver during its init - */ - -rtems_device_major_number rtems_clock_major = ~0; -rtems_device_minor_number rtems_clock_minor; - -/* - * The previous ISR on this clock tick interrupt vector. - */ - -rtems_isr_entry Old_ticker; - -void Clock_exit( void ); - -static unsigned32 mips_timer_rate = 0; - -/* - * Isr Handler - */ - -rtems_isr Clock_isr( - rtems_vector_number vector -) -{ -/* - * bump the number of clock driver ticks since initialization - * - * determine if it is time to announce the passing of tick as configured - * to RTEMS through the rtems_clock_tick directive - * - * perform any timer dependent tasks - */ - - /* refresh the internal CPU timer */ - mips_set_timer( mips_timer_rate ); - - Clock_driver_ticks += 1; - - rtems_clock_tick(); -} - -/* User callback shell (set from Clock_Control) */ -static void (*user_callback)(void); - -rtems_isr User_Clock_isr( - rtems_vector_number vector -) -{ - /* refresh the internal CPU timer */ - mips_set_timer( mips_timer_rate ); - - if (user_callback) - user_callback(); -} - -/* - * Install_clock - * - * Install a clock tick handleR and reprograms the chip. This - * is used to initially establish the clock tick. - */ - -void Install_clock( - rtems_isr_entry clock_isr -) -{ - /* - * Initialize the clock tick device driver variables - */ - - Clock_driver_ticks = 0; - Clock_isrs = BSP_Configuration.microseconds_per_tick / 1000; - - /* - * If ticks_per_timeslice is configured as non-zero, then the user - * wants a clock tick. - */ - - if ( BSP_Configuration.ticks_per_timeslice ) { - Old_ticker = (rtems_isr_entry) set_vector( clock_isr, CLOCK_VECTOR, 1 ); - /* - * Hardware specific initialize goes here - */ - - mips_timer_rate = BSP_Configuration.microseconds_per_tick * CLOCKS_PER_MICROSECOND; - mips_set_timer( mips_timer_rate ); - enable_int(CLOCK_VECTOR_MASK); - } - - /* - * Schedule the clock cleanup routine to execute if the application exits. - */ - - atexit( Clock_exit ); -} - -/* - * Clean up before the application exits - */ - -void Clock_exit( void ) -{ - if ( BSP_Configuration.ticks_per_timeslice ) { - - /* mips: turn off the timer interrupts */ - disable_int(CLOCK_VECTOR_MASK); - - } -} - -/* - * Clock_initialize - * - * Device driver entry point for clock tick driver initialization. - */ - -rtems_device_driver Clock_initialize( - rtems_device_major_number major, - rtems_device_minor_number minor, - void *pargp -) -{ - Install_clock( Clock_isr ); - - /* - * make major/minor avail to others such as shared memory driver - */ - - rtems_clock_major = major; - rtems_clock_minor = minor; - - return RTEMS_SUCCESSFUL; -} - -rtems_device_driver Clock_control( - rtems_device_major_number major, - rtems_device_minor_number minor, - void *pargp -) -{ - rtems_unsigned32 isrlevel; - rtems_libio_ioctl_args_t *args = pargp; - - if (args == 0) - goto done; - - /* - * This is hokey, but until we get a defined interface - * to do this, it will just be this simple... - */ - - if (args->command == rtems_build_name('I', 'S', 'R', ' ')) - { - Clock_isr(CLOCK_VECTOR); - } - else if (args->command == rtems_build_name('N', 'E', 'W', ' ')) - { - rtems_interrupt_disable( isrlevel ); - user_callback = (void (*)(void))args->buffer; - (void) set_vector( User_Clock_isr, CLOCK_VECTOR, 1 ); - rtems_interrupt_enable( isrlevel ); - } - -done: - return RTEMS_SUCCESSFUL; -} diff --git a/c/src/lib/libcpu/mips/clock/clock.S b/c/src/lib/libcpu/mips/clock/clock.S deleted file mode 100644 index ec0280f494..0000000000 --- a/c/src/lib/libcpu/mips/clock/clock.S +++ /dev/null @@ -1,45 +0,0 @@ -/* clock.s - * - * This file contains the assembly code for the IDT 4650 clock driver. - * - * Author: Craig Lebakken <craigl@transition.com> - * - * COPYRIGHT (c) 1996 by Transition Networks Inc. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of Transition Networks not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * Transition Networks makes no representations about the suitability - * of this software for any purpose. - * - * $Id$ - */ -/* @(#)clock.S 08/20/96 1.2 */ - -#include <rtems/score/iregdef.h> -#include <rtems/score/idtcpu.h> -#include <rtems/score/idtmon.h> - -FRAME(mips_set_timer,sp,0,ra) - .set noreorder - mfc0 t0,C0_COUNT - nop - addu t0,a0,t0 - mtc0 t0,C0_COMPARE - nop - j ra - .set reorder -ENDFRAME(mips_set_timer) - -FRAME(mips_get_timer,sp,0,ra) - .set noreorder - mfc0 v0,C0_COUNT - nop - j ra - .set reorder -ENDFRAME(mips_get_timer) diff --git a/c/src/lib/libcpu/mips/clock/clock.h b/c/src/lib/libcpu/mips/clock/clock.h deleted file mode 100644 index a14304f668..0000000000 --- a/c/src/lib/libcpu/mips/clock/clock.h +++ /dev/null @@ -1,25 +0,0 @@ -/* clock.s - * - * This file contains the assembly code for the IDT 4650 clock driver. - * - * Author: Craig Lebakken <craigl@transition.com> - * - * COPYRIGHT (c) 1996 by Transition Networks Inc. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of Transition Networks not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * Transition Networks makes no representations about the suitability - * of this software for any purpose. - * - * $Id$ - */ - -/* @(#)clock.h 08/20/96 1.2 */ - -extern void mips_set_timer( unsigned32 timer_clock_interval ); diff --git a/c/src/lib/libcpu/mips/timer/gettime.S b/c/src/lib/libcpu/mips/timer/gettime.S deleted file mode 100644 index a00f2d5819..0000000000 --- a/c/src/lib/libcpu/mips/timer/gettime.S +++ /dev/null @@ -1,35 +0,0 @@ -/* gettime.s - * - * This file contains the assembly code for the IDT 4650 timer driver. - * - * Author: Craig Lebakken <craigl@transition.com> - * - * COPYRIGHT (c) 1996 by Transition Networks Inc. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of Transition Networks not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * Transition Networks makes no representations about the suitability - * of this software for any purpose. - * - * $Id$ - */ - -/* @(#)gettime.S 08/20/96 1.2 */ - -#include <rtems/score/iregdef.h> -#include <rtems/score/idtcpu.h> -#include <rtems/score/idtmon.h> - -FRAME(mips_read_timer,sp,0,ra) - .set noreorder - mfc0 v0,C0_COUNT - nop - j ra - .set reorder -ENDFRAME(mips_read_timer) diff --git a/c/src/lib/libcpu/mips/timer/timer.c b/c/src/lib/libcpu/mips/timer/timer.c deleted file mode 100644 index 167a9b3804..0000000000 --- a/c/src/lib/libcpu/mips/timer/timer.c +++ /dev/null @@ -1,140 +0,0 @@ -/* timer.c - * - * This file contains the initialization code for the IDT 4650 timer driver. - * - * Author: Craig Lebakken <craigl@transition.com> - * - * COPYRIGHT (c) 1996 by Transition Networks Inc. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of Transition Networks not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * Transition Networks makes no representations about the suitability - * of this software for any purpose. - * - * derived from src/lib/libbsp/no_cpu/no_bsp/timer/timer.c - * - * This file manages the benchmark timer used by the RTEMS Timing Test - * Suite. Each measured time period is demarcated by calls to - * Timer_initialize() and Read_timer(). Read_timer() usually returns - * the number of microseconds since Timer_initialize() exitted. - * - * NOTE: It is important that the timer start/stop overhead be - * determined when porting or modifying this code. - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * Copyright assigned to U.S. Government, 1994. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -/* - * Rather than deleting this, it is commented out to (hopefully) help - * the submitter send updates. - * - * static char _sccsid[] = "@(#)timer.c 08/20/96 1.5\n"; - */ - - -#include <rtems.h> -#include <bsp.h> - -#define CLOCKS_PER_MICROSECOND ( CPU_CLOCK_RATE_MHZ ) -#define TIMER_MAX_VALUE 0xffffffff - -extern unsigned32 mips_read_timer( void ); - -static rtems_boolean Timer_driver_Find_average_overhead; -static unsigned32 Timer_initial_value = 0; - -void Timer_initialize( void ) -{ - Timer_initial_value = mips_read_timer(); - /* - * Somehow start the timer - */ - - /* Timer on 4650 is always running */ -} - -/* - * The following controls the behavior of Read_timer(). - * - * AVG_OVEREHAD is the overhead for starting and stopping the timer. It - * is usually deducted from the number returned. - * - * LEAST_VALID is the lowest number this routine should trust. Numbers - * below this are "noise" and zero is returned. - */ - -#define AVG_OVERHEAD 8 /* It typically takes X.X microseconds */ - /* (Y countdowns) to start/stop the timer. */ - /* This value is in cycles. */ -#define LEAST_VALID 1 /* Don't trust a clicks value lower than this */ - -int Read_timer( void ) -{ - unsigned64 clicks; - unsigned32 total; - - /* - * Read the timer and see how many clicks it has been since we started. - */ - - clicks = mips_read_timer(); /* XXX: read some HW here */ - if (clicks < Timer_initial_value) - { - clicks += TIMER_MAX_VALUE; - } - clicks -= Timer_initial_value; - - /* - * Total is calculated by taking into account the number of timer overflow - * interrupts since the timer was initialized and clicks since the last - * interrupts. - */ -#if 0 /* leave total in number of cycles */ - total = clicks / CLOCKS_PER_MICROSECOND; -#else - total = clicks; -#endif - - if ( Timer_driver_Find_average_overhead == 1 ) - return total; /* in # cycles units */ - else { - if ( total < LEAST_VALID ) - return 0; /* below timer resolution */ - /* - * leave total in cycles - */ - return (total - AVG_OVERHEAD); - } -} - -/* - * Empty function call used in loops to measure basic cost of looping - * in Timing Test Suite. - */ - -rtems_status_code Empty_function( void ) -{ - return RTEMS_SUCCESSFUL; -} - -void Set_find_average_overhead( - rtems_boolean find_flag -) -{ - Timer_driver_Find_average_overhead = find_flag; -} - diff --git a/c/src/lib/libcpu/sh/sh7032/score/cpu_asm.c b/c/src/lib/libcpu/sh/sh7032/score/cpu_asm.c deleted file mode 100644 index 42764f6eb1..0000000000 --- a/c/src/lib/libcpu/sh/sh7032/score/cpu_asm.c +++ /dev/null @@ -1,311 +0,0 @@ -/* - * This file contains the basic algorithms for all assembly code used - * in an specific CPU port of RTEMS. These algorithms must be implemented - * in assembly language - * - * NOTE: This port uses a C file with inline assembler instructions - * - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998. - * On-Line Applications Research Corporation (OAR). - * Copyright assigned to U.S. Government, 1994. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - * - * This material may be reproduced by or for the U.S. Government pursuant - * to the copyright license under the clause at DFARS 252.227-7013. This - * notice must appear in all copies of this file and its derivatives. - * - */ - -/* - * This is supposed to be an assembly file. This means that system.h - * and cpu.h should not be included in a "real" cpu_asm file. An - * implementation in assembly should include "cpu_asm.h" - */ - -#include <rtems/system.h> -#include <rtems/score/cpu.h> -#include <rtems/score/isr.h> -#include <rtems/score/thread.h> -#include <rtems/score/cpu_isps.h> -#include <rtems/score/sh_io.h> -#include <rtems/score/sh.h> -#include <rtems/score/iosh7030.h> - -/* from cpu_isps.c */ -extern proc_ptr _Hardware_isr_Table[]; - -#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) - unsigned long *_old_stack_ptr; -#endif - -register unsigned long *stack_ptr asm("r15"); - -/* - * sh_set_irq_priority - * - * this function sets the interrupt level of the specified interrupt - * - * parameters: - * - irq : interrupt number - * - prio: priority to set for this interrupt number - * - * returns: 0 if ok - * -1 on error - */ - -unsigned int sh_set_irq_priority( - unsigned int irq, - unsigned int prio ) -{ - unsigned32 shiftcount; - unsigned32 prioreg; - unsigned16 temp16; - unsigned32 level; - - /* - * first check for valid interrupt - */ - if(( irq > 113) || (_Hardware_isr_Table[irq] == _dummy_isp)) - return -1; - /* - * check for valid irq priority - */ - if( prio > 15 ) - return -1; - - /* - * look up appropriate interrupt priority register - */ - if( irq > 71) - { - irq = irq - 72; - shiftcount = 12 - ((irq & ~0x03) % 16); - - switch( irq / 16) - { - case 0: { prioreg = INTC_IPRC; break;} - case 1: { prioreg = INTC_IPRD; break;} - case 2: { prioreg = INTC_IPRE; break;} - default: return -1; - } - } - else - { - shiftcount = 12 - 4 * ( irq % 4); - if( irq > 67) - prioreg = INTC_IPRB; - else - prioreg = INTC_IPRA; - } - - /* - * Set the interrupt priority register - */ - _CPU_ISR_Disable( level ); - - temp16 = read16( prioreg); - temp16 &= ~( 15 << shiftcount); - temp16 |= prio << shiftcount; - write16( temp16, prioreg); - - _CPU_ISR_Enable( level ); - - return 0; -} - -/* - * _CPU_Context_save_fp_context - * - * This routine is responsible for saving the FP context - * at *fp_context_ptr. If the point to load the FP context - * from is changed then the pointer is modified by this routine. - * - * Sometimes a macro implementation of this is in cpu.h which dereferences - * the ** and a similarly named routine in this file is passed something - * like a (Context_Control_fp *). The general rule on making this decision - * is to avoid writing assembly language. - */ - -void _CPU_Context_save_fp( - void **fp_context_ptr -) -{ -} - -/* - * _CPU_Context_restore_fp_context - * - * This routine is responsible for restoring the FP context - * at *fp_context_ptr. If the point to load the FP context - * from is changed then the pointer is modified by this routine. - * - * Sometimes a macro implementation of this is in cpu.h which dereferences - * the ** and a similarly named routine in this file is passed something - * like a (Context_Control_fp *). The general rule on making this decision - * is to avoid writing assembly language. - */ - -void _CPU_Context_restore_fp( - void **fp_context_ptr -) -{ -} - -/* _CPU_Context_switch - * - * This routine performs a normal non-FP context switch. - */ - -/* within __CPU_Context_switch: - * _CPU_Context_switch - * _CPU_Context_restore - * - * This routine is generally used only to restart self in an - * efficient manner. It may simply be a label in _CPU_Context_switch. - * - * NOTE: It should be safe not to store r4, r5 - * - * NOTE: It is doubtful if r0 is really needed to be stored - * - * NOTE: gbr is added, but should not be necessary, as it is - * only used globally in this port. - */ - -/* - * FIXME: This is an ugly hack, but we wanted to avoid recalculating - * the offset each time Context_Control is changed - */ -void __CPU_Context_switch( - Context_Control *run, /* r4 */ - Context_Control *heir /* r5 */ -) -{ - -asm volatile(" - .global __CPU_Context_switch -__CPU_Context_switch: - - add %0,r4 - - stc.l sr,@-r4 - stc.l gbr,@-r4 - mov.l r0,@-r4 - mov.l r1,@-r4 - mov.l r2,@-r4 - mov.l r3,@-r4 - - mov.l r6,@-r4 - mov.l r7,@-r4 - mov.l r8,@-r4 - mov.l r9,@-r4 - mov.l r10,@-r4 - mov.l r11,@-r4 - mov.l r12,@-r4 - mov.l r13,@-r4 - mov.l r14,@-r4 - sts.l pr,@-r4 - sts.l mach,@-r4 - sts.l macl,@-r4 - mov.l r15,@-r4 - - mov r5, r4" - :: "I" (sizeof(Context_Control)) - ); - - asm volatile(" - .global __CPU_Context_restore -__CPU_Context_restore: - mov.l @r4+,r15 - lds.l @r4+,macl - lds.l @r4+,mach - lds.l @r4+,pr - mov.l @r4+,r14 - mov.l @r4+,r13 - mov.l @r4+,r12 - mov.l @r4+,r11 - mov.l @r4+,r10 - mov.l @r4+,r9 - mov.l @r4+,r8 - mov.l @r4+,r7 - mov.l @r4+,r6 - - mov.l @r4+,r3 - mov.l @r4+,r2 - mov.l @r4+,r1 - mov.l @r4+,r0 - ldc.l @r4+,gbr - ldc.l @r4+,sr - - rts - nop" ); -} - -/* - * This routine provides the RTEMS interrupt management. - */ - -void __ISR_Handler( unsigned32 vector) -{ - register unsigned32 level; - - _CPU_ISR_Disable( level ); - - _Thread_Dispatch_disable_level++; - -#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) - if( _ISR_Nest_level == 0 ) - { - /* Install irq stack */ - _old_stack_ptr = stack_ptr; - stack_ptr = _CPU_Interrupt_stack_high; - } - -#endif - - _ISR_Nest_level++; - - _CPU_ISR_Enable( level ); - - /* call isp */ - if( _ISR_Vector_table[ vector]) - (*_ISR_Vector_table[ vector ])( vector ); - - _CPU_ISR_Disable( level ); - - _ISR_Nest_level--; - -#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) - - if( _ISR_Nest_level == 0 ) - /* restore old stack pointer */ - stack_ptr = _old_stack_ptr; -#endif - - _Thread_Dispatch_disable_level--; - - _CPU_ISR_Enable( level ); - - if ( _Thread_Dispatch_disable_level == 0 ) - { - if(( _Context_Switch_necessary) || (! _ISR_Signals_to_thread_executing)) - { - _ISR_Signals_to_thread_executing = FALSE; - _Thread_Dispatch(); - } - } -} diff --git a/c/src/lib/libcpu/sh/sh7032/score/ispsh7032.c b/c/src/lib/libcpu/sh/sh7032/score/ispsh7032.c deleted file mode 100644 index 3ef3c32465..0000000000 --- a/c/src/lib/libcpu/sh/sh7032/score/ispsh7032.c +++ /dev/null @@ -1,252 +0,0 @@ -/* - * This file contains the isp frames for the user interrupts. - * From these procedures __ISR_Handler is called with the vector number - * as argument. - * - * __ISR_Handler is kept in a separate file (cpu_asm.c), because a bug in - * some releases of gcc doesn't properly handle #pragma interrupt, if a - * file contains both isrs and normal functions. - * - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE - * - * - * COPYRIGHT (c) 1998. - * On-Line Applications Research Corporation (OAR). - * Copyright assigned to U.S. Government, 1994. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/shtypes.h> -#include <rtems/score/cpu_isps.h> - -/* - * This is a exception vector table - * - * It has the same structure like the actual vector table (vectab) - */ -proc_ptr _Hardware_isr_Table[256]={ -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, -_nmi_isp, _usb_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, -/* trapa 0 -31 */ -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -/* irq 64 ... */ -_irq0_isp, _irq1_isp, _irq2_isp, _irq3_isp, -_irq4_isp, _irq5_isp, _irq6_isp, _irq7_isp, -_dma0_isp, _dummy_isp, _dma1_isp, _dummy_isp, -_dma2_isp, _dummy_isp, _dma3_isp, _dummy_isp, -_imia0_isp, _imib0_isp, _ovi0_isp, _dummy_isp, -_imia1_isp, _imib1_isp, _ovi1_isp, _dummy_isp, -_imia2_isp, _imib2_isp, _ovi2_isp, _dummy_isp, -_imia3_isp, _imib3_isp, _ovi3_isp, _dummy_isp, -_imia4_isp, _imib4_isp, _ovi4_isp, _dummy_isp, -_eri0_isp, _rxi0_isp, _txi0_isp, _tei0_isp, -_eri1_isp, _rxi1_isp, _txi1_isp, _tei1_isp, -_prt_isp, _adu_isp, _dummy_isp, _dummy_isp, -_wdt_isp, -/* 113 */ _dref_isp -}; - -#define Str(a)#a - -/* - * Some versions of gcc and all version of egcs at least until egcs-1.1b - * are not able to handle #pragma interrupt correctly if more than 1 isr is - * contained in a file and when optimizing. - * We try to work around this problem by using the macro below. - */ -#define isp( name, number, func)\ -asm (".global _"Str(name)"\n\t" \ - "_"Str(name)": \n\t" \ - " mov.l r0,@-r15 \n\t" \ - " mov.l r1,@-r15 \n\t" \ - " mov.l r2,@-r15 \n\t" \ - " mov.l r3,@-r15 \n\t" \ - " mov.l r4,@-r15 \n\t" \ - " mov.l r5,@-r15 \n\t" \ - " mov.l r6,@-r15 \n\t" \ - " mov.l r7,@-r15 \n\t" \ - " mov.l r14,@-r15 \n\t" \ - " sts.l pr,@-r15 \n\t" \ - " sts.l mach,@-r15 \n\t" \ - " sts.l macl,@-r15 \n\t" \ - " mov r15,r14 \n\t" \ - " mov.l "Str(name)"_k, r1\n\t" \ - " jsr @r1 \n\t" \ - " mov #"Str(number)", r4\n\t" \ - " mov r14,r15 \n\t" \ - " lds.l @r15+,macl \n\t" \ - " lds.l @r15+,mach \n\t" \ - " lds.l @r15+,pr \n\t" \ - " mov.l @r15+,r14 \n\t" \ - " mov.l @r15+,r7 \n\t" \ - " mov.l @r15+,r6 \n\t" \ - " mov.l @r15+,r5 \n\t" \ - " mov.l @r15+,r4 \n\t" \ - " mov.l @r15+,r3 \n\t" \ - " mov.l @r15+,r2 \n\t" \ - " mov.l @r15+,r1 \n\t" \ - " mov.l @r15+,r0 \n\t" \ - " rte \n\t" \ - " nop \n\t" \ - " .align 2 \n\t" \ - #name"_k: \n\t" \ - ".long "Str(func)); - -/************************************************ - * Dummy interrupt service procedure for - * interrupts being not allowed --> Trap 34 - ************************************************/ -asm(" .section .text -.global __dummy_isp -__dummy_isp: - mov.l r14,@-r15 - mov r15, r14 - trapa #34 - mov.l @r15+,r14 - rte - nop"); - -/***************************** - * Non maskable interrupt - *****************************/ -isp( _nmi_isp, NMI_ISP_V, ___ISR_Handler); - -/***************************** - * User break controller - *****************************/ -isp( _usb_isp, USB_ISP_V, ___ISR_Handler); - -/***************************** - * External interrupts 0-7 - *****************************/ -isp( _irq0_isp, IRQ0_ISP_V, ___ISR_Handler); -isp( _irq1_isp, IRQ1_ISP_V, ___ISR_Handler); -isp( _irq2_isp, IRQ2_ISP_V, ___ISR_Handler); -isp( _irq3_isp, IRQ3_ISP_V, ___ISR_Handler); -isp( _irq4_isp, IRQ4_ISP_V, ___ISR_Handler); -isp( _irq5_isp, IRQ5_ISP_V, ___ISR_Handler); -isp( _irq6_isp, IRQ6_ISP_V, ___ISR_Handler); -isp( _irq7_isp, IRQ7_ISP_V, ___ISR_Handler); - -/***************************** - * DMA - controller - *****************************/ -isp( _dma0_isp, DMA0_ISP_V, ___ISR_Handler); -isp( _dma1_isp, DMA1_ISP_V, ___ISR_Handler); -isp( _dma2_isp, DMA2_ISP_V, ___ISR_Handler); -isp( _dma3_isp, DMA3_ISP_V, ___ISR_Handler); - - -/***************************** - * Interrupt timer unit - *****************************/ - -/***************************** - * Timer 0 - *****************************/ -isp( _imia0_isp, IMIA0_ISP_V, ___ISR_Handler); -isp( _imib0_isp, IMIB0_ISP_V, ___ISR_Handler); -isp( _ovi0_isp, OVI0_ISP_V, ___ISR_Handler); - -/***************************** - * Timer 1 - *****************************/ -isp( _imia1_isp, IMIA1_ISP_V, ___ISR_Handler); -isp( _imib1_isp, IMIB1_ISP_V, ___ISR_Handler); -isp( _ovi1_isp, OVI1_ISP_V, ___ISR_Handler); - -/***************************** - * Timer 2 - *****************************/ -isp( _imia2_isp, IMIA2_ISP_V, ___ISR_Handler); -isp( _imib2_isp, IMIB2_ISP_V, ___ISR_Handler); -isp( _ovi2_isp, OVI2_ISP_V, ___ISR_Handler); - -/***************************** - * Timer 3 - *****************************/ -isp( _imia3_isp, IMIA3_ISP_V, ___ISR_Handler); -isp( _imib3_isp, IMIB3_ISP_V, ___ISR_Handler); -isp( _ovi3_isp, OVI3_ISP_V, ___ISR_Handler); - -/***************************** - * Timer 4 - *****************************/ -isp( _imia4_isp, IMIA4_ISP_V, ___ISR_Handler); -isp( _imib4_isp, IMIB4_ISP_V, ___ISR_Handler); -isp( _ovi4_isp, OVI4_ISP_V, ___ISR_Handler); - - -/***************************** - * Serial interfaces - *****************************/ - -/***************************** - * Serial interface 0 - *****************************/ -isp( _eri0_isp, ERI0_ISP_V, ___ISR_Handler); -isp( _rxi0_isp, RXI0_ISP_V, ___ISR_Handler); -isp( _txi0_isp, TXI0_ISP_V, ___ISR_Handler); -isp( _tei0_isp, TEI0_ISP_V, ___ISR_Handler); - -/***************************** - * Serial interface 1 - *****************************/ -isp( _eri1_isp, ERI1_ISP_V, ___ISR_Handler); -isp( _rxi1_isp, RXI1_ISP_V, ___ISR_Handler); -isp( _txi1_isp, TXI1_ISP_V, ___ISR_Handler); -isp( _tei1_isp, TEI1_ISP_V, ___ISR_Handler); - - -/***************************** - * Parity control unit of - * the bus state controller - *****************************/ -isp( _prt_isp, PRT_ISP_V, ___ISR_Handler); - - -/****************************** - * Analog digital converter - * ADC - ******************************/ -isp( _adu_isp, ADU_ISP_V, ___ISR_Handler); - - -/****************************** - * Watchdog timer - ******************************/ -isp( _wdt_isp, WDT_ISP_V, ___ISR_Handler); - - -/****************************** - * DRAM refresh control unit - * of bus state controller - ******************************/ -isp( _dref_isp, DREF_ISP_V, ___ISR_Handler); diff --git a/c/src/lib/libcpu/sh/sh7045/score/cpu_asm.c b/c/src/lib/libcpu/sh/sh7045/score/cpu_asm.c deleted file mode 100644 index 42764f6eb1..0000000000 --- a/c/src/lib/libcpu/sh/sh7045/score/cpu_asm.c +++ /dev/null @@ -1,311 +0,0 @@ -/* - * This file contains the basic algorithms for all assembly code used - * in an specific CPU port of RTEMS. These algorithms must be implemented - * in assembly language - * - * NOTE: This port uses a C file with inline assembler instructions - * - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998. - * On-Line Applications Research Corporation (OAR). - * Copyright assigned to U.S. Government, 1994. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - * - * This material may be reproduced by or for the U.S. Government pursuant - * to the copyright license under the clause at DFARS 252.227-7013. This - * notice must appear in all copies of this file and its derivatives. - * - */ - -/* - * This is supposed to be an assembly file. This means that system.h - * and cpu.h should not be included in a "real" cpu_asm file. An - * implementation in assembly should include "cpu_asm.h" - */ - -#include <rtems/system.h> -#include <rtems/score/cpu.h> -#include <rtems/score/isr.h> -#include <rtems/score/thread.h> -#include <rtems/score/cpu_isps.h> -#include <rtems/score/sh_io.h> -#include <rtems/score/sh.h> -#include <rtems/score/iosh7030.h> - -/* from cpu_isps.c */ -extern proc_ptr _Hardware_isr_Table[]; - -#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) - unsigned long *_old_stack_ptr; -#endif - -register unsigned long *stack_ptr asm("r15"); - -/* - * sh_set_irq_priority - * - * this function sets the interrupt level of the specified interrupt - * - * parameters: - * - irq : interrupt number - * - prio: priority to set for this interrupt number - * - * returns: 0 if ok - * -1 on error - */ - -unsigned int sh_set_irq_priority( - unsigned int irq, - unsigned int prio ) -{ - unsigned32 shiftcount; - unsigned32 prioreg; - unsigned16 temp16; - unsigned32 level; - - /* - * first check for valid interrupt - */ - if(( irq > 113) || (_Hardware_isr_Table[irq] == _dummy_isp)) - return -1; - /* - * check for valid irq priority - */ - if( prio > 15 ) - return -1; - - /* - * look up appropriate interrupt priority register - */ - if( irq > 71) - { - irq = irq - 72; - shiftcount = 12 - ((irq & ~0x03) % 16); - - switch( irq / 16) - { - case 0: { prioreg = INTC_IPRC; break;} - case 1: { prioreg = INTC_IPRD; break;} - case 2: { prioreg = INTC_IPRE; break;} - default: return -1; - } - } - else - { - shiftcount = 12 - 4 * ( irq % 4); - if( irq > 67) - prioreg = INTC_IPRB; - else - prioreg = INTC_IPRA; - } - - /* - * Set the interrupt priority register - */ - _CPU_ISR_Disable( level ); - - temp16 = read16( prioreg); - temp16 &= ~( 15 << shiftcount); - temp16 |= prio << shiftcount; - write16( temp16, prioreg); - - _CPU_ISR_Enable( level ); - - return 0; -} - -/* - * _CPU_Context_save_fp_context - * - * This routine is responsible for saving the FP context - * at *fp_context_ptr. If the point to load the FP context - * from is changed then the pointer is modified by this routine. - * - * Sometimes a macro implementation of this is in cpu.h which dereferences - * the ** and a similarly named routine in this file is passed something - * like a (Context_Control_fp *). The general rule on making this decision - * is to avoid writing assembly language. - */ - -void _CPU_Context_save_fp( - void **fp_context_ptr -) -{ -} - -/* - * _CPU_Context_restore_fp_context - * - * This routine is responsible for restoring the FP context - * at *fp_context_ptr. If the point to load the FP context - * from is changed then the pointer is modified by this routine. - * - * Sometimes a macro implementation of this is in cpu.h which dereferences - * the ** and a similarly named routine in this file is passed something - * like a (Context_Control_fp *). The general rule on making this decision - * is to avoid writing assembly language. - */ - -void _CPU_Context_restore_fp( - void **fp_context_ptr -) -{ -} - -/* _CPU_Context_switch - * - * This routine performs a normal non-FP context switch. - */ - -/* within __CPU_Context_switch: - * _CPU_Context_switch - * _CPU_Context_restore - * - * This routine is generally used only to restart self in an - * efficient manner. It may simply be a label in _CPU_Context_switch. - * - * NOTE: It should be safe not to store r4, r5 - * - * NOTE: It is doubtful if r0 is really needed to be stored - * - * NOTE: gbr is added, but should not be necessary, as it is - * only used globally in this port. - */ - -/* - * FIXME: This is an ugly hack, but we wanted to avoid recalculating - * the offset each time Context_Control is changed - */ -void __CPU_Context_switch( - Context_Control *run, /* r4 */ - Context_Control *heir /* r5 */ -) -{ - -asm volatile(" - .global __CPU_Context_switch -__CPU_Context_switch: - - add %0,r4 - - stc.l sr,@-r4 - stc.l gbr,@-r4 - mov.l r0,@-r4 - mov.l r1,@-r4 - mov.l r2,@-r4 - mov.l r3,@-r4 - - mov.l r6,@-r4 - mov.l r7,@-r4 - mov.l r8,@-r4 - mov.l r9,@-r4 - mov.l r10,@-r4 - mov.l r11,@-r4 - mov.l r12,@-r4 - mov.l r13,@-r4 - mov.l r14,@-r4 - sts.l pr,@-r4 - sts.l mach,@-r4 - sts.l macl,@-r4 - mov.l r15,@-r4 - - mov r5, r4" - :: "I" (sizeof(Context_Control)) - ); - - asm volatile(" - .global __CPU_Context_restore -__CPU_Context_restore: - mov.l @r4+,r15 - lds.l @r4+,macl - lds.l @r4+,mach - lds.l @r4+,pr - mov.l @r4+,r14 - mov.l @r4+,r13 - mov.l @r4+,r12 - mov.l @r4+,r11 - mov.l @r4+,r10 - mov.l @r4+,r9 - mov.l @r4+,r8 - mov.l @r4+,r7 - mov.l @r4+,r6 - - mov.l @r4+,r3 - mov.l @r4+,r2 - mov.l @r4+,r1 - mov.l @r4+,r0 - ldc.l @r4+,gbr - ldc.l @r4+,sr - - rts - nop" ); -} - -/* - * This routine provides the RTEMS interrupt management. - */ - -void __ISR_Handler( unsigned32 vector) -{ - register unsigned32 level; - - _CPU_ISR_Disable( level ); - - _Thread_Dispatch_disable_level++; - -#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) - if( _ISR_Nest_level == 0 ) - { - /* Install irq stack */ - _old_stack_ptr = stack_ptr; - stack_ptr = _CPU_Interrupt_stack_high; - } - -#endif - - _ISR_Nest_level++; - - _CPU_ISR_Enable( level ); - - /* call isp */ - if( _ISR_Vector_table[ vector]) - (*_ISR_Vector_table[ vector ])( vector ); - - _CPU_ISR_Disable( level ); - - _ISR_Nest_level--; - -#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) - - if( _ISR_Nest_level == 0 ) - /* restore old stack pointer */ - stack_ptr = _old_stack_ptr; -#endif - - _Thread_Dispatch_disable_level--; - - _CPU_ISR_Enable( level ); - - if ( _Thread_Dispatch_disable_level == 0 ) - { - if(( _Context_Switch_necessary) || (! _ISR_Signals_to_thread_executing)) - { - _ISR_Signals_to_thread_executing = FALSE; - _Thread_Dispatch(); - } - } -} diff --git a/c/src/lib/libcpu/sparc/include/erc32.h b/c/src/lib/libcpu/sparc/include/erc32.h deleted file mode 100644 index 50df21267f..0000000000 --- a/c/src/lib/libcpu/sparc/include/erc32.h +++ /dev/null @@ -1,521 +0,0 @@ -/* erc32.h - * - * This include file contains information pertaining to the ERC32. - * The ERC32 is a custom SPARC V7 implementation based on the Cypress - * 601/602 chipset. This CPU has a number of on-board peripherals and - * was developed by the European Space Agency to target space applications. - * - * NOTE: Other than where absolutely required, this version currently - * supports only the peripherals and bits used by the basic board - * support package. This includes at least significant pieces of - * the following items: - * - * + UART Channels A and B - * + General Purpose Timer - * + Real Time Clock - * + Watchdog Timer (so it can be disabled) - * + Control Register (so powerdown mode can be enabled) - * + Memory Control Register - * + Interrupt Control - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * Copyright assigned to U.S. Government, 1994. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * Ported to ERC32 implementation of the SPARC by On-Line Applications - * Research Corporation (OAR) under contract to the European Space - * Agency (ESA). - * - * ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995. - * European Space Agency. - * - * $Id$ - */ - -#ifndef _INCLUDE_ERC32_h -#define _INCLUDE_ERC32_h - -#include <rtems/score/sparc.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * Interrupt Sources - * - * The interrupt source numbers directly map to the trap type and to - * the bits used in the Interrupt Clear, Interrupt Force, Interrupt Mask, - * and the Interrupt Pending Registers. - */ - -#define ERC32_INTERRUPT_MASKED_ERRORS 1 -#define ERC32_INTERRUPT_EXTERNAL_1 2 -#define ERC32_INTERRUPT_EXTERNAL_2 3 -#define ERC32_INTERRUPT_UART_A_RX_TX 4 -#define ERC32_INTERRUPT_UART_B_RX_TX 5 -#define ERC32_INTERRUPT_CORRECTABLE_MEMORY_ERROR 6 -#define ERC32_INTERRUPT_UART_ERROR 7 -#define ERC32_INTERRUPT_DMA_ACCESS_ERROR 8 -#define ERC32_INTERRUPT_DMA_TIMEOUT 9 -#define ERC32_INTERRUPT_EXTERNAL_3 10 -#define ERC32_INTERRUPT_EXTERNAL_4 11 -#define ERC32_INTERRUPT_GENERAL_PURPOSE_TIMER 12 -#define ERC32_INTERRUPT_REAL_TIME_CLOCK 13 -#define ERC32_INTERRUPT_EXTERNAL_5 14 -#define ERC32_INTERRUPT_WATCHDOG_TIMEOUT 15 - -#ifndef ASM - -/* - * Trap Types for on-chip peripherals - * - * Source: Table 8 - Interrupt Trap Type and Default Priority Assignments - * - * NOTE: The priority level for each source corresponds to the least - * significant nibble of the trap type. - */ - -#define ERC32_TRAP_TYPE( _source ) SPARC_ASYNCHRONOUS_TRAP((_source) + 0x10) - -#define ERC32_TRAP_SOURCE( _trap ) ((_trap) - 0x10) - -#define ERC32_Is_MEC_Trap( _trap ) \ - ( (_trap) >= ERC32_TRAP_TYPE( ERC32_INTERRUPT_MASKED_ERRORS ) && \ - (_trap) <= ERC32_TRAP_TYPE( ERC32_INTERRUPT_WATCHDOG_TIMEOUT ) ) - -/* - * Structure for ERC32 memory mapped registers. - * - * Source: Section 3.25.2 - Register Address Map - * - * NOTE: There is only one of these structures per CPU, its base address - * is 0x01f80000, and the variable MEC is placed there by the - * linkcmds file. - */ - -typedef struct { - volatile unsigned32 Control; /* offset 0x00 */ - volatile unsigned32 Software_Reset; /* offset 0x04 */ - volatile unsigned32 Power_Down; /* offset 0x08 */ - volatile unsigned32 Unimplemented_0; /* offset 0x0c */ - volatile unsigned32 Memory_Configuration; /* offset 0x10 */ - volatile unsigned32 IO_Configuration; /* offset 0x14 */ - volatile unsigned32 Wait_State_Configuration; /* offset 0x18 */ - volatile unsigned32 Unimplemented_1; /* offset 0x1c */ - volatile unsigned32 Memory_Access_0; /* offset 0x20 */ - volatile unsigned32 Memory_Access_1; /* offset 0x24 */ - volatile unsigned32 Unimplemented_2[ 7 ]; /* offset 0x28 */ - volatile unsigned32 Interrupt_Shape; /* offset 0x44 */ - volatile unsigned32 Interrupt_Pending; /* offset 0x48 */ - volatile unsigned32 Interrupt_Mask; /* offset 0x4c */ - volatile unsigned32 Interrupt_Clear; /* offset 0x50 */ - volatile unsigned32 Interrupt_Force; /* offset 0x54 */ - volatile unsigned32 Unimplemented_3[ 2 ]; /* offset 0x58 */ - /* offset 0x60 */ - volatile unsigned32 Watchdog_Program_and_Timeout_Acknowledge; - volatile unsigned32 Watchdog_Trap_Door_Set; /* offset 0x64 */ - volatile unsigned32 Unimplemented_4[ 6 ]; /* offset 0x68 */ - volatile unsigned32 Real_Time_Clock_Counter; /* offset 0x80 */ - volatile unsigned32 Real_Time_Clock_Scalar; /* offset 0x84 */ - volatile unsigned32 General_Purpose_Timer_Counter; /* offset 0x88 */ - volatile unsigned32 General_Purpose_Timer_Scalar; /* offset 0x8c */ - volatile unsigned32 Unimplemented_5[ 2 ]; /* offset 0x90 */ - volatile unsigned32 Timer_Control; /* offset 0x98 */ - volatile unsigned32 Unimplemented_6; /* offset 0x9c */ - volatile unsigned32 System_Fault_Status; /* offset 0xa0 */ - volatile unsigned32 First_Failing_Address; /* offset 0xa4 */ - volatile unsigned32 First_Failing_Data; /* offset 0xa8 */ - volatile unsigned32 First_Failing_Syndrome_and_Check_Bits;/* offset 0xac */ - volatile unsigned32 Error_and_Reset_Status; /* offset 0xb0 */ - volatile unsigned32 Error_Mask; /* offset 0xb4 */ - volatile unsigned32 Unimplemented_7[ 2 ]; /* offset 0xb8 */ - volatile unsigned32 Debug_Control; /* offset 0xc0 */ - volatile unsigned32 Breakpoint; /* offset 0xc4 */ - volatile unsigned32 Watchpoint; /* offset 0xc8 */ - volatile unsigned32 Unimplemented_8; /* offset 0xcc */ - volatile unsigned32 Test_Control; /* offset 0xd0 */ - volatile unsigned32 Test_Data; /* offset 0xd4 */ - volatile unsigned32 Unimplemented_9[ 2 ]; /* offset 0xd8 */ - volatile unsigned32 UART_Channel_A; /* offset 0xe0 */ - volatile unsigned32 UART_Channel_B; /* offset 0xe4 */ - volatile unsigned32 UART_Status; /* offset 0xe8 */ -} ERC32_Register_Map; - -#endif - -/* - * The following constants are intended to be used ONLY in assembly - * language files. - * - * NOTE: The intended style of usage is to load the address of MEC - * into a register and then use these as displacements from - * that register. - */ - -#ifdef ASM - -#define ERC32_MEC_CONTROL_OFFSET 0x00 -#define ERC32_MEC_SOFTWARE_RESET_OFFSET 0x04 -#define ERC32_MEC_POWER_DOWN_OFFSET 0x08 -#define ERC32_MEC_UNIMPLEMENTED_0_OFFSET 0x0C -#define ERC32_MEC_MEMORY_CONFIGURATION_OFFSET 0x10 -#define ERC32_MEC_IO_CONFIGURATION_OFFSET 0x14 -#define ERC32_MEC_WAIT_STATE_CONFIGURATION_OFFSET 0x18 -#define ERC32_MEC_UNIMPLEMENTED_1_OFFSET 0x1C -#define ERC32_MEC_MEMORY_ACCESS_0_OFFSET 0x20 -#define ERC32_MEC_MEMORY_ACCESS_1_OFFSET 0x24 -#define ERC32_MEC_UNIMPLEMENTED_2_OFFSET 0x28 -#define ERC32_MEC_INTERRUPT_SHAPE_OFFSET 0x44 -#define ERC32_MEC_INTERRUPT_PENDING_OFFSET 0x48 -#define ERC32_MEC_INTERRUPT_MASK_OFFSET 0x4C -#define ERC32_MEC_INTERRUPT_CLEAR_OFFSET 0x50 -#define ERC32_MEC_INTERRUPT_FORCE_OFFSET 0x54 -#define ERC32_MEC_UNIMPLEMENTED_3_OFFSET 0x58 -#define ERC32_MEC_WATCHDOG_PROGRAM_AND_TIMEOUT_ACKNOWLEDGE_OFFSET 0x60 -#define ERC32_MEC_WATCHDOG_TRAP_DOOR_SET_OFFSET 0x64 -#define ERC32_MEC_UNIMPLEMENTED_4_OFFSET 0x6C -#define ERC32_MEC_REAL_TIME_CLOCK_COUNTER_OFFSET 0x80 -#define ERC32_MEC_REAL_TIME_CLOCK_SCALAR_OFFSET 0x84 -#define ERC32_MEC_GENERAL_PURPOSE_TIMER_COUNTER_OFFSET 0x88 -#define ERC32_MEC_GENERAL_PURPOSE_TIMER_SCALAR_OFFSET 0x8C -#define ERC32_MEC_UNIMPLEMENTED_5_OFFSET 0x90 -#define ERC32_MEC_TIMER_CONTROL_OFFSET 0x98 -#define ERC32_MEC_UNIMPLEMENTED_6_OFFSET 0x9C -#define ERC32_MEC_SYSTEM_FAULT_STATUS_OFFSET 0xA0 -#define ERC32_MEC_FIRST_FAILING_ADDRESS_OFFSET 0xA4 -#define ERC32_MEC_FIRST_FAILING_DATA_OFFSET 0xA8 -#define ERC32_MEC_FIRST_FAILING_SYNDROME_AND_CHECK_BITS_OFFSET 0xAC -#define ERC32_MEC_ERROR_AND_RESET_STATUS_OFFSET 0xB0 -#define ERC32_MEC_ERROR_MASK_OFFSET 0xB4 -#define ERC32_MEC_UNIMPLEMENTED_7_OFFSET 0xB8 -#define ERC32_MEC_DEBUG_CONTROL_OFFSET 0xC0 -#define ERC32_MEC_BREAKPOINT_OFFSET 0xC4 -#define ERC32_MEC_WATCHPOINT_OFFSET 0xC8 -#define ERC32_MEC_UNIMPLEMENTED_8_OFFSET 0xCC -#define ERC32_MEC_TEST_CONTROL_OFFSET 0xD0 -#define ERC32_MEC_TEST_DATA_OFFSET 0xD4 -#define ERC32_MEC_UNIMPLEMENTED_9_OFFSET 0xD8 -#define ERC32_MEC_UART_CHANNEL_A_OFFSET 0xE0 -#define ERC32_MEC_UART_CHANNEL_B_OFFSET 0xE4 -#define ERC32_MEC_UART_STATUS_OFFSET 0xE8 - -#endif - -/* - * The following defines the bits in the Configuration Register. - */ - -#define ERC32_CONFIGURATION_POWER_DOWN_MASK 0x00000001 -#define ERC32_CONFIGURATION_POWER_DOWN_ALLOWED 0x00000001 -#define ERC32_CONFIGURATION_POWER_DOWN_DISABLED 0x00000000 - -#define ERC32_CONFIGURATION_SOFTWARE_RESET_MASK 0x00000002 -#define ERC32_CONFIGURATION_SOFTWARE_RESET_ALLOWED 0x00000002 -#define ERC32_CONFIGURATION_SOFTWARE_RESET_DISABLED 0x00000000 - -#define ERC32_CONFIGURATION_BUS_TIMEOUT_MASK 0x00000004 -#define ERC32_CONFIGURATION_BUS_TIMEOUT_ENABLED 0x00000004 -#define ERC32_CONFIGURATION_BUS_TIMEOUT_DISABLED 0x00000000 - -#define ERC32_CONFIGURATION_ACCESS_PROTECTION_MASK 0x00000008 -#define ERC32_CONFIGURATION_ACCESS_PROTECTION_ENABLED 0x00000008 -#define ERC32_CONFIGURATION_ACCESS_PROTECTION_DISABLED 0x00000000 - - -/* - * The following defines the bits in the Memory Configuration Register. - */ - -#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_MASK 0x00001C00 -#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_256K ( 0 << 10 ) -#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_512K ( 1 << 10 ) -#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_1MB ( 2 << 10 ) -#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_2MB ( 3 << 10 ) -#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_4MB ( 4 << 10 ) -#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_8MB ( 5 << 10 ) -#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_16MB ( 6 << 10 ) -#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_32MB ( 7 << 10 ) - -#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_MASK 0x001C0000 -#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_128K ( 0 << 18 ) -#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_256K ( 1 << 18 ) -#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_512K ( 2 << 18 ) -#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_1M ( 3 << 18 ) -#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_2M ( 4 << 18 ) -#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_4M ( 5 << 18 ) -#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_8M ( 6 << 18 ) -#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_16M ( 7 << 18 ) - -/* - * The following defines the bits in the Timer Control Register. - */ - -#define ERC32_MEC_TIMER_CONTROL_GCR 0x00000001 /* 1 = reload at 0 */ - /* 0 = stop at 0 */ -#define ERC32_MEC_TIMER_CONTROL_GCL 0x00000002 /* 1 = load and start */ - /* 0 = no function */ -#define ERC32_MEC_TIMER_CONTROL_GSE 0x00000004 /* 1 = enable counting */ - /* 0 = hold scalar and counter */ -#define ERC32_MEC_TIMER_CONTROL_GSL 0x00000008 /* 1 = load scalar and start */ - /* 0 = no function */ - -#define ERC32_MEC_TIMER_CONTROL_RTCCR 0x00000100 /* 1 = reload at 0 */ - /* 0 = stop at 0 */ -#define ERC32_MEC_TIMER_CONTROL_RTCCL 0x00000200 /* 1 = load and start */ - /* 0 = no function */ -#define ERC32_MEC_TIMER_CONTROL_RTCSE 0x00000400 /* 1 = enable counting */ - /* 0 = hold scalar and counter */ -#define ERC32_MEC_TIMER_CONTROL_RTCSL 0x00000800 /* 1 = load scalar and start */ - /* 0 = no function */ - -/* - * The following defines the bits in the UART Control Registers. - * - */ - -#define ERC32_MEC_UART_CONTROL_RTD 0x000000FF /* RX/TX data */ - -/* - * The following defines the bits in the MEC UART Control Registers. - */ - -#define ERC32_MEC_UART_STATUS_DR 0x00000001 /* Data Ready */ -#define ERC32_MEC_UART_STATUS_TSE 0x00000002 /* TX Send Register Empty */ -#define ERC32_MEC_UART_STATUS_THE 0x00000004 /* TX Hold Register Empty */ -#define ERC32_MEC_UART_STATUS_FE 0x00000010 /* RX Framing Error */ -#define ERC32_MEC_UART_STATUS_PE 0x00000020 /* RX Parity Error */ -#define ERC32_MEC_UART_STATUS_OE 0x00000040 /* RX Overrun Error */ -#define ERC32_MEC_UART_STATUS_CU 0x00000080 /* Clear Errors */ -#define ERC32_MEC_UART_STATUS_TXE 0x00000006 /* TX Empty */ -#define ERC32_MEC_UART_STATUS_CLRA 0x00000080 /* Clear UART A */ -#define ERC32_MEC_UART_STATUS_CLRB 0x00800000 /* Clear UART B */ -#define ERC32_MEC_UART_STATUS_ERRA 0x00000070 /* Error in UART A */ -#define ERC32_MEC_UART_STATUS_ERRB 0x00700000 /* Error in UART B */ - -#define ERC32_MEC_UART_STATUS_DRA (ERC32_MEC_UART_STATUS_DR << 0) -#define ERC32_MEC_UART_STATUS_TSEA (ERC32_MEC_UART_STATUS_TSE << 0) -#define ERC32_MEC_UART_STATUS_THEA (ERC32_MEC_UART_STATUS_THE << 0) -#define ERC32_MEC_UART_STATUS_FEA (ERC32_MEC_UART_STATUS_FE << 0) -#define ERC32_MEC_UART_STATUS_PEA (ERC32_MEC_UART_STATUS_PE << 0) -#define ERC32_MEC_UART_STATUS_OEA (ERC32_MEC_UART_STATUS_OE << 0) -#define ERC32_MEC_UART_STATUS_CUA (ERC32_MEC_UART_STATUS_CU << 0) -#define ERC32_MEC_UART_STATUS_TXEA (ERC32_MEC_UART_STATUS_TXE << 0) - -#define ERC32_MEC_UART_STATUS_DRB (ERC32_MEC_UART_STATUS_DR << 16) -#define ERC32_MEC_UART_STATUS_TSEB (ERC32_MEC_UART_STATUS_TSE << 16) -#define ERC32_MEC_UART_STATUS_THEB (ERC32_MEC_UART_STATUS_THE << 16) -#define ERC32_MEC_UART_STATUS_FEB (ERC32_MEC_UART_STATUS_FE << 16) -#define ERC32_MEC_UART_STATUS_PEB (ERC32_MEC_UART_STATUS_PE << 16) -#define ERC32_MEC_UART_STATUS_OEB (ERC32_MEC_UART_STATUS_OE << 16) -#define ERC32_MEC_UART_STATUS_CUB (ERC32_MEC_UART_STATUS_CU << 16) -#define ERC32_MEC_UART_STATUS_TXEB (ERC32_MEC_UART_STATUS_TXE << 16) - -#ifndef ASM - -/* - * This is used to manipulate the on-chip registers. - * - * The following symbol must be defined in the linkcmds file and point - * to the correct location. - */ - -extern ERC32_Register_Map ERC32_MEC; - -/* - * Macros to manipulate the Interrupt Clear, Interrupt Force, Interrupt Mask, - * and the Interrupt Pending Registers. - * - * NOTE: For operations which are not atomic, this code disables interrupts - * to guarantee there are no intervening accesses to the same register. - * The operations which read the register, modify the value and then - * store the result back are vulnerable. - */ - -#define ERC32_Clear_interrupt( _source ) \ - do { \ - ERC32_MEC.Interrupt_Clear = (1 << (_source)); \ - } while (0) - -#define ERC32_Force_interrupt( _source ) \ - do { \ - unsigned32 _level; \ - \ - sparc_disable_interrupts( _level ); \ - ERC32_MEC.Test_Control = ERC32_MEC.Test_Control | 0x80000; \ - ERC32_MEC.Interrupt_Force = (1 << (_source)); \ - sparc_enable_interrupts( _level ); \ - } while (0) - -#define ERC32_Is_interrupt_pending( _source ) \ - (ERC32_MEC.Interrupt_Pending & (1 << (_source))) - -#define ERC32_Is_interrupt_masked( _source ) \ - (ERC32_MEC.Interrupt_Masked & (1 << (_source))) - -#define ERC32_Mask_interrupt( _source ) \ - do { \ - unsigned32 _level; \ - \ - sparc_disable_interrupts( _level ); \ - ERC32_MEC.Interrupt_Mask |= (1 << (_source)); \ - sparc_enable_interrupts( _level ); \ - } while (0) - -#define ERC32_Unmask_interrupt( _source ) \ - do { \ - unsigned32 _level; \ - \ - sparc_disable_interrupts( _level ); \ - ERC32_MEC.Interrupt_Mask &= ~(1 << (_source)); \ - sparc_enable_interrupts( _level ); \ - } while (0) - -#define ERC32_Disable_interrupt( _source, _previous ) \ - do { \ - unsigned32 _level; \ - unsigned32 _mask = 1 << (_source); \ - \ - sparc_disable_interrupts( _level ); \ - (_previous) = ERC32_MEC.Interrupt_Mask; \ - ERC32_MEC.Interrupt_Mask = _previous | _mask; \ - sparc_enable_interrupts( _level ); \ - (_previous) &= ~_mask; \ - } while (0) - -#define ERC32_Restore_interrupt( _source, _previous ) \ - do { \ - unsigned32 _level; \ - unsigned32 _mask = 1 << (_source); \ - \ - sparc_disable_interrupts( _level ); \ - ERC32_MEC.Interrupt_Mask = \ - (ERC32_MEC.Interrupt_Mask & ~_mask) | (_previous); \ - sparc_enable_interrupts( _level ); \ - } while (0) - -/* - * The following macros attempt to hide the fact that the General Purpose - * Timer and Real Time Clock Timer share the Timer Control Register. Because - * the Timer Control Register is write only, we must mirror it in software - * and insure that writes to one timer do not alter the current settings - * and status of the other timer. - * - * This code promotes the view that the two timers are completely independent. - * By exclusively using the routines below to access the Timer Control - * Register, the application can view the system as having a General Purpose - * Timer Control Register and a Real Time Clock Timer Control Register - * rather than the single shared value. - * - * Each logical timer control register is organized as follows: - * - * D0 - Counter Reload - * 1 = reload counter at zero and restart - * 0 = stop counter at zero - * - * D1 - Counter Load - * 1 = load counter with preset value and restart - * 0 = no function - * - * D2 - Enable - * 1 = enable counting - * 0 = hold scaler and counter - * - * D3 - Scaler Load - * 1 = load scalar with preset value and restart - * 0 = no function - * - * To insure the management of the mirror is atomic, we disable interrupts - * around updates. - */ - -#define ERC32_MEC_TIMER_COUNTER_RELOAD_AT_ZERO 0x00000001 -#define ERC32_MEC_TIMER_COUNTER_STOP_AT_ZERO 0x00000000 - -#define ERC32_MEC_TIMER_COUNTER_LOAD_COUNTER 0x00000002 - -#define ERC32_MEC_TIMER_COUNTER_ENABLE_COUNTING 0x00000004 -#define ERC32_MEC_TIMER_COUNTER_DISABLE_COUNTING 0x00000000 - -#define ERC32_MEC_TIMER_COUNTER_LOAD_SCALER 0x00000008 - -#define ERC32_MEC_TIMER_COUNTER_RELOAD_MASK 0x00000001 -#define ERC32_MEC_TIMER_COUNTER_ENABLE_MASK 0x00000004 - -#define ERC32_MEC_TIMER_COUNTER_DEFINED_MASK 0x0000000F -#define ERC32_MEC_TIMER_COUNTER_CURRENT_MODE_MASK 0x00000005 - -extern unsigned32 _ERC32_MEC_Timer_Control_Mirror; - -/* - * This macros manipulate the General Purpose Timer portion of the - * Timer Control register and promote the view that there are actually - * two independent Timer Control Registers. - */ - -#define ERC32_MEC_Set_General_Purpose_Timer_Control( _value ) \ - do { \ - unsigned32 _level; \ - unsigned32 _control; \ - unsigned32 __value; \ - \ - __value = ((_value) & 0x0f); \ - sparc_disable_interrupts( _level ); \ - _control = _ERC32_MEC_Timer_Control_Mirror; \ - _control &= ERC32_MEC_TIMER_COUNTER_DEFINED_MASK << 8; \ - _ERC32_MEC_Timer_Control_Mirror = _control | _value; \ - _control &= (ERC32_MEC_TIMER_COUNTER_CURRENT_MODE_MASK << 8); \ - _control |= __value; \ - /* printf( "GPT 0x%x 0x%x 0x%x\n", _value, __value, _control ); */ \ - ERC32_MEC.Timer_Control = _control; \ - sparc_enable_interrupts( _level ); \ - } while ( 0 ) - -#define ERC32_MEC_Get_General_Purpose_Timer_Control( _value ) \ - do { \ - (_value) = _ERC32_MEC_Timer_Control_Mirror & 0xf; \ - } while ( 0 ) - -/* - * This macros manipulate the Real Timer Clock Timer portion of the - * Timer Control register and promote the view that there are actually - * two independent Timer Control Registers. - */ - -#define ERC32_MEC_Set_Real_Time_Clock_Timer_Control( _value ) \ - do { \ - unsigned32 _level; \ - unsigned32 _control; \ - unsigned32 __value; \ - \ - __value = ((_value) & 0x0f) << 8; \ - sparc_disable_interrupts( _level ); \ - _control = _ERC32_MEC_Timer_Control_Mirror; \ - _control &= ERC32_MEC_TIMER_COUNTER_DEFINED_MASK; \ - _ERC32_MEC_Timer_Control_Mirror = _control | __value; \ - _control &= ERC32_MEC_TIMER_COUNTER_CURRENT_MODE_MASK; \ - _control |= __value; \ - /* printf( "RTC 0x%x 0x%x 0x%x\n", _value, __value, _control ); */ \ - ERC32_MEC.Timer_Control = _control; \ - sparc_enable_interrupts( _level ); \ - } while ( 0 ) - -#define ERC32_MEC_Get_Real_Time_Clock_Timer_Control( _value ) \ - do { \ - (_value) = (_ERC32_MEC_Timer_Control_Mirror >> 8) & 0xf; \ - } while ( 0 ) - - -#endif /* !ASM */ - -#ifdef __cplusplus -} -#endif - -#endif /* !_INCLUDE_ERC32_h */ -/* end of include file */ - |