Import BBB sd driver files from FreeBSD.

10 files changed, 5100 insertions, 0 deletions

diff --git a/freebsd/sys/arm/ti/ti_hwmods.c b/freebsd/sys/arm/ti/ti_hwmods.c
new file mode 100644
index 00000000..0e703472
--- /dev/null
+++ b/freebsd/sys/arm/ti/ti_hwmods.c
@@ -0,0 +1,206 @@
+#include <machine/rtems-bsd-kernel-space.h>
+
+/*-
+ * Copyright (c) 2015 Oleksandr Tymoshenko <gonzo@freebsd.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+
+#include <dev/ofw/openfirm.h>
+#include <dev/ofw/ofw_bus.h>
+#include <dev/ofw/ofw_bus_subr.h>
+
+#include <machine/bus.h>
+#include <machine/fdt.h>
+
+#include <arm/ti/ti_prcm.h>
+#include <arm/ti/ti_hwmods.h>
+
+struct hwmod {
+	const char	*name;
+	int		clock_id;
+};
+
+struct hwmod ti_hwmods[] = {
+	{"i2c1",	I2C1_CLK},
+	{"i2c2",	I2C2_CLK},
+	{"i2c3",	I2C3_CLK},
+	{"i2c4",	I2C4_CLK},
+	{"i2c5",	I2C5_CLK},
+
+	{"gpio1",	GPIO1_CLK},
+	{"gpio2",	GPIO2_CLK},
+	{"gpio3",	GPIO3_CLK},
+	{"gpio4",	GPIO4_CLK},
+	{"gpio5",	GPIO5_CLK},
+	{"gpio6",	GPIO6_CLK},
+	{"gpio7",	GPIO7_CLK},
+
+	{"mmc1",	MMC1_CLK},
+	{"mmc2",	MMC2_CLK},
+	{"mmc3",	MMC3_CLK},
+	{"mmc4",	MMC4_CLK},
+	{"mmc5",	MMC5_CLK},
+	{"mmc6",	MMC6_CLK},
+
+	{"epwmss0",	PWMSS0_CLK},
+	{"epwmss1",	PWMSS1_CLK},
+	{"epwmss2",	PWMSS2_CLK},
+
+	{"spi0",	SPI0_CLK},
+	{"spi1",	SPI1_CLK},
+
+	{"timer1",	TIMER1_CLK},
+	{"timer2",	TIMER2_CLK},
+	{"timer3",	TIMER3_CLK},
+	{"timer4",	TIMER4_CLK},
+	{"timer5",	TIMER5_CLK},
+	{"timer6",	TIMER6_CLK},
+	{"timer7",	TIMER7_CLK},
+
+	{"uart1",	UART1_CLK},
+	{"uart2",	UART2_CLK},
+	{"uart3",	UART3_CLK},
+	{"uart4",	UART4_CLK},
+	{"uart5",	UART5_CLK},
+	{"uart6",	UART6_CLK},
+	{"uart7",	UART7_CLK},
+
+	{NULL,		0}
+};
+
+clk_ident_t
+ti_hwmods_get_clock(device_t dev)
+{
+	phandle_t node;
+	int len, l;
+	char *name;
+	char *buf;
+	int clk;
+	struct hwmod *hw;
+
+	if ((node = ofw_bus_get_node(dev)) == 0)
+		return (INVALID_CLK_IDENT);
+
+	if ((len = OF_getprop_alloc(node, "ti,hwmods", 1, (void**)&name)) <= 0)
+		return (INVALID_CLK_IDENT);
+
+	buf = name;
+
+	clk = INVALID_CLK_IDENT;
+	while ((len > 0) && (clk == INVALID_CLK_IDENT)) {
+		for (hw = ti_hwmods; hw->name != NULL; ++hw) {
+			if (strcmp(hw->name, name) == 0) {
+				clk = hw->clock_id;
+				break;
+			}
+		}
+
+		/* Slide to the next sub-string. */
+		l = strlen(name) + 1;
+		name += l;
+		len -= l;
+	}
+
+	if (len > 0)
+		device_printf(dev, "WARNING: more than one ti,hwmod \n");
+
+	OF_prop_free(buf);
+	return (clk);
+}
+
+int ti_hwmods_contains(device_t dev, const char *hwmod)
+{
+	phandle_t node;
+	int len, l;
+	char *name;
+	char *buf;
+	int result;
+
+	if ((node = ofw_bus_get_node(dev)) == 0)
+		return (0);
+
+	if ((len = OF_getprop_alloc(node, "ti,hwmods", 1, (void**)&name)) <= 0)
+		return (0);
+
+	buf = name;
+
+	result = 0;
+	while (len > 0) {
+		if (strcmp(name, hwmod) == 0) {
+			result = 1;
+			break;
+		}
+
+		/* Slide to the next sub-string. */
+		l = strlen(name) + 1;
+		name += l;
+		len -= l;
+	}
+
+	OF_prop_free(buf);
+
+	return (result);
+}
+
+int 
+ti_hwmods_get_unit(device_t dev, const char *hwmod)
+{
+	phandle_t node;
+	int l, len, hwmodlen, result;
+	char *name;
+	char *buf;
+
+	if ((node = ofw_bus_get_node(dev)) == 0)
+		return (0);
+
+	if ((len = OF_getprop_alloc(node, "ti,hwmods", 1, (void**)&name)) <= 0)
+		return (0);
+
+	buf = name;
+	hwmodlen = strlen(hwmod);
+	result = 0;
+	while (len > 0) {
+		if (strncmp(name, hwmod, hwmodlen) == 0) {
+                        result = (int)strtoul(name + hwmodlen, NULL, 10);
+			break;
+		}
+		/* Slide to the next sub-string. */
+		l = strlen(name) + 1;
+		name += l;
+		len -= l;
+	}
+
+	OF_prop_free(buf);
+	return (result);
+}
diff --git a/freebsd/sys/arm/ti/ti_hwmods.h b/freebsd/sys/arm/ti/ti_hwmods.h
new file mode 100644
index 00000000..c236cc0d
--- /dev/null
+++ b/freebsd/sys/arm/ti/ti_hwmods.h
@@ -0,0 +1,37 @@
+/*-
+ * Copyright (c) 2015 Oleksandr Tymoshenko <gonzo@freebsd.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+#ifndef _TI_HWMODS_H_
+#define _TI_HWMODS_H_
+
+clk_ident_t ti_hwmods_get_clock(device_t dev);
+int ti_hwmods_contains(device_t dev, const char *hwmod);
+
+/* Returns the N from "hwmodN" in the ti,hwmods property; 0 on failure. */
+int ti_hwmods_get_unit(device_t dev, const char *hwmod);
+
+#endif /* _TI_HWMODS_H_ */
diff --git a/freebsd/sys/arm/ti/ti_sdhci.c b/freebsd/sys/arm/ti/ti_sdhci.c
new file mode 100644
index 00000000..94096fd6
--- /dev/null
+++ b/freebsd/sys/arm/ti/ti_sdhci.c
@@ -0,0 +1,735 @@
+#include <machine/rtems-bsd-kernel-space.h>
+
+/*-
+ * Copyright (c) 2013 Ian Lepore <ian@freebsd.org>
+ * Copyright (c) 2011 Ben Gray <ben.r.gray@gmail.com>.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/gpio.h>
+#include <sys/kernel.h>
+#include <sys/malloc.h>
+#include <sys/module.h>
+#include <rtems/bsd/sys/resource.h>
+#include <sys/rman.h>
+#include <sys/sysctl.h>
+#include <sys/taskqueue.h>
+
+#include <machine/bus.h>
+#include <machine/resource.h>
+#include <machine/intr.h>
+
+#include <dev/ofw/ofw_bus.h>
+#include <dev/ofw/ofw_bus_subr.h>
+
+#include <dev/mmc/bridge.h>
+#include <dev/mmc/mmcreg.h>
+#include <dev/mmc/mmcbrvar.h>
+
+#include <dev/sdhci/sdhci.h>
+#include <dev/sdhci/sdhci_fdt_gpio.h>
+#include <rtems/bsd/local/sdhci_if.h>
+
+#include <arm/ti/ti_cpuid.h>
+#include <arm/ti/ti_prcm.h>
+#include <arm/ti/ti_hwmods.h>
+#include <rtems/bsd/local/gpio_if.h>
+
+struct ti_sdhci_softc {
+	device_t		dev;
+	struct sdhci_fdt_gpio * gpio;
+	struct resource *	mem_res;
+	struct resource *	irq_res;
+	void *			intr_cookie;
+	struct sdhci_slot	slot;
+	clk_ident_t		mmchs_clk_id;
+	uint32_t		mmchs_reg_off;
+	uint32_t		sdhci_reg_off;
+	uint32_t		baseclk_hz;
+	uint32_t		cmd_and_mode;
+	uint32_t		sdhci_clkdiv;
+	boolean_t		disable_highspeed;
+	boolean_t		force_card_present;
+	boolean_t		disable_readonly;
+};
+
+/*
+ * Table of supported FDT compat strings.
+ *
+ * Note that "ti,mmchs" is our own invention, and should be phased out in favor
+ * of the documented names.
+ *
+ * Note that vendor Beaglebone dtsi files use "ti,omap3-hsmmc" for the am335x.
+ */
+static struct ofw_compat_data compat_data[] = {
+	{"ti,omap3-hsmmc",	1},
+	{"ti,omap4-hsmmc",	1},
+	{"ti,mmchs",		1},
+	{NULL,		 	0},
+};
+
+/*
+ * The MMCHS hardware has a few control and status registers at the beginning of
+ * the device's memory map, followed by the standard sdhci register block.
+ * Different SoCs have the register blocks at different offsets from the
+ * beginning of the device.  Define some constants to map out the registers we
+ * access, and the various per-SoC offsets.  The SDHCI_REG_OFFSET is how far
+ * beyond the MMCHS block the SDHCI block is found; it's the same on all SoCs.
+ */
+#define	OMAP3_MMCHS_REG_OFFSET		0x000
+#define	OMAP4_MMCHS_REG_OFFSET		0x100
+#define	AM335X_MMCHS_REG_OFFSET		0x100
+#define	SDHCI_REG_OFFSET		0x100
+
+#define	MMCHS_SYSCONFIG			0x010
+#define	  MMCHS_SYSCONFIG_RESET		  (1 << 1)
+#define	MMCHS_SYSSTATUS			0x014
+#define	  MMCHS_SYSSTATUS_RESETDONE	  (1 << 0)
+#define	MMCHS_CON			0x02C
+#define	  MMCHS_CON_DW8			  (1 << 5)
+#define	  MMCHS_CON_DVAL_8_4MS		  (3 << 9)
+#define	  MMCHS_CON_OD			  (1 << 0)
+#define MMCHS_SYSCTL			0x12C
+#define   MMCHS_SYSCTL_CLKD_MASK	   0x3FF
+#define   MMCHS_SYSCTL_CLKD_SHIFT	   6
+#define	MMCHS_SD_CAPA			0x140
+#define	  MMCHS_SD_CAPA_VS18		  (1 << 26)
+#define	  MMCHS_SD_CAPA_VS30		  (1 << 25)
+#define	  MMCHS_SD_CAPA_VS33		  (1 << 24)
+
+static inline uint32_t
+ti_mmchs_read_4(struct ti_sdhci_softc *sc, bus_size_t off)
+{
+
+	return (bus_read_4(sc->mem_res, off + sc->mmchs_reg_off));
+}
+
+static inline void
+ti_mmchs_write_4(struct ti_sdhci_softc *sc, bus_size_t off, uint32_t val)
+{
+
+	bus_write_4(sc->mem_res, off + sc->mmchs_reg_off, val);
+}
+
+static inline uint32_t
+RD4(struct ti_sdhci_softc *sc, bus_size_t off)
+{
+
+	return (bus_read_4(sc->mem_res, off + sc->sdhci_reg_off));
+}
+
+static inline void
+WR4(struct ti_sdhci_softc *sc, bus_size_t off, uint32_t val)
+{
+
+	bus_write_4(sc->mem_res, off + sc->sdhci_reg_off, val);
+}
+
+static uint8_t
+ti_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off)
+{
+	struct ti_sdhci_softc *sc = device_get_softc(dev);
+
+	return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xff);
+}
+
+static uint16_t
+ti_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off)
+{
+	struct ti_sdhci_softc *sc = device_get_softc(dev);
+	uint32_t clkdiv, val32;
+
+	/*
+	 * The MMCHS hardware has a non-standard interpretation of the sdclock
+	 * divisor bits.  It uses the same bit positions as SDHCI 3.0 (15..6)
+	 * but doesn't split them into low:high fields.  Instead they're a
+	 * single number in the range 0..1023 and the number is exactly the
+	 * clock divisor (with 0 and 1 both meaning divide by 1).  The SDHCI
+	 * driver code expects a v2.0 or v3.0 divisor.  The shifting and masking
+	 * here extracts the MMCHS representation from the hardware word, cleans
+	 * those bits out, applies the 2N adjustment, and plugs the result into
+	 * the bit positions for the 2.0 or 3.0 divisor in the returned register
+	 * value. The ti_sdhci_write_2() routine performs the opposite
+	 * transformation when the SDHCI driver writes to the register.
+	 */
+	if (off == SDHCI_CLOCK_CONTROL) {
+		val32 = RD4(sc, SDHCI_CLOCK_CONTROL);
+		clkdiv = ((val32 >> MMCHS_SYSCTL_CLKD_SHIFT) &
+		    MMCHS_SYSCTL_CLKD_MASK) / 2;
+		val32 &= ~(MMCHS_SYSCTL_CLKD_MASK << MMCHS_SYSCTL_CLKD_SHIFT);
+		val32 |= (clkdiv & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT;
+		if (slot->version >= SDHCI_SPEC_300)
+			val32 |= ((clkdiv >> SDHCI_DIVIDER_MASK_LEN) &
+			    SDHCI_DIVIDER_HI_MASK) << SDHCI_DIVIDER_HI_SHIFT;
+		return (val32 & 0xffff);
+	}
+
+	/*
+	 * Standard 32-bit handling of command and transfer mode.
+	 */
+	if (off == SDHCI_TRANSFER_MODE) {
+		return (sc->cmd_and_mode >> 16);
+	} else if (off == SDHCI_COMMAND_FLAGS) {
+		return (sc->cmd_and_mode & 0x0000ffff);
+	}
+
+	return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xffff);
+}
+
+static uint32_t
+ti_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off)
+{
+	struct ti_sdhci_softc *sc = device_get_softc(dev);
+	uint32_t val32;
+
+	val32 = RD4(sc, off);
+
+	/*
+	 * If we need to disallow highspeed mode due to the OMAP4 erratum, strip
+	 * that flag from the returned capabilities.
+	 */
+	if (off == SDHCI_CAPABILITIES && sc->disable_highspeed)
+		val32 &= ~SDHCI_CAN_DO_HISPD;
+
+	/*
+	 * Force the card-present state if necessary.
+	 */
+	if (off == SDHCI_PRESENT_STATE && sc->force_card_present)
+		val32 |= SDHCI_CARD_PRESENT;
+
+	return (val32);
+}
+
+static void
+ti_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
+    uint32_t *data, bus_size_t count)
+{
+	struct ti_sdhci_softc *sc = device_get_softc(dev);
+
+	bus_read_multi_4(sc->mem_res, off + sc->sdhci_reg_off, data, count);
+}
+
+static void
+ti_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, 
+    uint8_t val)
+{
+	struct ti_sdhci_softc *sc = device_get_softc(dev);
+	uint32_t val32;
+
+	val32 = RD4(sc, off & ~3);
+	val32 &= ~(0xff << (off & 3) * 8);
+	val32 |= (val << (off & 3) * 8);
+
+	WR4(sc, off & ~3, val32);
+}
+
+static void
+ti_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, 
+    uint16_t val)
+{
+	struct ti_sdhci_softc *sc = device_get_softc(dev);
+	uint32_t clkdiv, val32;
+
+	/*
+	 * Translate between the hardware and SDHCI 2.0 or 3.0 representations
+	 * of the clock divisor.  See the comments in ti_sdhci_read_2() for
+	 * details.
+	 */
+	if (off == SDHCI_CLOCK_CONTROL) {
+		clkdiv = (val >> SDHCI_DIVIDER_SHIFT) & SDHCI_DIVIDER_MASK;
+		if (slot->version >= SDHCI_SPEC_300)
+			clkdiv |= ((val >> SDHCI_DIVIDER_HI_SHIFT) &
+			    SDHCI_DIVIDER_HI_MASK) << SDHCI_DIVIDER_MASK_LEN;
+		clkdiv *= 2;
+		if (clkdiv > MMCHS_SYSCTL_CLKD_MASK)
+			clkdiv = MMCHS_SYSCTL_CLKD_MASK;
+		val32 = RD4(sc, SDHCI_CLOCK_CONTROL);
+		val32 &= 0xffff0000;
+		val32 |= val & ~(MMCHS_SYSCTL_CLKD_MASK <<
+		    MMCHS_SYSCTL_CLKD_SHIFT);
+		val32 |= clkdiv << MMCHS_SYSCTL_CLKD_SHIFT;
+		WR4(sc, SDHCI_CLOCK_CONTROL, val32);
+		return;
+	}
+
+	/*
+	 * Standard 32-bit handling of command and transfer mode.
+	 */
+	if (off == SDHCI_TRANSFER_MODE) {
+		sc->cmd_and_mode = (sc->cmd_and_mode & 0xffff0000) |
+		    ((uint32_t)val & 0x0000ffff);
+		return;
+	} else if (off == SDHCI_COMMAND_FLAGS) {
+		sc->cmd_and_mode = (sc->cmd_and_mode & 0x0000ffff) |
+		    ((uint32_t)val << 16);
+		WR4(sc, SDHCI_TRANSFER_MODE, sc->cmd_and_mode);
+		return;
+	}
+
+	val32 = RD4(sc, off & ~3);
+	val32 &= ~(0xffff << (off & 3) * 8);
+	val32 |= ((val & 0xffff) << (off & 3) * 8);
+	WR4(sc, off & ~3, val32);	
+}
+
+static void
+ti_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 
+    uint32_t val)
+{
+	struct ti_sdhci_softc *sc = device_get_softc(dev);
+
+	WR4(sc, off, val);
+}
+
+static void
+ti_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
+    uint32_t *data, bus_size_t count)
+{
+	struct ti_sdhci_softc *sc = device_get_softc(dev);
+
+	bus_write_multi_4(sc->mem_res, off + sc->sdhci_reg_off, data, count);
+}
+
+static void
+ti_sdhci_intr(void *arg)
+{
+	struct ti_sdhci_softc *sc = arg;
+
+	sdhci_generic_intr(&sc->slot);
+}
+
+static int
+ti_sdhci_update_ios(device_t brdev, device_t reqdev)
+{
+	struct ti_sdhci_softc *sc = device_get_softc(brdev);
+	struct sdhci_slot *slot;
+	struct mmc_ios *ios;
+	uint32_t val32, newval32;
+
+	slot = device_get_ivars(reqdev);
+	ios = &slot->host.ios;
+
+	/*
+	 * There is an 8-bit-bus bit in the MMCHS control register which, when
+	 * set, overrides the 1 vs 4 bit setting in the standard SDHCI
+	 * registers.  Set that bit first according to whether an 8-bit bus is
+	 * requested, then let the standard driver handle everything else.
+	 */
+	val32 = ti_mmchs_read_4(sc, MMCHS_CON);
+	newval32  = val32;
+
+	if (ios->bus_width == bus_width_8)
+		newval32 |= MMCHS_CON_DW8;
+	else
+		newval32 &= ~MMCHS_CON_DW8;
+
+	if (ios->bus_mode == opendrain)
+		newval32 |= MMCHS_CON_OD;
+	else /* if (ios->bus_mode == pushpull) */
+		newval32 &= ~MMCHS_CON_OD;
+
+	if (newval32 != val32)
+		ti_mmchs_write_4(sc, MMCHS_CON, newval32);
+
+	return (sdhci_generic_update_ios(brdev, reqdev));
+}
+
+static int
+ti_sdhci_get_ro(device_t brdev, device_t reqdev)
+{
+	struct ti_sdhci_softc *sc = device_get_softc(brdev);
+
+	if (sc->disable_readonly)
+		return (0);
+
+	return (sdhci_fdt_gpio_get_readonly(sc->gpio));
+}
+
+static bool
+ti_sdhci_get_card_present(device_t dev, struct sdhci_slot *slot)
+{
+	struct ti_sdhci_softc *sc = device_get_softc(dev);
+
+	return (sdhci_fdt_gpio_get_present(sc->gpio));
+}
+
+static int
+ti_sdhci_detach(device_t dev)
+{
+
+	/* sdhci_fdt_gpio_teardown(sc->gpio); */
+
+	return (EBUSY);
+}
+
+static void
+ti_sdhci_hw_init(device_t dev)
+{
+	struct ti_sdhci_softc *sc = device_get_softc(dev);
+	uint32_t regval;
+	unsigned long timeout;
+
+	/* Enable the controller and interface/functional clocks */
+	if (ti_prcm_clk_enable(sc->mmchs_clk_id) != 0) {
+		device_printf(dev, "Error: failed to enable MMC clock\n");
+		return;
+	}
+
+	/* Get the frequency of the source clock */
+	if (ti_prcm_clk_get_source_freq(sc->mmchs_clk_id,
+	    &sc->baseclk_hz) != 0) {
+		device_printf(dev, "Error: failed to get source clock freq\n");
+		return;
+	}
+
+	/* Issue a softreset to the controller */
+	ti_mmchs_write_4(sc, MMCHS_SYSCONFIG, MMCHS_SYSCONFIG_RESET);
+	timeout = 1000;
+	while (!(ti_mmchs_read_4(sc, MMCHS_SYSSTATUS) &
+	    MMCHS_SYSSTATUS_RESETDONE)) {
+		if (--timeout == 0) {
+			device_printf(dev,
+			    "Error: Controller reset operation timed out\n");
+			break;
+		}
+		DELAY(100);
+	}
+
+	/*
+	 * Reset the command and data state machines and also other aspects of
+	 * the controller such as bus clock and power.
+	 *
+	 * If we read the software reset register too fast after writing it we
+	 * can get back a zero that means the reset hasn't started yet rather
+	 * than that the reset is complete. Per TI recommendations, work around
+	 * it by reading until we see the reset bit asserted, then read until
+	 * it's clear. We also set the SDHCI_QUIRK_WAITFOR_RESET_ASSERTED quirk
+	 * so that the main sdhci driver uses this same logic in its resets.
+	 */
+	ti_sdhci_write_1(dev, NULL, SDHCI_SOFTWARE_RESET, SDHCI_RESET_ALL);
+	timeout = 10000;
+	while ((ti_sdhci_read_1(dev, NULL, SDHCI_SOFTWARE_RESET) &
+	    SDHCI_RESET_ALL) != SDHCI_RESET_ALL) {
+		if (--timeout == 0) {
+			break;
+		}
+		DELAY(1);
+	}
+	timeout = 10000;
+	while ((ti_sdhci_read_1(dev, NULL, SDHCI_SOFTWARE_RESET) &
+	    SDHCI_RESET_ALL)) {
+		if (--timeout == 0) {
+			device_printf(dev,
+			    "Error: Software reset operation timed out\n");
+			break;
+		}
+		DELAY(100);
+	}
+
+	/*
+	 * The attach() routine has examined fdt data and set flags in
+	 * slot.host.caps to reflect what voltages we can handle.  Set those
+	 * values in the CAPA register.  The manual says that these values can
+	 * only be set once, "before initialization" whatever that means, and
+	 * that they survive a reset.  So maybe doing this will be a no-op if
+	 * u-boot has already initialized the hardware.
+	 */
+	regval = ti_mmchs_read_4(sc, MMCHS_SD_CAPA);
+	if (sc->slot.host.caps & MMC_OCR_LOW_VOLTAGE)
+		regval |= MMCHS_SD_CAPA_VS18;
+	if (sc->slot.host.caps & (MMC_OCR_290_300 | MMC_OCR_300_310))
+		regval |= MMCHS_SD_CAPA_VS30;
+	ti_mmchs_write_4(sc, MMCHS_SD_CAPA, regval);
+
+	/* Set initial host configuration (1-bit, std speed, pwr off). */
+	ti_sdhci_write_1(dev, NULL, SDHCI_HOST_CONTROL, 0);
+	ti_sdhci_write_1(dev, NULL, SDHCI_POWER_CONTROL, 0);
+
+	/* Set the initial controller configuration. */
+	ti_mmchs_write_4(sc, MMCHS_CON, MMCHS_CON_DVAL_8_4MS);
+}
+
+static int
+ti_sdhci_attach(device_t dev)
+{
+	struct ti_sdhci_softc *sc = device_get_softc(dev);
+	int rid, err;
+	pcell_t prop;
+	phandle_t node;
+
+	sc->dev = dev;
+
+	/*
+	 * Get the MMCHS device id from FDT.  If it's not there use the newbus
+	 * unit number (which will work as long as the devices are in order and
+	 * none are skipped in the fdt).  Note that this is a property we made
+	 * up and added in freebsd, it doesn't exist in the published bindings.
+	 */
+	node = ofw_bus_get_node(dev);
+	sc->mmchs_clk_id = ti_hwmods_get_clock(dev);
+	if (sc->mmchs_clk_id == INVALID_CLK_IDENT) {
+		device_printf(dev, "failed to get clock based on hwmods property\n");
+	}
+
+	/*
+	 * The hardware can inherently do dual-voltage (1p8v, 3p0v) on the first
+	 * device, and only 1p8v on other devices unless an external transceiver
+	 * is used.  The only way we could know about a transceiver is fdt data.
+	 * Note that we have to do this before calling ti_sdhci_hw_init() so
+	 * that it can set the right values in the CAPA register, which can only
+	 * be done once and never reset.
+	 */
+	sc->slot.host.caps |= MMC_OCR_LOW_VOLTAGE;
+	if (sc->mmchs_clk_id == MMC1_CLK || OF_hasprop(node, "ti,dual-volt")) {
+		sc->slot.host.caps |= MMC_OCR_290_300 | MMC_OCR_300_310;
+	}
+
+	/*
+	 * Set the offset from the device's memory start to the MMCHS registers.
+	 * Also for OMAP4 disable high speed mode due to erratum ID i626.
+	 */
+	switch (ti_chip()) {
+#ifdef SOC_OMAP4
+	case CHIP_OMAP_4:
+		sc->mmchs_reg_off = OMAP4_MMCHS_REG_OFFSET;
+		sc->disable_highspeed = true;
+		break;
+#endif
+#ifdef SOC_TI_AM335X
+	case CHIP_AM335X:
+		sc->mmchs_reg_off = AM335X_MMCHS_REG_OFFSET;
+		break;
+#endif
+	default:
+		panic("Unknown OMAP device\n");
+	}
+
+	/*
+	 * The standard SDHCI registers are at a fixed offset (the same on all
+	 * SoCs) beyond the MMCHS registers.
+	 */
+	sc->sdhci_reg_off = sc->mmchs_reg_off + SDHCI_REG_OFFSET;
+
+	/* Resource setup. */
+	rid = 0;
+	sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
+	    RF_ACTIVE);
+	if (!sc->mem_res) {
+		device_printf(dev, "cannot allocate memory window\n");
+		err = ENXIO;
+		goto fail;
+	}
+
+	rid = 0;
+	sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
+	    RF_ACTIVE);
+	if (!sc->irq_res) {
+		device_printf(dev, "cannot allocate interrupt\n");
+		err = ENXIO;
+		goto fail;
+	}
+
+	if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
+	    NULL, ti_sdhci_intr, sc, &sc->intr_cookie)) {
+		device_printf(dev, "cannot setup interrupt handler\n");
+		err = ENXIO;
+		goto fail;
+	}
+
+	/*
+	 * Set up handling of card-detect and write-protect gpio lines.
+	 *
+	 * If there is no write protect info in the fdt data, fall back to the
+	 * historical practice of assuming that the card is writable.  This
+	 * works around bad fdt data from the upstream source.  The alternative
+	 * would be to trust the sdhci controller's PRESENT_STATE register WP
+	 * bit, but it may say write protect is in effect when it's not if the
+	 * pinmux setup doesn't route the WP signal into the sdchi block.
+	 */
+	sc->gpio = sdhci_fdt_gpio_setup(sc->dev, &sc->slot);
+
+	if (!OF_hasprop(node, "wp-gpios") && !OF_hasprop(node, "wp-disable"))
+		sc->disable_readonly = true;
+
+	/* Initialise the MMCHS hardware. */
+	ti_sdhci_hw_init(dev);
+
+	/*
+	 * The capabilities register can only express base clock frequencies in
+	 * the range of 0-63MHz for a v2.0 controller.  Since our clock runs
+	 * faster than that, the hardware sets the frequency to zero in the
+	 * register.  When the register contains zero, the sdhci driver expects
+	 * slot.max_clk to already have the right value in it.
+	 */
+	sc->slot.max_clk = sc->baseclk_hz;
+
+	/*
+	 * The MMCHS timeout counter is based on the output sdclock.  Tell the
+	 * sdhci driver to recalculate the timeout clock whenever the output
+	 * sdclock frequency changes.
+	 */
+	sc->slot.quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK;
+
+	/*
+	 * The MMCHS hardware shifts the 136-bit response data (in violation of
+	 * the spec), so tell the sdhci driver not to do the same in software.
+	 */
+	sc->slot.quirks |= SDHCI_QUIRK_DONT_SHIFT_RESPONSE;
+
+	/*
+	 * Reset bits are broken, have to wait to see the bits asserted
+	 * before waiting to see them de-asserted.
+	 */
+	sc->slot.quirks |= SDHCI_QUIRK_WAITFOR_RESET_ASSERTED;
+	
+	/*
+	 * The controller waits for busy responses.
+	 */
+	sc->slot.quirks |= SDHCI_QUIRK_WAIT_WHILE_BUSY;
+
+	/*
+	 * DMA is not really broken, I just haven't implemented it yet.
+	 */
+	sc->slot.quirks |= SDHCI_QUIRK_BROKEN_DMA;
+
+	/*
+	 *  Set up the hardware and go.  Note that this sets many of the
+	 *  slot.host.* fields, so we have to do this before overriding any of
+	 *  those values based on fdt data, below.
+	 */
+	sdhci_init_slot(dev, &sc->slot, 0);
+
+	/*
+	 * The SDHCI controller doesn't realize it, but we can support 8-bit
+	 * even though we're not a v3.0 controller.  If there's an fdt bus-width
+	 * property, honor it.
+	 */
+	if (OF_getencprop(node, "bus-width", &prop, sizeof(prop)) > 0) {
+		sc->slot.host.caps &= ~(MMC_CAP_4_BIT_DATA | 
+		    MMC_CAP_8_BIT_DATA);
+		switch (prop) {
+		case 8:
+			sc->slot.host.caps |= MMC_CAP_8_BIT_DATA;
+			/* FALLTHROUGH */
+		case 4:
+			sc->slot.host.caps |= MMC_CAP_4_BIT_DATA;
+			break;
+		case 1:
+			break;
+		default:
+			device_printf(dev, "Bad bus-width value %u\n", prop);
+			break;
+		}
+	}
+
+	/*
+	 * If the slot is flagged with the non-removable property, set our flag
+	 * to always force the SDHCI_CARD_PRESENT bit on.
+	 */
+	node = ofw_bus_get_node(dev);
+	if (OF_hasprop(node, "non-removable"))
+		sc->force_card_present = true;
+
+	bus_generic_probe(dev);
+	bus_generic_attach(dev);
+
+	sdhci_start_slot(&sc->slot);
+
+	return (0);
+
+fail:
+	if (sc->intr_cookie)
+		bus_teardown_intr(dev, sc->irq_res, sc->intr_cookie);
+	if (sc->irq_res)
+		bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res);
+	if (sc->mem_res)
+		bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res);
+
+	return (err);
+}
+
+static int
+ti_sdhci_probe(device_t dev)
+{
+
+	if (!ofw_bus_status_okay(dev))
+		return (ENXIO);
+
+	if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) {
+		device_set_desc(dev, "TI MMCHS (SDHCI 2.0)");
+		return (BUS_PROBE_DEFAULT);
+	}
+
+	return (ENXIO);
+}
+
+static device_method_t ti_sdhci_methods[] = {
+	/* Device interface */
+	DEVMETHOD(device_probe,		ti_sdhci_probe),
+	DEVMETHOD(device_attach,	ti_sdhci_attach),
+	DEVMETHOD(device_detach,	ti_sdhci_detach),
+
+	/* Bus interface */
+	DEVMETHOD(bus_read_ivar,	sdhci_generic_read_ivar),
+	DEVMETHOD(bus_write_ivar,	sdhci_generic_write_ivar),
+
+	/* MMC bridge interface */
+	DEVMETHOD(mmcbr_update_ios,	ti_sdhci_update_ios),
+	DEVMETHOD(mmcbr_request,	sdhci_generic_request),
+	DEVMETHOD(mmcbr_get_ro,		ti_sdhci_get_ro),
+	DEVMETHOD(mmcbr_acquire_host,	sdhci_generic_acquire_host),
+	DEVMETHOD(mmcbr_release_host,	sdhci_generic_release_host),
+
+	/* SDHCI registers accessors */
+	DEVMETHOD(sdhci_read_1,		ti_sdhci_read_1),
+	DEVMETHOD(sdhci_read_2,		ti_sdhci_read_2),
+	DEVMETHOD(sdhci_read_4,		ti_sdhci_read_4),
+	DEVMETHOD(sdhci_read_multi_4,	ti_sdhci_read_multi_4),
+	DEVMETHOD(sdhci_write_1,	ti_sdhci_write_1),
+	DEVMETHOD(sdhci_write_2,	ti_sdhci_write_2),
+	DEVMETHOD(sdhci_write_4,	ti_sdhci_write_4),
+	DEVMETHOD(sdhci_write_multi_4,	ti_sdhci_write_multi_4),
+	DEVMETHOD(sdhci_get_card_present, ti_sdhci_get_card_present),
+
+	DEVMETHOD_END
+};
+
+static devclass_t ti_sdhci_devclass;
+
+static driver_t ti_sdhci_driver = {
+	"sdhci_ti",
+	ti_sdhci_methods,
+	sizeof(struct ti_sdhci_softc),
+};
+
+DRIVER_MODULE(sdhci_ti, simplebus, ti_sdhci_driver, ti_sdhci_devclass, NULL,
+    NULL);
+MODULE_DEPEND(sdhci_ti, sdhci, 1, 1, 1);
+MMC_DECLARE_BRIDGE(sdhci_ti);
diff --git a/freebsd/sys/dev/gpio/gpiobus.c b/freebsd/sys/dev/gpio/gpiobus.c
new file mode 100644
index 00000000..bbe8fc6c
--- /dev/null
+++ b/freebsd/sys/dev/gpio/gpiobus.c
@@ -0,0 +1,862 @@
+#include <machine/rtems-bsd-kernel-space.h>
+
+/*-
+ * Copyright (c) 2009 Oleksandr Tymoshenko <gonzo@freebsd.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/gpio.h>
+#ifdef INTRNG
+#include <sys/intr.h>
+#endif
+#include <sys/kernel.h>
+#include <sys/malloc.h>
+#include <sys/module.h>
+
+#include <dev/gpio/gpiobusvar.h>
+
+#include <rtems/bsd/local/gpiobus_if.h>
+
+#undef GPIOBUS_DEBUG
+#ifdef GPIOBUS_DEBUG
+#define	dprintf printf
+#else
+#define	dprintf(x, arg...)
+#endif
+
+static void gpiobus_print_pins(struct gpiobus_ivar *, char *, size_t);
+static int gpiobus_parse_pins(struct gpiobus_softc *, device_t, int);
+static int gpiobus_probe(device_t);
+static int gpiobus_attach(device_t);
+static int gpiobus_detach(device_t);
+static int gpiobus_suspend(device_t);
+static int gpiobus_resume(device_t);
+static void gpiobus_probe_nomatch(device_t, device_t);
+static int gpiobus_print_child(device_t, device_t);
+static int gpiobus_child_location_str(device_t, device_t, char *, size_t);
+static int gpiobus_child_pnpinfo_str(device_t, device_t, char *, size_t);
+static device_t gpiobus_add_child(device_t, u_int, const char *, int);
+static void gpiobus_hinted_child(device_t, const char *, int);
+
+/*
+ * GPIOBUS interface
+ */
+static int gpiobus_acquire_bus(device_t, device_t, int);
+static void gpiobus_release_bus(device_t, device_t);
+static int gpiobus_pin_setflags(device_t, device_t, uint32_t, uint32_t);
+static int gpiobus_pin_getflags(device_t, device_t, uint32_t, uint32_t*);
+static int gpiobus_pin_getcaps(device_t, device_t, uint32_t, uint32_t*);
+static int gpiobus_pin_set(device_t, device_t, uint32_t, unsigned int);
+static int gpiobus_pin_get(device_t, device_t, uint32_t, unsigned int*);
+static int gpiobus_pin_toggle(device_t, device_t, uint32_t);
+
+/*
+ * XXX -> Move me to better place - gpio_subr.c?
+ * Also, this function must be changed when interrupt configuration
+ * data will be moved into struct resource.
+ */
+#ifdef INTRNG
+
+struct resource *
+gpio_alloc_intr_resource(device_t consumer_dev, int *rid, u_int alloc_flags,
+    gpio_pin_t pin, uint32_t intr_mode)
+{
+	u_int irq;
+	struct intr_map_data_gpio *gpio_data;
+	struct resource *res;
+
+	gpio_data = (struct intr_map_data_gpio *)intr_alloc_map_data(
+	    INTR_MAP_DATA_GPIO, sizeof(*gpio_data), M_WAITOK | M_ZERO);
+	gpio_data->gpio_pin_num = pin->pin;
+	gpio_data->gpio_pin_flags = pin->flags;
+	gpio_data->gpio_intr_mode = intr_mode;
+
+	irq = intr_map_irq(pin->dev, 0, (struct intr_map_data *)gpio_data);
+	res = bus_alloc_resource(consumer_dev, SYS_RES_IRQ, rid, irq, irq, 1,
+	    alloc_flags);
+	if (res == NULL) {
+		intr_free_intr_map_data((struct intr_map_data *)gpio_data);
+		return (NULL);
+	}
+	rman_set_virtual(res, gpio_data);
+	return (res);
+}
+#else
+struct resource *
+gpio_alloc_intr_resource(device_t consumer_dev, int *rid, u_int alloc_flags,
+    gpio_pin_t pin, uint32_t intr_mode)
+{
+
+	return (NULL);
+}
+#endif
+
+int
+gpio_check_flags(uint32_t caps, uint32_t flags)
+{
+
+	/* Filter unwanted flags. */
+	flags &= caps;
+
+	/* Cannot mix input/output together. */
+	if (flags & GPIO_PIN_INPUT && flags & GPIO_PIN_OUTPUT)
+		return (EINVAL);
+	/* Cannot mix pull-up/pull-down together. */
+	if (flags & GPIO_PIN_PULLUP && flags & GPIO_PIN_PULLDOWN)
+		return (EINVAL);
+
+	return (0);
+}
+
+static void
+gpiobus_print_pins(struct gpiobus_ivar *devi, char *buf, size_t buflen)
+{
+	char tmp[128];
+	int i, range_start, range_stop, need_coma;
+
+	if (devi->npins == 0)
+		return;
+
+	need_coma = 0;
+	range_start = range_stop = devi->pins[0];
+	for (i = 1; i < devi->npins; i++) {
+		if (devi->pins[i] != (range_stop + 1)) {
+			if (need_coma)
+				strlcat(buf, ",", buflen);
+			memset(tmp, 0, sizeof(tmp));
+			if (range_start != range_stop)
+				snprintf(tmp, sizeof(tmp) - 1, "%d-%d",
+				    range_start, range_stop);
+			else
+				snprintf(tmp, sizeof(tmp) - 1, "%d",
+				    range_start);
+			strlcat(buf, tmp, buflen);
+
+			range_start = range_stop = devi->pins[i];
+			need_coma = 1;
+		}
+		else
+			range_stop++;
+	}
+
+	if (need_coma)
+		strlcat(buf, ",", buflen);
+	memset(tmp, 0, sizeof(tmp));
+	if (range_start != range_stop)
+		snprintf(tmp, sizeof(tmp) - 1, "%d-%d",
+		    range_start, range_stop);
+	else
+		snprintf(tmp, sizeof(tmp) - 1, "%d",
+		    range_start);
+	strlcat(buf, tmp, buflen);
+}
+
+device_t
+gpiobus_attach_bus(device_t dev)
+{
+	device_t busdev;
+
+	busdev = device_add_child(dev, "gpiobus", -1);
+	if (busdev == NULL)
+		return (NULL);
+	if (device_add_child(dev, "gpioc", -1) == NULL) {
+		device_delete_child(dev, busdev);
+		return (NULL);
+	}
+#ifdef FDT
+	ofw_gpiobus_register_provider(dev);
+#endif
+	bus_generic_attach(dev);
+
+	return (busdev);
+}
+
+int
+gpiobus_detach_bus(device_t dev)
+{
+	int err;
+
+#ifdef FDT
+	ofw_gpiobus_unregister_provider(dev);
+#endif
+	err = bus_generic_detach(dev);
+	if (err != 0)
+		return (err);
+
+	return (device_delete_children(dev));
+}
+
+int
+gpiobus_init_softc(device_t dev)
+{
+	struct gpiobus_softc *sc;
+
+	sc = GPIOBUS_SOFTC(dev);
+	sc->sc_busdev = dev;
+	sc->sc_dev = device_get_parent(dev);
+	sc->sc_intr_rman.rm_type = RMAN_ARRAY;
+	sc->sc_intr_rman.rm_descr = "GPIO Interrupts";
+	if (rman_init(&sc->sc_intr_rman) != 0 ||
+	    rman_manage_region(&sc->sc_intr_rman, 0, ~0) != 0)
+		panic("%s: failed to set up rman.", __func__);
+
+	if (GPIO_PIN_MAX(sc->sc_dev, &sc->sc_npins) != 0)
+		return (ENXIO);
+
+	KASSERT(sc->sc_npins >= 0, ("GPIO device with no pins"));
+
+	/* Pins = GPIO_PIN_MAX() + 1 */
+	sc->sc_npins++;
+
+	sc->sc_pins = malloc(sizeof(*sc->sc_pins) * sc->sc_npins, M_DEVBUF,
+	    M_NOWAIT | M_ZERO);
+	if (sc->sc_pins == NULL)
+		return (ENOMEM);
+
+	/* Initialize the bus lock. */
+	GPIOBUS_LOCK_INIT(sc);
+
+	return (0);
+}
+
+int
+gpiobus_alloc_ivars(struct gpiobus_ivar *devi)
+{
+
+	/* Allocate pins and flags memory. */
+	devi->pins = malloc(sizeof(uint32_t) * devi->npins, M_DEVBUF,
+	    M_NOWAIT | M_ZERO);
+	if (devi->pins == NULL)
+		return (ENOMEM);
+	devi->flags = malloc(sizeof(uint32_t) * devi->npins, M_DEVBUF,
+	    M_NOWAIT | M_ZERO);
+	if (devi->flags == NULL) {
+		free(devi->pins, M_DEVBUF);
+		return (ENOMEM);
+	}
+
+	return (0);
+}
+
+void
+gpiobus_free_ivars(struct gpiobus_ivar *devi)
+{
+
+	if (devi->flags) {
+		free(devi->flags, M_DEVBUF);
+		devi->flags = NULL;
+	}
+	if (devi->pins) {
+		free(devi->pins, M_DEVBUF);
+		devi->pins = NULL;
+	}
+}
+
+int
+gpiobus_acquire_pin(device_t bus, uint32_t pin)
+{
+	struct gpiobus_softc *sc;
+
+	sc = device_get_softc(bus);
+	/* Consistency check. */
+	if (pin >= sc->sc_npins) {
+		device_printf(bus,
+		    "invalid pin %d, max: %d\n", pin, sc->sc_npins - 1);
+		return (-1);
+	}
+	/* Mark pin as mapped and give warning if it's already mapped. */
+	if (sc->sc_pins[pin].mapped) {
+		device_printf(bus, "warning: pin %d is already mapped\n", pin);
+		return (-1);
+	}
+	sc->sc_pins[pin].mapped = 1;
+
+	return (0);
+}
+
+/* Release mapped pin */
+int
+gpiobus_release_pin(device_t bus, uint32_t pin)
+{
+	struct gpiobus_softc *sc;
+
+	sc = device_get_softc(bus);
+	/* Consistency check. */
+	if (pin >= sc->sc_npins) {
+		device_printf(bus,
+		    "gpiobus_acquire_pin: invalid pin %d, max=%d\n",
+		    pin, sc->sc_npins - 1);
+		return (-1);
+	}
+
+	if (!sc->sc_pins[pin].mapped) {
+		device_printf(bus, "gpiobus_acquire_pin: pin %d is not mapped\n", pin);
+		return (-1);
+	}
+	sc->sc_pins[pin].mapped = 0;
+
+	return (0);
+}
+
+static int
+gpiobus_parse_pins(struct gpiobus_softc *sc, device_t child, int mask)
+{
+	struct gpiobus_ivar *devi = GPIOBUS_IVAR(child);
+	int i, npins;
+
+	npins = 0;
+	for (i = 0; i < 32; i++) {
+		if (mask & (1 << i))
+			npins++;
+	}
+	if (npins == 0) {
+		device_printf(child, "empty pin mask\n");
+		return (EINVAL);
+	}
+	devi->npins = npins;
+	if (gpiobus_alloc_ivars(devi) != 0) {
+		device_printf(child, "cannot allocate device ivars\n");
+		return (EINVAL);
+	}
+	npins = 0;
+	for (i = 0; i < 32; i++) {
+		if ((mask & (1 << i)) == 0)
+			continue;
+		/* Reserve the GPIO pin. */
+		if (gpiobus_acquire_pin(sc->sc_busdev, i) != 0) {
+			gpiobus_free_ivars(devi);
+			return (EINVAL);
+		}
+		devi->pins[npins++] = i;
+		/* Use the child name as pin name. */
+		GPIOBUS_PIN_SETNAME(sc->sc_busdev, i,
+		    device_get_nameunit(child));
+	}
+
+	return (0);
+}
+
+static int
+gpiobus_probe(device_t dev)
+{
+	device_set_desc(dev, "GPIO bus");
+
+	return (BUS_PROBE_GENERIC);
+}
+
+static int
+gpiobus_attach(device_t dev)
+{
+	int err;
+
+	err = gpiobus_init_softc(dev);
+	if (err != 0)
+		return (err);
+
+	/*
+	 * Get parent's pins and mark them as unmapped
+	 */
+	bus_generic_probe(dev);
+	bus_enumerate_hinted_children(dev);
+
+	return (bus_generic_attach(dev));
+}
+
+/*
+ * Since this is not a self-enumerating bus, and since we always add
+ * children in attach, we have to always delete children here.
+ */
+static int
+gpiobus_detach(device_t dev)
+{
+	struct gpiobus_softc *sc;
+	struct gpiobus_ivar *devi;
+	device_t *devlist;
+	int i, err, ndevs;
+
+	sc = GPIOBUS_SOFTC(dev);
+	KASSERT(mtx_initialized(&sc->sc_mtx),
+	    ("gpiobus mutex not initialized"));
+	GPIOBUS_LOCK_DESTROY(sc);
+
+	if ((err = bus_generic_detach(dev)) != 0)
+		return (err);
+
+	if ((err = device_get_children(dev, &devlist, &ndevs)) != 0)
+		return (err);
+	for (i = 0; i < ndevs; i++) {
+		devi = GPIOBUS_IVAR(devlist[i]);
+		gpiobus_free_ivars(devi);
+		resource_list_free(&devi->rl);
+		free(devi, M_DEVBUF);
+		device_delete_child(dev, devlist[i]);
+	}
+	free(devlist, M_TEMP);
+	rman_fini(&sc->sc_intr_rman);
+	if (sc->sc_pins) {
+		for (i = 0; i < sc->sc_npins; i++) {
+			if (sc->sc_pins[i].name != NULL)
+				free(sc->sc_pins[i].name, M_DEVBUF);
+			sc->sc_pins[i].name = NULL;
+		}
+		free(sc->sc_pins, M_DEVBUF);
+		sc->sc_pins = NULL;
+	}
+
+	return (0);
+}
+
+static int
+gpiobus_suspend(device_t dev)
+{
+
+	return (bus_generic_suspend(dev));
+}
+
+static int
+gpiobus_resume(device_t dev)
+{
+
+	return (bus_generic_resume(dev));
+}
+
+static void
+gpiobus_probe_nomatch(device_t dev, device_t child)
+{
+	char pins[128];
+	struct gpiobus_ivar *devi;
+
+	devi = GPIOBUS_IVAR(child);
+	memset(pins, 0, sizeof(pins));
+	gpiobus_print_pins(devi, pins, sizeof(pins));
+	if (devi->npins > 1)
+		device_printf(dev, "<unknown device> at pins %s", pins);
+	else
+		device_printf(dev, "<unknown device> at pin %s", pins);
+	resource_list_print_type(&devi->rl, "irq", SYS_RES_IRQ, "%jd");
+	printf("\n");
+}
+
+static int
+gpiobus_print_child(device_t dev, device_t child)
+{
+	char pins[128];
+	int retval = 0;
+	struct gpiobus_ivar *devi;
+
+	devi = GPIOBUS_IVAR(child);
+	memset(pins, 0, sizeof(pins));
+	retval += bus_print_child_header(dev, child);
+	if (devi->npins > 0) {
+		if (devi->npins > 1)
+			retval += printf(" at pins ");
+		else
+			retval += printf(" at pin ");
+		gpiobus_print_pins(devi, pins, sizeof(pins));
+		retval += printf("%s", pins);
+	}
+	resource_list_print_type(&devi->rl, "irq", SYS_RES_IRQ, "%jd");
+	retval += bus_print_child_footer(dev, child);
+
+	return (retval);
+}
+
+static int
+gpiobus_child_location_str(device_t bus, device_t child, char *buf,
+    size_t buflen)
+{
+	struct gpiobus_ivar *devi;
+
+	devi = GPIOBUS_IVAR(child);
+	if (devi->npins > 1)
+		strlcpy(buf, "pins=", buflen);
+	else
+		strlcpy(buf, "pin=", buflen);
+	gpiobus_print_pins(devi, buf, buflen);
+
+	return (0);
+}
+
+static int
+gpiobus_child_pnpinfo_str(device_t bus, device_t child, char *buf,
+    size_t buflen)
+{
+
+	*buf = '\0';
+	return (0);
+}
+
+static device_t
+gpiobus_add_child(device_t dev, u_int order, const char *name, int unit)
+{
+	device_t child;
+	struct gpiobus_ivar *devi;
+
+	child = device_add_child_ordered(dev, order, name, unit);
+	if (child == NULL) 
+		return (child);
+	devi = malloc(sizeof(struct gpiobus_ivar), M_DEVBUF, M_NOWAIT | M_ZERO);
+	if (devi == NULL) {
+		device_delete_child(dev, child);
+		return (NULL);
+	}
+	resource_list_init(&devi->rl);
+	device_set_ivars(child, devi);
+
+	return (child);
+}
+
+static void
+gpiobus_hinted_child(device_t bus, const char *dname, int dunit)
+{
+	struct gpiobus_softc *sc = GPIOBUS_SOFTC(bus);
+	struct gpiobus_ivar *devi;
+	device_t child;
+	int irq, pins;
+
+	child = BUS_ADD_CHILD(bus, 0, dname, dunit);
+	devi = GPIOBUS_IVAR(child);
+	resource_int_value(dname, dunit, "pins", &pins);
+	if (gpiobus_parse_pins(sc, child, pins)) {
+		resource_list_free(&devi->rl);
+		free(devi, M_DEVBUF);
+		device_delete_child(bus, child);
+	}
+	if (resource_int_value(dname, dunit, "irq", &irq) == 0) {
+		if (bus_set_resource(child, SYS_RES_IRQ, 0, irq, 1) != 0)
+			device_printf(bus,
+			    "warning: bus_set_resource() failed\n");
+	}
+}
+
+static int
+gpiobus_set_resource(device_t dev, device_t child, int type, int rid,
+    rman_res_t start, rman_res_t count)
+{
+	struct gpiobus_ivar *devi;
+	struct resource_list_entry *rle;
+
+	dprintf("%s: entry (%p, %p, %d, %d, %p, %ld)\n",
+	    __func__, dev, child, type, rid, (void *)(intptr_t)start, count);
+	devi = GPIOBUS_IVAR(child);
+	rle = resource_list_add(&devi->rl, type, rid, start,
+	    start + count - 1, count);
+	if (rle == NULL)
+		return (ENXIO);
+
+	return (0);
+}
+
+static struct resource *
+gpiobus_alloc_resource(device_t bus, device_t child, int type, int *rid,
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
+{
+	struct gpiobus_softc *sc;
+	struct resource *rv;
+	struct resource_list *rl;
+	struct resource_list_entry *rle;
+	int isdefault;
+
+	if (type != SYS_RES_IRQ)
+		return (NULL);
+	isdefault = (RMAN_IS_DEFAULT_RANGE(start, end) && count == 1);
+	rle = NULL;
+	if (isdefault) {
+		rl = BUS_GET_RESOURCE_LIST(bus, child);
+		if (rl == NULL)
+			return (NULL);
+		rle = resource_list_find(rl, type, *rid);
+		if (rle == NULL)
+			return (NULL);
+		if (rle->res != NULL)
+			panic("%s: resource entry is busy", __func__);
+		start = rle->start;
+		count = rle->count;
+		end = rle->end;
+	}
+	sc = device_get_softc(bus);
+	rv = rman_reserve_resource(&sc->sc_intr_rman, start, end, count, flags,
+	    child);
+	if (rv == NULL)
+		return (NULL);
+	rman_set_rid(rv, *rid);
+	if ((flags & RF_ACTIVE) != 0 &&
+	    bus_activate_resource(child, type, *rid, rv) != 0) {
+		rman_release_resource(rv);
+		return (NULL);
+	}
+
+	return (rv);
+}
+
+static int
+gpiobus_release_resource(device_t bus __unused, device_t child, int type,
+    int rid, struct resource *r)
+{
+	int error;
+
+	if (rman_get_flags(r) & RF_ACTIVE) {
+		error = bus_deactivate_resource(child, type, rid, r);
+		if (error)
+			return (error);
+	}
+
+	return (rman_release_resource(r));
+}
+
+static struct resource_list *
+gpiobus_get_resource_list(device_t bus __unused, device_t child)
+{
+	struct gpiobus_ivar *ivar;
+
+	ivar = GPIOBUS_IVAR(child);
+
+	return (&ivar->rl);
+}
+
+static int
+gpiobus_acquire_bus(device_t busdev, device_t child, int how)
+{
+	struct gpiobus_softc *sc;
+
+	sc = device_get_softc(busdev);
+	GPIOBUS_ASSERT_UNLOCKED(sc);
+	GPIOBUS_LOCK(sc);
+	if (sc->sc_owner != NULL) {
+		if (sc->sc_owner == child)
+			panic("%s: %s still owns the bus.",
+			    device_get_nameunit(busdev),
+			    device_get_nameunit(child));
+		if (how == GPIOBUS_DONTWAIT) {
+			GPIOBUS_UNLOCK(sc);
+			return (EWOULDBLOCK);
+		}
+		while (sc->sc_owner != NULL)
+			mtx_sleep(sc, &sc->sc_mtx, 0, "gpiobuswait", 0);
+	}
+	sc->sc_owner = child;
+	GPIOBUS_UNLOCK(sc);
+
+	return (0);
+}
+
+static void
+gpiobus_release_bus(device_t busdev, device_t child)
+{
+	struct gpiobus_softc *sc;
+
+	sc = device_get_softc(busdev);
+	GPIOBUS_ASSERT_UNLOCKED(sc);
+	GPIOBUS_LOCK(sc);
+	if (sc->sc_owner == NULL)
+		panic("%s: %s releasing unowned bus.",
+		    device_get_nameunit(busdev),
+		    device_get_nameunit(child));
+	if (sc->sc_owner != child)
+		panic("%s: %s trying to release bus owned by %s",
+		    device_get_nameunit(busdev),
+		    device_get_nameunit(child),
+		    device_get_nameunit(sc->sc_owner));
+	sc->sc_owner = NULL;
+	wakeup(sc);
+	GPIOBUS_UNLOCK(sc);
+}
+
+static int
+gpiobus_pin_setflags(device_t dev, device_t child, uint32_t pin, 
+    uint32_t flags)
+{
+	struct gpiobus_softc *sc = GPIOBUS_SOFTC(dev);
+	struct gpiobus_ivar *devi = GPIOBUS_IVAR(child);
+	uint32_t caps;
+
+	if (pin >= devi->npins)
+		return (EINVAL);
+	if (GPIO_PIN_GETCAPS(sc->sc_dev, devi->pins[pin], &caps) != 0)
+		return (EINVAL);
+	if (gpio_check_flags(caps, flags) != 0)
+		return (EINVAL);
+
+	return (GPIO_PIN_SETFLAGS(sc->sc_dev, devi->pins[pin], flags));
+}
+
+static int
+gpiobus_pin_getflags(device_t dev, device_t child, uint32_t pin, 
+    uint32_t *flags)
+{
+	struct gpiobus_softc *sc = GPIOBUS_SOFTC(dev);
+	struct gpiobus_ivar *devi = GPIOBUS_IVAR(child);
+
+	if (pin >= devi->npins)
+		return (EINVAL);
+
+	return GPIO_PIN_GETFLAGS(sc->sc_dev, devi->pins[pin], flags);
+}
+
+static int
+gpiobus_pin_getcaps(device_t dev, device_t child, uint32_t pin, 
+    uint32_t *caps)
+{
+	struct gpiobus_softc *sc = GPIOBUS_SOFTC(dev);
+	struct gpiobus_ivar *devi = GPIOBUS_IVAR(child);
+
+	if (pin >= devi->npins)
+		return (EINVAL);
+
+	return GPIO_PIN_GETCAPS(sc->sc_dev, devi->pins[pin], caps);
+}
+
+static int
+gpiobus_pin_set(device_t dev, device_t child, uint32_t pin, 
+    unsigned int value)
+{
+	struct gpiobus_softc *sc = GPIOBUS_SOFTC(dev);
+	struct gpiobus_ivar *devi = GPIOBUS_IVAR(child);
+
+	if (pin >= devi->npins)
+		return (EINVAL);
+
+	return GPIO_PIN_SET(sc->sc_dev, devi->pins[pin], value);
+}
+
+static int
+gpiobus_pin_get(device_t dev, device_t child, uint32_t pin, 
+    unsigned int *value)
+{
+	struct gpiobus_softc *sc = GPIOBUS_SOFTC(dev);
+	struct gpiobus_ivar *devi = GPIOBUS_IVAR(child);
+
+	if (pin >= devi->npins)
+		return (EINVAL);
+
+	return GPIO_PIN_GET(sc->sc_dev, devi->pins[pin], value);
+}
+
+static int
+gpiobus_pin_toggle(device_t dev, device_t child, uint32_t pin)
+{
+	struct gpiobus_softc *sc = GPIOBUS_SOFTC(dev);
+	struct gpiobus_ivar *devi = GPIOBUS_IVAR(child);
+
+	if (pin >= devi->npins)
+		return (EINVAL);
+
+	return GPIO_PIN_TOGGLE(sc->sc_dev, devi->pins[pin]);
+}
+
+static int
+gpiobus_pin_getname(device_t dev, uint32_t pin, char *name)
+{
+	struct gpiobus_softc *sc;
+
+	sc = GPIOBUS_SOFTC(dev);
+	if (pin > sc->sc_npins)
+		return (EINVAL);
+	/* Did we have a name for this pin ? */
+	if (sc->sc_pins[pin].name != NULL) {
+		memcpy(name, sc->sc_pins[pin].name, GPIOMAXNAME);
+		return (0);
+	}
+
+	/* Return the default pin name. */
+	return (GPIO_PIN_GETNAME(device_get_parent(dev), pin, name));
+}
+
+static int
+gpiobus_pin_setname(device_t dev, uint32_t pin, const char *name)
+{
+	struct gpiobus_softc *sc;
+
+	sc = GPIOBUS_SOFTC(dev);
+	if (pin > sc->sc_npins)
+		return (EINVAL);
+	if (name == NULL)
+		return (EINVAL);
+	/* Save the pin name. */
+	if (sc->sc_pins[pin].name == NULL)
+		sc->sc_pins[pin].name = malloc(GPIOMAXNAME, M_DEVBUF,
+		    M_WAITOK | M_ZERO);
+	strlcpy(sc->sc_pins[pin].name, name, GPIOMAXNAME);
+
+	return (0);
+}
+
+static device_method_t gpiobus_methods[] = {
+	/* Device interface */
+	DEVMETHOD(device_probe,		gpiobus_probe),
+	DEVMETHOD(device_attach,	gpiobus_attach),
+	DEVMETHOD(device_detach,	gpiobus_detach),
+	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
+	DEVMETHOD(device_suspend,	gpiobus_suspend),
+	DEVMETHOD(device_resume,	gpiobus_resume),
+
+	/* Bus interface */
+	DEVMETHOD(bus_setup_intr,	bus_generic_setup_intr),
+	DEVMETHOD(bus_config_intr,	bus_generic_config_intr),
+	DEVMETHOD(bus_teardown_intr,	bus_generic_teardown_intr),
+	DEVMETHOD(bus_set_resource,	gpiobus_set_resource),
+	DEVMETHOD(bus_alloc_resource,	gpiobus_alloc_resource),
+	DEVMETHOD(bus_release_resource,	gpiobus_release_resource),
+	DEVMETHOD(bus_activate_resource,	bus_generic_activate_resource),
+	DEVMETHOD(bus_deactivate_resource,	bus_generic_deactivate_resource),
+	DEVMETHOD(bus_get_resource_list,	gpiobus_get_resource_list),
+	DEVMETHOD(bus_add_child,	gpiobus_add_child),
+	DEVMETHOD(bus_probe_nomatch,	gpiobus_probe_nomatch),
+	DEVMETHOD(bus_print_child,	gpiobus_print_child),
+	DEVMETHOD(bus_child_pnpinfo_str, gpiobus_child_pnpinfo_str),
+	DEVMETHOD(bus_child_location_str, gpiobus_child_location_str),
+	DEVMETHOD(bus_hinted_child,	gpiobus_hinted_child),
+
+	/* GPIO protocol */
+	DEVMETHOD(gpiobus_acquire_bus,	gpiobus_acquire_bus),
+	DEVMETHOD(gpiobus_release_bus,	gpiobus_release_bus),
+	DEVMETHOD(gpiobus_pin_getflags,	gpiobus_pin_getflags),
+	DEVMETHOD(gpiobus_pin_getcaps,	gpiobus_pin_getcaps),
+	DEVMETHOD(gpiobus_pin_setflags,	gpiobus_pin_setflags),
+	DEVMETHOD(gpiobus_pin_get,	gpiobus_pin_get),
+	DEVMETHOD(gpiobus_pin_set,	gpiobus_pin_set),
+	DEVMETHOD(gpiobus_pin_toggle,	gpiobus_pin_toggle),
+	DEVMETHOD(gpiobus_pin_getname,	gpiobus_pin_getname),
+	DEVMETHOD(gpiobus_pin_setname,	gpiobus_pin_setname),
+
+	DEVMETHOD_END
+};
+
+driver_t gpiobus_driver = {
+	"gpiobus",
+	gpiobus_methods,
+	sizeof(struct gpiobus_softc)
+};
+
+devclass_t	gpiobus_devclass;
+
+EARLY_DRIVER_MODULE(gpiobus, gpio, gpiobus_driver, gpiobus_devclass, 0, 0,
+    BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);
+MODULE_VERSION(gpiobus, 1);
diff --git a/freebsd/sys/dev/gpio/gpiobusvar.h b/freebsd/sys/dev/gpio/gpiobusvar.h
new file mode 100644
index 00000000..9eee5a03
--- /dev/null
+++ b/freebsd/sys/dev/gpio/gpiobusvar.h
@@ -0,0 +1,156 @@
+/*-
+ * Copyright (c) 2009 Oleksandr Tymoshenko <gonzo@freebsd.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ *
+ */
+
+#ifndef	__GPIOBUS_H__
+#define	__GPIOBUS_H__
+
+#include <rtems/bsd/local/opt_platform.h>
+
+#include <sys/lock.h>
+#include <sys/mutex.h>
+#include <sys/rman.h>
+
+#ifdef FDT
+#include <dev/ofw/ofw_bus_subr.h>
+#endif
+
+#ifdef	INTRNG
+#include <sys/intr.h>
+#endif
+
+#include <rtems/bsd/local/gpio_if.h>
+
+#ifdef FDT
+#define	GPIOBUS_IVAR(d) (struct gpiobus_ivar *)				\
+	&((struct ofw_gpiobus_devinfo *)device_get_ivars(d))->opd_dinfo
+#else
+#define	GPIOBUS_IVAR(d) (struct gpiobus_ivar *) device_get_ivars(d)
+#endif
+#define	GPIOBUS_SOFTC(d) (struct gpiobus_softc *) device_get_softc(d)
+#define	GPIOBUS_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
+#define	GPIOBUS_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
+#define	GPIOBUS_LOCK_INIT(_sc) mtx_init(&_sc->sc_mtx,			\
+	    device_get_nameunit(_sc->sc_dev), "gpiobus", MTX_DEF)
+#define	GPIOBUS_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx)
+#define	GPIOBUS_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED)
+#define	GPIOBUS_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED)
+
+#define	GPIOBUS_WAIT		1
+#define	GPIOBUS_DONTWAIT	2
+
+/* Use default interrupt mode -  for gpio_alloc_intr_resource */
+#define GPIO_INTR_CONFORM	GPIO_INTR_NONE
+
+struct gpiobus_pin_data
+{
+	int		mapped;		/* pin is mapped/reserved. */
+	char		*name;		/* pin name. */
+};
+
+#ifdef INTRNG
+struct intr_map_data_gpio {
+	struct intr_map_data	hdr;
+	u_int			gpio_pin_num;
+	u_int			gpio_pin_flags;
+	u_int		 	gpio_intr_mode;
+};
+#endif
+
+struct gpiobus_softc
+{
+	struct mtx	sc_mtx;		/* bus mutex */
+	struct rman	sc_intr_rman;	/* isr resources */
+	device_t	sc_busdev;	/* bus device */
+	device_t	sc_owner;	/* bus owner */
+	device_t	sc_dev;		/* driver device */
+	int		sc_npins;	/* total pins on bus */
+	struct gpiobus_pin_data	*sc_pins; /* pin data */
+};
+
+struct gpiobus_pin
+{
+	device_t	dev;	/* gpio device */
+	uint32_t	flags;	/* pin flags */
+	uint32_t	pin;	/* pin number */
+};
+typedef struct gpiobus_pin *gpio_pin_t;
+
+struct gpiobus_ivar
+{
+	struct resource_list	rl;	/* isr resource list */
+	uint32_t	npins;	/* pins total */
+	uint32_t	*flags;	/* pins flags */
+	uint32_t	*pins;	/* pins map */
+};
+
+#ifdef FDT
+struct ofw_gpiobus_devinfo {
+	struct gpiobus_ivar	opd_dinfo;
+	struct ofw_bus_devinfo	opd_obdinfo;
+};
+
+static __inline int
+gpio_map_gpios(device_t bus, phandle_t dev, phandle_t gparent, int gcells,
+    pcell_t *gpios, uint32_t *pin, uint32_t *flags)
+{
+	return (GPIO_MAP_GPIOS(bus, dev, gparent, gcells, gpios, pin, flags));
+}
+
+device_t ofw_gpiobus_add_fdt_child(device_t, const char *, phandle_t);
+int ofw_gpiobus_parse_gpios(device_t, char *, struct gpiobus_pin **);
+void ofw_gpiobus_register_provider(device_t);
+void ofw_gpiobus_unregister_provider(device_t);
+
+/* Consumers interface. */
+int gpio_pin_get_by_ofw_name(device_t consumer, phandle_t node,
+    char *name, gpio_pin_t *gpio);
+int gpio_pin_get_by_ofw_idx(device_t consumer, phandle_t node,
+    int idx, gpio_pin_t *gpio);
+int gpio_pin_get_by_ofw_property(device_t consumer, phandle_t node,
+    char *name, gpio_pin_t *gpio);
+void gpio_pin_release(gpio_pin_t gpio);
+int gpio_pin_getcaps(gpio_pin_t pin, uint32_t *caps);
+int gpio_pin_is_active(gpio_pin_t pin, bool *active);
+int gpio_pin_set_active(gpio_pin_t pin, bool active);
+int gpio_pin_setflags(gpio_pin_t pin, uint32_t flags);
+#endif
+struct resource *gpio_alloc_intr_resource(device_t consumer_dev, int *rid,
+    u_int alloc_flags, gpio_pin_t pin, uint32_t intr_mode);
+int gpio_check_flags(uint32_t, uint32_t);
+device_t gpiobus_attach_bus(device_t);
+int gpiobus_detach_bus(device_t);
+int gpiobus_init_softc(device_t);
+int gpiobus_alloc_ivars(struct gpiobus_ivar *);
+void gpiobus_free_ivars(struct gpiobus_ivar *);
+int gpiobus_acquire_pin(device_t, uint32_t);
+int gpiobus_release_pin(device_t, uint32_t);
+
+extern driver_t gpiobus_driver;
+
+#endif	/* __GPIOBUS_H__ */
diff --git a/freebsd/sys/dev/gpio/ofw_gpiobus.c b/freebsd/sys/dev/gpio/ofw_gpiobus.c
new file mode 100644
index 00000000..24e9477c
--- /dev/null
+++ b/freebsd/sys/dev/gpio/ofw_gpiobus.c
@@ -0,0 +1,593 @@
+#include <machine/rtems-bsd-kernel-space.h>
+
+/*-
+ * Copyright (c) 2009, Nathan Whitehorn <nwhitehorn@FreeBSD.org>
+ * Copyright (c) 2013, Luiz Otavio O Souza <loos@FreeBSD.org>
+ * Copyright (c) 2013 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice unmodified, this list of conditions, and the following
+ *    disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/malloc.h>
+#include <sys/module.h>
+
+#include <dev/gpio/gpiobusvar.h>
+#include <dev/ofw/ofw_bus.h>
+
+#include <rtems/bsd/local/gpiobus_if.h>
+
+#define	GPIO_ACTIVE_LOW		1
+
+static struct ofw_gpiobus_devinfo *ofw_gpiobus_setup_devinfo(device_t,
+	device_t, phandle_t);
+static void ofw_gpiobus_destroy_devinfo(device_t, struct ofw_gpiobus_devinfo *);
+static int ofw_gpiobus_parse_gpios_impl(device_t, phandle_t, char *,
+	struct gpiobus_softc *, struct gpiobus_pin **);
+
+/*
+ * Utility functions for easier handling of OFW GPIO pins.
+ *
+ * !!! BEWARE !!!
+ * GPIOBUS uses children's IVARs, so we cannot use this interface for cross
+ * tree consumers.
+ *
+ */
+static int
+gpio_pin_get_by_ofw_impl(device_t consumer, phandle_t cnode,
+    char *prop_name, int idx, gpio_pin_t *out_pin)
+{
+	phandle_t xref;
+	pcell_t *cells;
+	device_t busdev;
+	struct gpiobus_pin pin;
+	int ncells, rv;
+
+	KASSERT(consumer != NULL && cnode > 0,
+	    ("both consumer and cnode required"));
+
+	rv = ofw_bus_parse_xref_list_alloc(cnode, prop_name, "#gpio-cells",
+	    idx, &xref, &ncells, &cells);
+	if (rv != 0)
+		return (rv);
+
+	/* Translate provider to device. */
+	pin.dev = OF_device_from_xref(xref);
+	if (pin.dev == NULL) {
+		OF_prop_free(cells);
+		return (ENODEV);
+	}
+
+	/* Test if GPIO bus already exist. */
+	busdev = GPIO_GET_BUS(pin.dev);
+	if (busdev == NULL) {
+		OF_prop_free(cells);
+		return (ENODEV);
+	}
+
+	/* Map GPIO pin. */
+	rv = gpio_map_gpios(pin.dev, cnode, OF_node_from_xref(xref), ncells,
+	    cells, &pin.pin, &pin.flags);
+	OF_prop_free(cells);
+	if (rv != 0)
+		return (ENXIO);
+
+	/* Reserve GPIO pin. */
+	rv = gpiobus_acquire_pin(busdev, pin.pin);
+	if (rv != 0)
+		return (EBUSY);
+
+	*out_pin = malloc(sizeof(struct gpiobus_pin), M_DEVBUF,
+	    M_WAITOK | M_ZERO);
+	**out_pin = pin;
+	return (0);
+}
+
+int
+gpio_pin_get_by_ofw_idx(device_t consumer, phandle_t node,
+    int idx, gpio_pin_t *pin)
+{
+
+	return (gpio_pin_get_by_ofw_impl(consumer, node, "gpios", idx, pin));
+}
+
+int
+gpio_pin_get_by_ofw_property(device_t consumer, phandle_t node,
+    char *name, gpio_pin_t *pin)
+{
+
+	return (gpio_pin_get_by_ofw_impl(consumer, node, name, 0, pin));
+}
+
+int
+gpio_pin_get_by_ofw_name(device_t consumer, phandle_t node,
+    char *name, gpio_pin_t *pin)
+{
+	int rv, idx;
+
+	KASSERT(consumer != NULL && node > 0,
+	    ("both consumer and node required"));
+
+	rv = ofw_bus_find_string_index(node, "gpio-names", name, &idx);
+	if (rv != 0)
+		return (rv);
+	return (gpio_pin_get_by_ofw_idx(consumer, node, idx, pin));
+}
+
+void
+gpio_pin_release(gpio_pin_t gpio)
+{
+	device_t busdev;
+
+	if (gpio == NULL)
+		return;
+
+	KASSERT(gpio->dev != NULL, ("invalid pin state"));
+
+	busdev = GPIO_GET_BUS(gpio->dev);
+	if (busdev != NULL)
+		gpiobus_release_pin(busdev, gpio->pin);
+
+	/* XXXX Unreserve pin. */
+	free(gpio, M_DEVBUF);
+}
+
+int
+gpio_pin_getcaps(gpio_pin_t pin, uint32_t *caps)
+{
+
+	KASSERT(pin != NULL, ("GPIO pin is NULL."));
+	KASSERT(pin->dev != NULL, ("GPIO pin device is NULL."));
+	return (GPIO_PIN_GETCAPS(pin->dev, pin->pin, caps));
+}
+
+int
+gpio_pin_is_active(gpio_pin_t pin, bool *active)
+{
+	int rv;
+	uint32_t tmp;
+
+	KASSERT(pin != NULL, ("GPIO pin is NULL."));
+	KASSERT(pin->dev != NULL, ("GPIO pin device is NULL."));
+	rv = GPIO_PIN_GET(pin->dev, pin->pin, &tmp);
+	if (rv  != 0) {
+		return (rv);
+	}
+
+	if (pin->flags & GPIO_ACTIVE_LOW)
+		*active = tmp == 0;
+	else
+		*active = tmp != 0;
+	return (0);
+}
+
+int
+gpio_pin_set_active(gpio_pin_t pin, bool active)
+{
+	int rv;
+	uint32_t tmp;
+
+	if (pin->flags & GPIO_ACTIVE_LOW)
+		tmp = active ? 0 : 1;
+	else
+		tmp = active ? 1 : 0;
+
+	KASSERT(pin != NULL, ("GPIO pin is NULL."));
+	KASSERT(pin->dev != NULL, ("GPIO pin device is NULL."));
+	rv = GPIO_PIN_SET(pin->dev, pin->pin, tmp);
+	return (rv);
+}
+
+int
+gpio_pin_setflags(gpio_pin_t pin, uint32_t flags)
+{
+	int rv;
+
+	KASSERT(pin != NULL, ("GPIO pin is NULL."));
+	KASSERT(pin->dev != NULL, ("GPIO pin device is NULL."));
+
+	rv = GPIO_PIN_SETFLAGS(pin->dev, pin->pin, flags);
+	return (rv);
+}
+
+/*
+ * OFW_GPIOBUS driver.
+ */
+device_t
+ofw_gpiobus_add_fdt_child(device_t bus, const char *drvname, phandle_t child)
+{
+	device_t childdev;
+	int i;
+	struct gpiobus_ivar *devi;
+	struct ofw_gpiobus_devinfo *dinfo;
+
+	/*
+	 * Check to see if we already have a child for @p child, and if so
+	 * return it.
+	 */
+	childdev = ofw_bus_find_child_device_by_phandle(bus, child);
+	if (childdev != NULL)
+		return (childdev);
+
+	/*
+	 * Set up the GPIO child and OFW bus layer devinfo and add it to bus.
+	 */
+	childdev = device_add_child(bus, drvname, -1);
+	if (childdev == NULL)
+		return (NULL);
+	dinfo = ofw_gpiobus_setup_devinfo(bus, childdev, child);
+	if (dinfo == NULL) {
+		device_delete_child(bus, childdev);
+		return (NULL);
+	}
+	if (device_probe_and_attach(childdev) != 0) {
+		ofw_gpiobus_destroy_devinfo(bus, dinfo);
+		device_delete_child(bus, childdev);
+		return (NULL);
+	}
+	/* Use the child name as pin name. */
+	devi = &dinfo->opd_dinfo;
+	for (i = 0; i < devi->npins; i++)
+		GPIOBUS_PIN_SETNAME(bus, devi->pins[i],
+		    device_get_nameunit(childdev));
+
+	return (childdev);
+}
+
+int
+ofw_gpiobus_parse_gpios(device_t consumer, char *pname,
+	struct gpiobus_pin **pins)
+{
+
+	return (ofw_gpiobus_parse_gpios_impl(consumer,
+	    ofw_bus_get_node(consumer), pname, NULL, pins));
+}
+
+void
+ofw_gpiobus_register_provider(device_t provider)
+{
+	phandle_t node;
+
+	node = ofw_bus_get_node(provider);
+	OF_device_register_xref(OF_xref_from_node(node), provider);
+}
+
+void
+ofw_gpiobus_unregister_provider(device_t provider)
+{
+	phandle_t node;
+
+	node = ofw_bus_get_node(provider);
+	OF_device_register_xref(OF_xref_from_node(node), NULL);
+}
+
+static struct ofw_gpiobus_devinfo *
+ofw_gpiobus_setup_devinfo(device_t bus, device_t child, phandle_t node)
+{
+	int i, npins;
+	struct gpiobus_ivar *devi;
+	struct gpiobus_pin *pins;
+	struct gpiobus_softc *sc;
+	struct ofw_gpiobus_devinfo *dinfo;
+
+	sc = device_get_softc(bus);
+	dinfo = malloc(sizeof(*dinfo), M_DEVBUF, M_NOWAIT | M_ZERO);
+	if (dinfo == NULL)
+		return (NULL);
+	if (ofw_bus_gen_setup_devinfo(&dinfo->opd_obdinfo, node) != 0) {
+		free(dinfo, M_DEVBUF);
+		return (NULL);
+	}
+	/* Parse the gpios property for the child. */
+	npins = ofw_gpiobus_parse_gpios_impl(child, node, "gpios", sc, &pins);
+	if (npins <= 0) {
+		ofw_bus_gen_destroy_devinfo(&dinfo->opd_obdinfo);
+		free(dinfo, M_DEVBUF);
+		return (NULL);
+	}
+	/* Initialize the irq resource list. */
+	resource_list_init(&dinfo->opd_dinfo.rl);
+	/* Allocate the child ivars and copy the parsed pin data. */
+	devi = &dinfo->opd_dinfo;
+	devi->npins = (uint32_t)npins;
+	if (gpiobus_alloc_ivars(devi) != 0) {
+		free(pins, M_DEVBUF);
+		ofw_gpiobus_destroy_devinfo(bus, dinfo);
+		return (NULL);
+	}
+	for (i = 0; i < devi->npins; i++) {
+		devi->flags[i] = pins[i].flags;
+		devi->pins[i] = pins[i].pin;
+	}
+	free(pins, M_DEVBUF);
+	/* Parse the interrupt resources. */
+	if (ofw_bus_intr_to_rl(bus, node, &dinfo->opd_dinfo.rl, NULL) != 0) {
+		ofw_gpiobus_destroy_devinfo(bus, dinfo);
+		return (NULL);
+	}
+	device_set_ivars(child, dinfo);
+
+	return (dinfo);
+}
+
+static void
+ofw_gpiobus_destroy_devinfo(device_t bus, struct ofw_gpiobus_devinfo *dinfo)
+{
+	int i;
+	struct gpiobus_ivar *devi;
+	struct gpiobus_softc *sc;
+
+	sc = device_get_softc(bus);
+	devi = &dinfo->opd_dinfo;
+	for (i = 0; i < devi->npins; i++) {
+		if (devi->pins[i] > sc->sc_npins)
+			continue;
+		sc->sc_pins[devi->pins[i]].mapped = 0;
+	}
+	gpiobus_free_ivars(devi);
+	resource_list_free(&dinfo->opd_dinfo.rl);
+	ofw_bus_gen_destroy_devinfo(&dinfo->opd_obdinfo);
+	free(dinfo, M_DEVBUF);
+}
+
+static int
+ofw_gpiobus_parse_gpios_impl(device_t consumer, phandle_t cnode, char *pname,
+	struct gpiobus_softc *bussc, struct gpiobus_pin **pins)
+{
+	int gpiocells, i, j, ncells, npins;
+	pcell_t *gpios;
+	phandle_t gpio;
+
+	ncells = OF_getencprop_alloc(cnode, pname, sizeof(*gpios),
+            (void **)&gpios);
+	if (ncells == -1) {
+		device_printf(consumer,
+		    "Warning: No %s specified in fdt data; "
+		    "device may not function.\n", pname);
+		return (-1);
+	}
+	/*
+	 * The gpio-specifier is controller independent, the first pcell has
+	 * the reference to the GPIO controller phandler.
+	 * Count the number of encoded gpio-specifiers on the first pass.
+	 */
+	i = 0;
+	npins = 0;
+	while (i < ncells) {
+		/* Allow NULL specifiers. */
+		if (gpios[i] == 0) {
+			npins++;
+			i++;
+			continue;
+		}
+		gpio = OF_node_from_xref(gpios[i]);
+		/* If we have bussc, ignore devices from other gpios. */
+		if (bussc != NULL)
+			if (ofw_bus_get_node(bussc->sc_dev) != gpio)
+				return (0);
+		/*
+		 * Check for gpio-controller property and read the #gpio-cells
+		 * for this GPIO controller.
+		 */
+		if (!OF_hasprop(gpio, "gpio-controller") ||
+		    OF_getencprop(gpio, "#gpio-cells", &gpiocells,
+		    sizeof(gpiocells)) < 0) {
+			device_printf(consumer,
+			    "gpio reference is not a gpio-controller.\n");
+			OF_prop_free(gpios);
+			return (-1);
+		}
+		if (ncells - i < gpiocells + 1) {
+			device_printf(consumer,
+			    "%s cells doesn't match #gpio-cells.\n", pname);
+			return (-1);
+		}
+		npins++;
+		i += gpiocells + 1;
+	}
+	if (npins == 0 || pins == NULL) {
+		if (npins == 0)
+			device_printf(consumer, "no pin specified in %s.\n",
+			    pname);
+		OF_prop_free(gpios);
+		return (npins);
+	}
+	*pins = malloc(sizeof(struct gpiobus_pin) * npins, M_DEVBUF,
+	    M_NOWAIT | M_ZERO);
+	if (*pins == NULL) {
+		OF_prop_free(gpios);
+		return (-1);
+	}
+	/* Decode the gpio specifier on the second pass. */
+	i = 0;
+	j = 0;
+	while (i < ncells) {
+		/* Allow NULL specifiers. */
+		if (gpios[i] == 0) {
+			j++;
+			i++;
+			continue;
+		}
+		gpio = OF_node_from_xref(gpios[i]);
+		/* Read gpio-cells property for this GPIO controller. */
+		if (OF_getencprop(gpio, "#gpio-cells", &gpiocells,
+		    sizeof(gpiocells)) < 0) {
+			device_printf(consumer,
+			    "gpio does not have the #gpio-cells property.\n");
+			goto fail;
+		}
+		/* Return the device reference for the GPIO controller. */
+		(*pins)[j].dev = OF_device_from_xref(gpios[i]);
+		if ((*pins)[j].dev == NULL) {
+			device_printf(consumer,
+			    "no device registered for the gpio controller.\n");
+			goto fail;
+		}
+		/*
+		 * If the gpiobus softc is NULL we use the GPIO_GET_BUS() to
+		 * retrieve it.  The GPIO_GET_BUS() method is only valid after
+		 * the child is probed and attached.
+		 */
+		if (bussc == NULL) {
+			if (GPIO_GET_BUS((*pins)[j].dev) == NULL) {
+				device_printf(consumer,
+				    "no gpiobus reference for %s.\n",
+				    device_get_nameunit((*pins)[j].dev));
+				goto fail;
+			}
+			bussc = device_get_softc(GPIO_GET_BUS((*pins)[j].dev));
+		}
+		/* Get the GPIO pin number and flags. */
+		if (gpio_map_gpios((*pins)[j].dev, cnode, gpio, gpiocells,
+		    &gpios[i + 1], &(*pins)[j].pin, &(*pins)[j].flags) != 0) {
+			device_printf(consumer,
+			    "cannot map the gpios specifier.\n");
+			goto fail;
+		}
+		/* Reserve the GPIO pin. */
+		if (gpiobus_acquire_pin(bussc->sc_busdev, (*pins)[j].pin) != 0)
+			goto fail;
+		j++;
+		i += gpiocells + 1;
+	}
+	OF_prop_free(gpios);
+
+	return (npins);
+
+fail:
+	OF_prop_free(gpios);
+	free(*pins, M_DEVBUF);
+	return (-1);
+}
+
+static int
+ofw_gpiobus_probe(device_t dev)
+{
+
+	if (ofw_bus_get_node(dev) == -1)
+		return (ENXIO);
+	device_set_desc(dev, "OFW GPIO bus");
+
+	return (0);
+}
+
+static int
+ofw_gpiobus_attach(device_t dev)
+{
+	int err;
+	phandle_t child;
+
+	err = gpiobus_init_softc(dev);
+	if (err != 0)
+		return (err);
+	bus_generic_probe(dev);
+	bus_enumerate_hinted_children(dev);
+	/*
+	 * Attach the children represented in the device tree.
+	 */
+	for (child = OF_child(ofw_bus_get_node(dev)); child != 0;
+	    child = OF_peer(child)) {
+		if (!OF_hasprop(child, "gpios"))
+			continue;
+		if (ofw_gpiobus_add_fdt_child(dev, NULL, child) == NULL)
+			continue;
+	}
+
+	return (bus_generic_attach(dev));
+}
+
+static device_t
+ofw_gpiobus_add_child(device_t dev, u_int order, const char *name, int unit)
+{
+	device_t child;
+	struct ofw_gpiobus_devinfo *devi;
+
+	child = device_add_child_ordered(dev, order, name, unit);
+	if (child == NULL)
+		return (child);
+	devi = malloc(sizeof(struct ofw_gpiobus_devinfo), M_DEVBUF,
+	    M_NOWAIT | M_ZERO);
+	if (devi == NULL) {
+		device_delete_child(dev, child);
+		return (0);
+	}
+
+	/*
+	 * NULL all the OFW-related parts of the ivars for non-OFW
+	 * children.
+	 */
+	devi->opd_obdinfo.obd_node = -1;
+	devi->opd_obdinfo.obd_name = NULL;
+	devi->opd_obdinfo.obd_compat = NULL;
+	devi->opd_obdinfo.obd_type = NULL;
+	devi->opd_obdinfo.obd_model = NULL;
+
+	device_set_ivars(child, devi);
+
+	return (child);
+}
+
+static const struct ofw_bus_devinfo *
+ofw_gpiobus_get_devinfo(device_t bus, device_t dev)
+{
+	struct ofw_gpiobus_devinfo *dinfo;
+
+	dinfo = device_get_ivars(dev);
+
+	return (&dinfo->opd_obdinfo);
+}
+
+static device_method_t ofw_gpiobus_methods[] = {
+	/* Device interface */
+	DEVMETHOD(device_probe,		ofw_gpiobus_probe),
+	DEVMETHOD(device_attach,	ofw_gpiobus_attach),
+
+	/* Bus interface */
+	DEVMETHOD(bus_child_pnpinfo_str,	ofw_bus_gen_child_pnpinfo_str),
+	DEVMETHOD(bus_add_child,	ofw_gpiobus_add_child),
+
+	/* ofw_bus interface */
+	DEVMETHOD(ofw_bus_get_devinfo,	ofw_gpiobus_get_devinfo),
+	DEVMETHOD(ofw_bus_get_compat,	ofw_bus_gen_get_compat),
+	DEVMETHOD(ofw_bus_get_model,	ofw_bus_gen_get_model),
+	DEVMETHOD(ofw_bus_get_name,	ofw_bus_gen_get_name),
+	DEVMETHOD(ofw_bus_get_node,	ofw_bus_gen_get_node),
+	DEVMETHOD(ofw_bus_get_type,	ofw_bus_gen_get_type),
+
+	DEVMETHOD_END
+};
+
+devclass_t ofwgpiobus_devclass;
+
+DEFINE_CLASS_1(gpiobus, ofw_gpiobus_driver, ofw_gpiobus_methods,
+    sizeof(struct gpiobus_softc), gpiobus_driver);
+EARLY_DRIVER_MODULE(ofw_gpiobus, gpio, ofw_gpiobus_driver, ofwgpiobus_devclass,
+    0, 0, BUS_PASS_BUS);
+MODULE_VERSION(ofw_gpiobus, 1);
+MODULE_DEPEND(ofw_gpiobus, gpiobus, 1, 1, 1);
diff --git a/freebsd/sys/dev/sdhci/sdhci.c b/freebsd/sys/dev/sdhci/sdhci.c
new file mode 100644
index 00000000..8c1be21e
--- /dev/null
+++ b/freebsd/sys/dev/sdhci/sdhci.c
@@ -0,0 +1,1780 @@
+#include <machine/rtems-bsd-kernel-space.h>
+
+/*-
+ * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/callout.h>
+#include <sys/conf.h>
+#include <sys/kernel.h>
+#include <sys/lock.h>
+#include <sys/module.h>
+#include <sys/mutex.h>
+#include <rtems/bsd/sys/resource.h>
+#include <sys/rman.h>
+#include <sys/sysctl.h>
+#include <sys/taskqueue.h>
+
+#include <machine/bus.h>
+#include <machine/resource.h>
+#include <machine/stdarg.h>
+
+#include <dev/mmc/bridge.h>
+#include <dev/mmc/mmcreg.h>
+#include <dev/mmc/mmcbrvar.h>
+
+#include <rtems/bsd/local/mmcbr_if.h>
+#include "sdhci.h"
+#include <rtems/bsd/local/sdhci_if.h>
+
+SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD, 0, "sdhci driver");
+
+static int sdhci_debug;
+SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RWTUN, &sdhci_debug, 0,
+    "Debug level");
+u_int sdhci_quirk_clear = 0;
+SYSCTL_INT(_hw_sdhci, OID_AUTO, quirk_clear, CTLFLAG_RWTUN, &sdhci_quirk_clear,
+    0, "Mask of quirks to clear");
+u_int sdhci_quirk_set = 0;
+SYSCTL_INT(_hw_sdhci, OID_AUTO, quirk_set, CTLFLAG_RWTUN, &sdhci_quirk_set, 0,
+    "Mask of quirks to set");
+
+#define	RD1(slot, off)	SDHCI_READ_1((slot)->bus, (slot), (off))
+#define	RD2(slot, off)	SDHCI_READ_2((slot)->bus, (slot), (off))
+#define	RD4(slot, off)	SDHCI_READ_4((slot)->bus, (slot), (off))
+#define	RD_MULTI_4(slot, off, ptr, count)	\
+    SDHCI_READ_MULTI_4((slot)->bus, (slot), (off), (ptr), (count))
+
+#define	WR1(slot, off, val)	SDHCI_WRITE_1((slot)->bus, (slot), (off), (val))
+#define	WR2(slot, off, val)	SDHCI_WRITE_2((slot)->bus, (slot), (off), (val))
+#define	WR4(slot, off, val)	SDHCI_WRITE_4((slot)->bus, (slot), (off), (val))
+#define	WR_MULTI_4(slot, off, ptr, count)	\
+    SDHCI_WRITE_MULTI_4((slot)->bus, (slot), (off), (ptr), (count))
+
+static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock);
+static void sdhci_start(struct sdhci_slot *slot);
+static void sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data);
+
+static void sdhci_card_poll(void *);
+static void sdhci_card_task(void *, int);
+
+/* helper routines */
+static void sdhci_dumpregs(struct sdhci_slot *slot);
+static int slot_printf(struct sdhci_slot *slot, const char * fmt, ...)
+    __printflike(2, 3);
+
+#define	SDHCI_LOCK(_slot)		mtx_lock(&(_slot)->mtx)
+#define	SDHCI_UNLOCK(_slot)		mtx_unlock(&(_slot)->mtx)
+#define	SDHCI_LOCK_INIT(_slot) \
+	mtx_init(&_slot->mtx, "SD slot mtx", "sdhci", MTX_DEF)
+#define	SDHCI_LOCK_DESTROY(_slot)	mtx_destroy(&_slot->mtx);
+#define	SDHCI_ASSERT_LOCKED(_slot)	mtx_assert(&_slot->mtx, MA_OWNED);
+#define	SDHCI_ASSERT_UNLOCKED(_slot)	mtx_assert(&_slot->mtx, MA_NOTOWNED);
+
+#define	SDHCI_DEFAULT_MAX_FREQ	50
+
+#define	SDHCI_200_MAX_DIVIDER	256
+#define	SDHCI_300_MAX_DIVIDER	2046
+
+#define	SDHCI_CARD_PRESENT_TICKS	(hz / 5)
+#define	SDHCI_INSERT_DELAY_TICKS	(hz / 2)
+
+/*
+ * Broadcom BCM577xx Controller Constants
+ */
+/* Maximum divider supported by the default clock source. */
+#define	BCM577XX_DEFAULT_MAX_DIVIDER	256
+/* Alternative clock's base frequency. */
+#define	BCM577XX_ALT_CLOCK_BASE		63000000
+
+#define	BCM577XX_HOST_CONTROL		0x198
+#define	BCM577XX_CTRL_CLKSEL_MASK	0xFFFFCFFF
+#define	BCM577XX_CTRL_CLKSEL_SHIFT	12
+#define	BCM577XX_CTRL_CLKSEL_DEFAULT	0x0
+#define	BCM577XX_CTRL_CLKSEL_64MHZ	0x3
+
+static void
+sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
+{
+
+	if (error != 0) {
+		printf("getaddr: error %d\n", error);
+		return;
+	}
+	*(bus_addr_t *)arg = segs[0].ds_addr;
+}
+
+static int
+slot_printf(struct sdhci_slot *slot, const char * fmt, ...)
+{
+	va_list ap;
+	int retval;
+
+	retval = printf("%s-slot%d: ",
+	    device_get_nameunit(slot->bus), slot->num);
+
+	va_start(ap, fmt);
+	retval += vprintf(fmt, ap);
+	va_end(ap);
+	return (retval);
+}
+
+static void
+sdhci_dumpregs(struct sdhci_slot *slot)
+{
+
+	slot_printf(slot,
+	    "============== REGISTER DUMP ==============\n");
+
+	slot_printf(slot, "Sys addr: 0x%08x | Version:  0x%08x\n",
+	    RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION));
+	slot_printf(slot, "Blk size: 0x%08x | Blk cnt:  0x%08x\n",
+	    RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT));
+	slot_printf(slot, "Argument: 0x%08x | Trn mode: 0x%08x\n",
+	    RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE));
+	slot_printf(slot, "Present:  0x%08x | Host ctl: 0x%08x\n",
+	    RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL));
+	slot_printf(slot, "Power:    0x%08x | Blk gap:  0x%08x\n",
+	    RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL));
+	slot_printf(slot, "Wake-up:  0x%08x | Clock:    0x%08x\n",
+	    RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL));
+	slot_printf(slot, "Timeout:  0x%08x | Int stat: 0x%08x\n",
+	    RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS));
+	slot_printf(slot, "Int enab: 0x%08x | Sig enab: 0x%08x\n",
+	    RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE));
+	slot_printf(slot, "AC12 err: 0x%08x | Host ctl2: 0x%08x\n",
+	    RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_HOST_CONTROL2));
+	slot_printf(slot, "Caps:     0x%08x | Caps2:    0x%08x\n",
+	    RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_CAPABILITIES2));
+	slot_printf(slot, "Max curr: 0x%08x | ADMA err: 0x%08x\n",
+	    RD4(slot, SDHCI_MAX_CURRENT), RD1(slot, SDHCI_ADMA_ERR));
+	slot_printf(slot, "ADMA addr: 0x%08x | Slot int: 0x%08x\n",
+	    RD4(slot, SDHCI_ADMA_ADDRESS_LO), RD2(slot, SDHCI_SLOT_INT_STATUS));
+
+	slot_printf(slot,
+	    "===========================================\n");
+}
+
+static void
+sdhci_reset(struct sdhci_slot *slot, uint8_t mask)
+{
+	int timeout;
+	uint32_t clock;
+
+	if (slot->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
+		if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot))
+			return;
+	}
+
+	/* Some controllers need this kick or reset won't work. */
+	if ((mask & SDHCI_RESET_ALL) == 0 &&
+	    (slot->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) {
+		/* This is to force an update */
+		clock = slot->clock;
+		slot->clock = 0;
+		sdhci_set_clock(slot, clock);
+	}
+
+	if (mask & SDHCI_RESET_ALL) {
+		slot->clock = 0;
+		slot->power = 0;
+	}
+
+	WR1(slot, SDHCI_SOFTWARE_RESET, mask);
+
+	if (slot->quirks & SDHCI_QUIRK_WAITFOR_RESET_ASSERTED) {
+		/*
+		 * Resets on TI OMAPs and AM335x are incompatible with SDHCI
+		 * specification.  The reset bit has internal propagation delay,
+		 * so a fast read after write returns 0 even if reset process is
+		 * in progress.  The workaround is to poll for 1 before polling
+		 * for 0.  In the worst case, if we miss seeing it asserted the
+		 * time we spent waiting is enough to ensure the reset finishes.
+		 */
+		timeout = 10000;
+		while ((RD1(slot, SDHCI_SOFTWARE_RESET) & mask) != mask) {
+			if (timeout <= 0)
+				break;
+			timeout--;
+			DELAY(1);
+		}
+	}
+
+	/* Wait max 100 ms */
+	timeout = 10000;
+	/* Controller clears the bits when it's done */
+	while (RD1(slot, SDHCI_SOFTWARE_RESET) & mask) {
+		if (timeout <= 0) {
+			slot_printf(slot, "Reset 0x%x never completed.\n",
+			    mask);
+			sdhci_dumpregs(slot);
+			return;
+		}
+		timeout--;
+		DELAY(10);
+	}
+}
+
+static void
+sdhci_init(struct sdhci_slot *slot)
+{
+
+	sdhci_reset(slot, SDHCI_RESET_ALL);
+
+	/* Enable interrupts. */
+	slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
+	    SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
+	    SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
+	    SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
+	    SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE |
+	    SDHCI_INT_ACMD12ERR;
+
+	if (!(slot->quirks & SDHCI_QUIRK_POLL_CARD_PRESENT) &&
+	    !(slot->opt & SDHCI_NON_REMOVABLE)) {
+		slot->intmask |= SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT;
+	}
+
+	WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
+	WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
+}
+
+static void
+sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock)
+{
+	uint32_t clk_base;
+	uint32_t clk_sel;
+	uint32_t res;
+	uint16_t clk;
+	uint16_t div;
+	int timeout;
+
+	if (clock == slot->clock)
+		return;
+	slot->clock = clock;
+
+	/* Turn off the clock. */
+	clk = RD2(slot, SDHCI_CLOCK_CONTROL);
+	WR2(slot, SDHCI_CLOCK_CONTROL, clk & ~SDHCI_CLOCK_CARD_EN);
+	/* If no clock requested - leave it so. */
+	if (clock == 0)
+		return;
+
+	/* Determine the clock base frequency */
+	clk_base = slot->max_clk;
+	if (slot->quirks & SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC) {
+		clk_sel = RD2(slot, BCM577XX_HOST_CONTROL) &
+		    BCM577XX_CTRL_CLKSEL_MASK;
+
+		/*
+		 * Select clock source appropriate for the requested frequency.
+		 */
+		if ((clk_base / BCM577XX_DEFAULT_MAX_DIVIDER) > clock) {
+			clk_base = BCM577XX_ALT_CLOCK_BASE;
+			clk_sel |= (BCM577XX_CTRL_CLKSEL_64MHZ <<
+			    BCM577XX_CTRL_CLKSEL_SHIFT);
+		} else {
+			clk_sel |= (BCM577XX_CTRL_CLKSEL_DEFAULT <<
+			    BCM577XX_CTRL_CLKSEL_SHIFT);
+		}
+
+		WR2(slot, BCM577XX_HOST_CONTROL, clk_sel);
+	}
+
+	/* Recalculate timeout clock frequency based on the new sd clock. */
+	if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
+		slot->timeout_clk = slot->clock / 1000;
+
+	if (slot->version < SDHCI_SPEC_300) {
+		/* Looking for highest freq <= clock. */
+		res = clk_base;
+		for (div = 1; div < SDHCI_200_MAX_DIVIDER; div <<= 1) {
+			if (res <= clock)
+				break;
+			res >>= 1;
+		}
+		/* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */
+		div >>= 1;
+	} else {
+		/* Version 3.0 divisors are multiples of two up to 1023 * 2 */
+		if (clock >= clk_base)
+			div = 0;
+		else {
+			for (div = 2; div < SDHCI_300_MAX_DIVIDER; div += 2) {
+				if ((clk_base / div) <= clock)
+					break;
+			}
+		}
+		div >>= 1;
+	}
+
+	if (bootverbose || sdhci_debug)
+		slot_printf(slot, "Divider %d for freq %d (base %d)\n",
+			div, clock, clk_base);
+
+	/* Now we have got divider, set it. */
+	clk = (div & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT;
+	clk |= ((div >> SDHCI_DIVIDER_MASK_LEN) & SDHCI_DIVIDER_HI_MASK)
+		<< SDHCI_DIVIDER_HI_SHIFT;
+
+	WR2(slot, SDHCI_CLOCK_CONTROL, clk);
+	/* Enable clock. */
+	clk |= SDHCI_CLOCK_INT_EN;
+	WR2(slot, SDHCI_CLOCK_CONTROL, clk);
+	/* Wait up to 10 ms until it stabilize. */
+	timeout = 10;
+	while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL))
+		& SDHCI_CLOCK_INT_STABLE)) {
+		if (timeout == 0) {
+			slot_printf(slot,
+			    "Internal clock never stabilised.\n");
+			sdhci_dumpregs(slot);
+			return;
+		}
+		timeout--;
+		DELAY(1000);
+	}
+	/* Pass clock signal to the bus. */
+	clk |= SDHCI_CLOCK_CARD_EN;
+	WR2(slot, SDHCI_CLOCK_CONTROL, clk);
+}
+
+static void
+sdhci_set_power(struct sdhci_slot *slot, u_char power)
+{
+	uint8_t pwr;
+
+	if (slot->power == power)
+		return;
+
+	slot->power = power;
+
+	/* Turn off the power. */
+	pwr = 0;
+	WR1(slot, SDHCI_POWER_CONTROL, pwr);
+	/* If power down requested - leave it so. */
+	if (power == 0)
+		return;
+	/* Set voltage. */
+	switch (1 << power) {
+	case MMC_OCR_LOW_VOLTAGE:
+		pwr |= SDHCI_POWER_180;
+		break;
+	case MMC_OCR_290_300:
+	case MMC_OCR_300_310:
+		pwr |= SDHCI_POWER_300;
+		break;
+	case MMC_OCR_320_330:
+	case MMC_OCR_330_340:
+		pwr |= SDHCI_POWER_330;
+		break;
+	}
+	WR1(slot, SDHCI_POWER_CONTROL, pwr);
+	/* Turn on the power. */
+	pwr |= SDHCI_POWER_ON;
+	WR1(slot, SDHCI_POWER_CONTROL, pwr);
+
+	if (slot->quirks & SDHCI_QUIRK_INTEL_POWER_UP_RESET) {
+		WR1(slot, SDHCI_POWER_CONTROL, pwr | 0x10);
+		DELAY(10);
+		WR1(slot, SDHCI_POWER_CONTROL, pwr);
+		DELAY(300);
+	}
+}
+
+static void
+sdhci_read_block_pio(struct sdhci_slot *slot)
+{
+	uint32_t data;
+	char *buffer;
+	size_t left;
+
+	buffer = slot->curcmd->data->data;
+	buffer += slot->offset;
+	/* Transfer one block at a time. */
+	left = min(512, slot->curcmd->data->len - slot->offset);
+	slot->offset += left;
+
+	/* If we are too fast, broken controllers return zeroes. */
+	if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS)
+		DELAY(10);
+	/* Handle unaligned and aligned buffer cases. */
+	if ((intptr_t)buffer & 3) {
+		while (left > 3) {
+			data = RD4(slot, SDHCI_BUFFER);
+			buffer[0] = data;
+			buffer[1] = (data >> 8);
+			buffer[2] = (data >> 16);
+			buffer[3] = (data >> 24);
+			buffer += 4;
+			left -= 4;
+		}
+	} else {
+		RD_MULTI_4(slot, SDHCI_BUFFER,
+		    (uint32_t *)buffer, left >> 2);
+		left &= 3;
+	}
+	/* Handle uneven size case. */
+	if (left > 0) {
+		data = RD4(slot, SDHCI_BUFFER);
+		while (left > 0) {
+			*(buffer++) = data;
+			data >>= 8;
+			left--;
+		}
+	}
+}
+
+static void
+sdhci_write_block_pio(struct sdhci_slot *slot)
+{
+	uint32_t data = 0;
+	char *buffer;
+	size_t left;
+
+	buffer = slot->curcmd->data->data;
+	buffer += slot->offset;
+	/* Transfer one block at a time. */
+	left = min(512, slot->curcmd->data->len - slot->offset);
+	slot->offset += left;
+
+	/* Handle unaligned and aligned buffer cases. */
+	if ((intptr_t)buffer & 3) {
+		while (left > 3) {
+			data = buffer[0] +
+			    (buffer[1] << 8) +
+			    (buffer[2] << 16) +
+			    (buffer[3] << 24);
+			left -= 4;
+			buffer += 4;
+			WR4(slot, SDHCI_BUFFER, data);
+		}
+	} else {
+		WR_MULTI_4(slot, SDHCI_BUFFER,
+		    (uint32_t *)buffer, left >> 2);
+		left &= 3;
+	}
+	/* Handle uneven size case. */
+	if (left > 0) {
+		while (left > 0) {
+			data <<= 8;
+			data += *(buffer++);
+			left--;
+		}
+		WR4(slot, SDHCI_BUFFER, data);
+	}
+}
+
+static void
+sdhci_transfer_pio(struct sdhci_slot *slot)
+{
+
+	/* Read as many blocks as possible. */
+	if (slot->curcmd->data->flags & MMC_DATA_READ) {
+		while (RD4(slot, SDHCI_PRESENT_STATE) &
+		    SDHCI_DATA_AVAILABLE) {
+			sdhci_read_block_pio(slot);
+			if (slot->offset >= slot->curcmd->data->len)
+				break;
+		}
+	} else {
+		while (RD4(slot, SDHCI_PRESENT_STATE) &
+		    SDHCI_SPACE_AVAILABLE) {
+			sdhci_write_block_pio(slot);
+			if (slot->offset >= slot->curcmd->data->len)
+				break;
+		}
+	}
+}
+
+static void
+sdhci_card_task(void *arg, int pending __unused)
+{
+	struct sdhci_slot *slot = arg;
+	device_t d;
+
+	SDHCI_LOCK(slot);
+	if (SDHCI_GET_CARD_PRESENT(slot->bus, slot)) {
+		if (slot->dev == NULL) {
+			/* If card is present - attach mmc bus. */
+			if (bootverbose || sdhci_debug)
+				slot_printf(slot, "Card inserted\n");
+			slot->dev = device_add_child(slot->bus, "mmc", -1);
+			device_set_ivars(slot->dev, slot);
+			SDHCI_UNLOCK(slot);
+			device_probe_and_attach(slot->dev);
+		} else
+			SDHCI_UNLOCK(slot);
+	} else {
+		if (slot->dev != NULL) {
+			/* If no card present - detach mmc bus. */
+			if (bootverbose || sdhci_debug)
+				slot_printf(slot, "Card removed\n");
+			d = slot->dev;
+			slot->dev = NULL;
+			SDHCI_UNLOCK(slot);
+			device_delete_child(slot->bus, d);
+		} else
+			SDHCI_UNLOCK(slot);
+	}
+}
+
+static void
+sdhci_handle_card_present_locked(struct sdhci_slot *slot, bool is_present)
+{
+	bool was_present;
+
+	/*
+	 * If there was no card and now there is one, schedule the task to
+	 * create the child device after a short delay.  The delay is to
+	 * debounce the card insert (sometimes the card detect pin stabilizes
+	 * before the other pins have made good contact).
+	 *
+	 * If there was a card present and now it's gone, immediately schedule
+	 * the task to delete the child device.  No debouncing -- gone is gone,
+	 * because once power is removed, a full card re-init is needed, and
+	 * that happens by deleting and recreating the child device.
+	 */
+	was_present = slot->dev != NULL;
+	if (!was_present && is_present) {
+		taskqueue_enqueue_timeout(taskqueue_swi_giant,
+		    &slot->card_delayed_task, -SDHCI_INSERT_DELAY_TICKS);
+	} else if (was_present && !is_present) {
+		taskqueue_enqueue(taskqueue_swi_giant, &slot->card_task);
+	}
+}
+
+void
+sdhci_handle_card_present(struct sdhci_slot *slot, bool is_present)
+{
+
+	SDHCI_LOCK(slot);
+	sdhci_handle_card_present_locked(slot, is_present);
+	SDHCI_UNLOCK(slot);
+}
+
+static void
+sdhci_card_poll(void *arg)
+{
+	struct sdhci_slot *slot = arg;
+
+	sdhci_handle_card_present(slot,
+	    SDHCI_GET_CARD_PRESENT(slot->bus, slot));
+	callout_reset(&slot->card_poll_callout, SDHCI_CARD_PRESENT_TICKS,
+	    sdhci_card_poll, slot);
+}
+
+int
+sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num)
+{
+	uint32_t caps, caps2, freq, host_caps;
+	int err;
+
+	SDHCI_LOCK_INIT(slot);
+	slot->num = num;
+	slot->bus = dev;
+
+	/* Allocate DMA tag. */
+	err = bus_dma_tag_create(bus_get_dma_tag(dev),
+	    DMA_BLOCK_SIZE, 0, BUS_SPACE_MAXADDR_32BIT,
+	    BUS_SPACE_MAXADDR, NULL, NULL,
+	    DMA_BLOCK_SIZE, 1, DMA_BLOCK_SIZE,
+	    BUS_DMA_ALLOCNOW, NULL, NULL,
+	    &slot->dmatag);
+	if (err != 0) {
+		device_printf(dev, "Can't create DMA tag\n");
+		SDHCI_LOCK_DESTROY(slot);
+		return (err);
+	}
+	/* Allocate DMA memory. */
+	err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem,
+	    BUS_DMA_NOWAIT, &slot->dmamap);
+	if (err != 0) {
+		device_printf(dev, "Can't alloc DMA memory\n");
+		SDHCI_LOCK_DESTROY(slot);
+		return (err);
+	}
+	/* Map the memory. */
+	err = bus_dmamap_load(slot->dmatag, slot->dmamap,
+	    (void *)slot->dmamem, DMA_BLOCK_SIZE,
+	    sdhci_getaddr, &slot->paddr, 0);
+	if (err != 0 || slot->paddr == 0) {
+		device_printf(dev, "Can't load DMA memory\n");
+		SDHCI_LOCK_DESTROY(slot);
+		if (err)
+			return (err);
+		else
+			return (EFAULT);
+	}
+
+	/* Initialize slot. */
+	sdhci_init(slot);
+	slot->version = (RD2(slot, SDHCI_HOST_VERSION)
+		>> SDHCI_SPEC_VER_SHIFT) & SDHCI_SPEC_VER_MASK;
+	if (slot->quirks & SDHCI_QUIRK_MISSING_CAPS) {
+		caps = slot->caps;
+		caps2 = slot->caps2;
+	} else {
+		caps = RD4(slot, SDHCI_CAPABILITIES);
+		if (slot->version >= SDHCI_SPEC_300)
+			caps2 = RD4(slot, SDHCI_CAPABILITIES2);
+		else
+			caps2 = 0;
+	}
+	/* Calculate base clock frequency. */
+	if (slot->version >= SDHCI_SPEC_300)
+		freq = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
+		    SDHCI_CLOCK_BASE_SHIFT;
+	else
+		freq = (caps & SDHCI_CLOCK_BASE_MASK) >>
+		    SDHCI_CLOCK_BASE_SHIFT;
+	if (freq != 0)
+		slot->max_clk = freq * 1000000;
+	/*
+	 * If the frequency wasn't in the capabilities and the hardware driver
+	 * hasn't already set max_clk we're probably not going to work right
+	 * with an assumption, so complain about it.
+	 */
+	if (slot->max_clk == 0) {
+		slot->max_clk = SDHCI_DEFAULT_MAX_FREQ * 1000000;
+		device_printf(dev, "Hardware doesn't specify base clock "
+		    "frequency, using %dMHz as default.\n",
+		    SDHCI_DEFAULT_MAX_FREQ);
+	}
+	/* Calculate/set timeout clock frequency. */
+	if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) {
+		slot->timeout_clk = slot->max_clk / 1000;
+	} else if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_1MHZ) {
+		slot->timeout_clk = 1000;
+	} else {
+		slot->timeout_clk = (caps & SDHCI_TIMEOUT_CLK_MASK) >>
+		    SDHCI_TIMEOUT_CLK_SHIFT;
+		if (caps & SDHCI_TIMEOUT_CLK_UNIT)
+			slot->timeout_clk *= 1000;
+	}
+	/*
+	 * If the frequency wasn't in the capabilities and the hardware driver
+	 * hasn't already set timeout_clk we'll probably work okay using the
+	 * max timeout, but still mention it.
+	 */
+	if (slot->timeout_clk == 0) {
+		device_printf(dev, "Hardware doesn't specify timeout clock "
+		    "frequency, setting BROKEN_TIMEOUT quirk.\n");
+		slot->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
+	}
+
+	slot->host.f_min = SDHCI_MIN_FREQ(slot->bus, slot);
+	slot->host.f_max = slot->max_clk;
+	slot->host.host_ocr = 0;
+	if (caps & SDHCI_CAN_VDD_330)
+	    slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340;
+	if (caps & SDHCI_CAN_VDD_300)
+	    slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310;
+	if (caps & SDHCI_CAN_VDD_180)
+	    slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE;
+	if (slot->host.host_ocr == 0) {
+		device_printf(dev, "Hardware doesn't report any "
+		    "support voltages.\n");
+	}
+	host_caps = MMC_CAP_4_BIT_DATA;
+	if (caps & SDHCI_CAN_DO_8BITBUS)
+		host_caps |= MMC_CAP_8_BIT_DATA;
+	if (caps & SDHCI_CAN_DO_HISPD)
+		host_caps |= MMC_CAP_HSPEED;
+	if (slot->quirks & SDHCI_QUIRK_BOOT_NOACC)
+		host_caps |= MMC_CAP_BOOT_NOACC;
+	if (slot->quirks & SDHCI_QUIRK_WAIT_WHILE_BUSY)
+		host_caps |= MMC_CAP_WAIT_WHILE_BUSY;
+	if (caps2 & (SDHCI_CAN_SDR50 | SDHCI_CAN_SDR104 | SDHCI_CAN_DDR50))
+		host_caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
+	if (caps2 & SDHCI_CAN_SDR104) {
+		host_caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
+		if (!(slot->quirks & SDHCI_QUIRK_BROKEN_MMC_HS200))
+			host_caps |= MMC_CAP_MMC_HS200;
+	} else if (caps2 & SDHCI_CAN_SDR50)
+		host_caps |= MMC_CAP_UHS_SDR50;
+	if (caps2 & SDHCI_CAN_DDR50 &&
+	    !(slot->quirks & SDHCI_QUIRK_BROKEN_UHS_DDR50))
+		host_caps |= MMC_CAP_UHS_DDR50;
+	if (slot->quirks & SDHCI_QUIRK_MMC_DDR52)
+		host_caps |= MMC_CAP_MMC_DDR52;
+	if (slot->quirks & SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 &&
+	    caps2 & SDHCI_CAN_MMC_HS400)
+		host_caps |= MMC_CAP_MMC_HS400;
+	host_caps |= MMC_CAP_SIGNALING_330;
+	if (host_caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
+	    MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_DDR50 |
+	    MMC_CAP_MMC_DDR52_180 | MMC_CAP_MMC_HS200_180 |
+	    MMC_CAP_MMC_HS400_180))
+		host_caps |= MMC_CAP_SIGNALING_180;
+	if (caps & SDHCI_CTRL2_DRIVER_TYPE_A)
+		host_caps |= MMC_CAP_DRIVER_TYPE_A;
+	if (caps & SDHCI_CTRL2_DRIVER_TYPE_C)
+		host_caps |= MMC_CAP_DRIVER_TYPE_C;
+	if (caps & SDHCI_CTRL2_DRIVER_TYPE_D)
+		host_caps |= MMC_CAP_DRIVER_TYPE_D;
+	slot->host.caps = host_caps;
+
+	/* Decide if we have usable DMA. */
+	if (caps & SDHCI_CAN_DO_DMA)
+		slot->opt |= SDHCI_HAVE_DMA;
+
+	if (slot->quirks & SDHCI_QUIRK_BROKEN_DMA)
+		slot->opt &= ~SDHCI_HAVE_DMA;
+	if (slot->quirks & SDHCI_QUIRK_FORCE_DMA)
+		slot->opt |= SDHCI_HAVE_DMA;
+	if (slot->quirks & SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE)
+		slot->opt |= SDHCI_NON_REMOVABLE;
+
+	/*
+	 * Use platform-provided transfer backend
+	 * with PIO as a fallback mechanism
+	 */
+	if (slot->opt & SDHCI_PLATFORM_TRANSFER)
+		slot->opt &= ~SDHCI_HAVE_DMA;
+
+	if (bootverbose || sdhci_debug) {
+		slot_printf(slot,
+		    "%uMHz%s %s VDD:%s%s%s VCCQ: 3.3V%s%s DRV: B%s%s%s %s\n",
+		    slot->max_clk / 1000000,
+		    (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "",
+		    (host_caps & MMC_CAP_8_BIT_DATA) ? "8bits" :
+			((host_caps & MMC_CAP_4_BIT_DATA) ? "4bits" : "1bit"),
+		    (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "",
+		    (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "",
+		    (caps & SDHCI_CAN_VDD_180) ? " 1.8V" : "",
+		    (host_caps & MMC_CAP_SIGNALING_180) ? " 1.8V" : "",
+		    (host_caps & MMC_CAP_SIGNALING_120) ? " 1.2V" : "",
+		    (caps & SDHCI_CTRL2_DRIVER_TYPE_A) ? "A" : "",
+		    (caps & SDHCI_CTRL2_DRIVER_TYPE_C) ? "C" : "",
+		    (caps & SDHCI_CTRL2_DRIVER_TYPE_D) ? "D" : "",
+		    (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO");
+		if (host_caps & (MMC_CAP_MMC_DDR52 | MMC_CAP_MMC_HS200 |
+		    MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE))
+			slot_printf(slot, "eMMC:%s%s%s%s\n",
+			    (host_caps & MMC_CAP_MMC_DDR52) ? " DDR52" : "",
+			    (host_caps & MMC_CAP_MMC_HS200) ? " HS200" : "",
+			    (host_caps & MMC_CAP_MMC_HS400) ? " HS400" : "",
+			    ((host_caps &
+			    (MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE)) ==
+			    (MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE)) ?
+			    " HS400ES" : "");
+		if (host_caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
+		    MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104))
+			slot_printf(slot, "UHS-I:%s%s%s%s%s\n",
+			    (host_caps & MMC_CAP_UHS_SDR12) ? " SDR12" : "",
+			    (host_caps & MMC_CAP_UHS_SDR25) ? " SDR25" : "",
+			    (host_caps & MMC_CAP_UHS_SDR50) ? " SDR50" : "",
+			    (host_caps & MMC_CAP_UHS_SDR104) ? " SDR104" : "",
+			    (host_caps & MMC_CAP_UHS_DDR50) ? " DDR50" : "");
+		sdhci_dumpregs(slot);
+	}
+
+	slot->timeout = 10;
+	SYSCTL_ADD_INT(device_get_sysctl_ctx(slot->bus),
+	    SYSCTL_CHILDREN(device_get_sysctl_tree(slot->bus)), OID_AUTO,
+	    "timeout", CTLFLAG_RW, &slot->timeout, 0,
+	    "Maximum timeout for SDHCI transfers (in secs)");
+	TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot);
+	TIMEOUT_TASK_INIT(taskqueue_swi_giant, &slot->card_delayed_task, 0,
+		sdhci_card_task, slot);
+	callout_init(&slot->card_poll_callout, 1);
+	callout_init_mtx(&slot->timeout_callout, &slot->mtx, 0);
+
+	if ((slot->quirks & SDHCI_QUIRK_POLL_CARD_PRESENT) &&
+	    !(slot->opt & SDHCI_NON_REMOVABLE)) {
+		callout_reset(&slot->card_poll_callout,
+		    SDHCI_CARD_PRESENT_TICKS, sdhci_card_poll, slot);
+	}
+
+	return (0);
+}
+
+void
+sdhci_start_slot(struct sdhci_slot *slot)
+{
+
+	sdhci_card_task(slot, 0);
+}
+
+int
+sdhci_cleanup_slot(struct sdhci_slot *slot)
+{
+	device_t d;
+
+	callout_drain(&slot->timeout_callout);
+	callout_drain(&slot->card_poll_callout);
+	taskqueue_drain(taskqueue_swi_giant, &slot->card_task);
+	taskqueue_drain_timeout(taskqueue_swi_giant, &slot->card_delayed_task);
+
+	SDHCI_LOCK(slot);
+	d = slot->dev;
+	slot->dev = NULL;
+	SDHCI_UNLOCK(slot);
+	if (d != NULL)
+		device_delete_child(slot->bus, d);
+
+	SDHCI_LOCK(slot);
+	sdhci_reset(slot, SDHCI_RESET_ALL);
+	SDHCI_UNLOCK(slot);
+	bus_dmamap_unload(slot->dmatag, slot->dmamap);
+	bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap);
+	bus_dma_tag_destroy(slot->dmatag);
+
+	SDHCI_LOCK_DESTROY(slot);
+
+	return (0);
+}
+
+int
+sdhci_generic_suspend(struct sdhci_slot *slot)
+{
+
+	sdhci_reset(slot, SDHCI_RESET_ALL);
+
+	return (0);
+}
+
+int
+sdhci_generic_resume(struct sdhci_slot *slot)
+{
+
+	sdhci_init(slot);
+
+	return (0);
+}
+
+uint32_t
+sdhci_generic_min_freq(device_t brdev __unused, struct sdhci_slot *slot)
+{
+
+	if (slot->version >= SDHCI_SPEC_300)
+		return (slot->max_clk / SDHCI_300_MAX_DIVIDER);
+	else
+		return (slot->max_clk / SDHCI_200_MAX_DIVIDER);
+}
+
+bool
+sdhci_generic_get_card_present(device_t brdev __unused, struct sdhci_slot *slot)
+{
+
+	if (slot->opt & SDHCI_NON_REMOVABLE)
+		return true;
+
+	return (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
+}
+
+void
+sdhci_generic_set_uhs_timing(device_t brdev __unused, struct sdhci_slot *slot)
+{
+	struct mmc_ios *ios;
+	uint16_t hostctrl2;
+
+	if (slot->version < SDHCI_SPEC_300)
+		return;
+
+	ios = &slot->host.ios;
+	sdhci_set_clock(slot, 0);
+	hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
+	hostctrl2 &= ~SDHCI_CTRL2_UHS_MASK;
+	if (ios->timing == bus_timing_mmc_hs400 ||
+	    ios->timing == bus_timing_mmc_hs400es)
+		hostctrl2 |= SDHCI_CTRL2_MMC_HS400;
+	else if (ios->clock > SD_SDR50_MAX)
+		hostctrl2 |= SDHCI_CTRL2_UHS_SDR104;
+	else if (ios->clock > SD_SDR25_MAX)
+		hostctrl2 |= SDHCI_CTRL2_UHS_SDR50;
+	else if (ios->clock > SD_SDR12_MAX) {
+		if (ios->timing == bus_timing_uhs_ddr50 ||
+		    ios->timing == bus_timing_mmc_ddr52)
+			hostctrl2 |= SDHCI_CTRL2_UHS_DDR50;
+		else
+			hostctrl2 |= SDHCI_CTRL2_UHS_SDR25;
+	} else if (ios->clock > SD_MMC_CARD_ID_FREQUENCY)
+		hostctrl2 |= SDHCI_CTRL2_UHS_SDR12;
+	WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2);
+	sdhci_set_clock(slot, ios->clock);
+}
+
+int
+sdhci_generic_update_ios(device_t brdev, device_t reqdev)
+{
+	struct sdhci_slot *slot = device_get_ivars(reqdev);
+	struct mmc_ios *ios = &slot->host.ios;
+
+	SDHCI_LOCK(slot);
+	/* Do full reset on bus power down to clear from any state. */
+	if (ios->power_mode == power_off) {
+		WR4(slot, SDHCI_SIGNAL_ENABLE, 0);
+		sdhci_init(slot);
+	}
+	/* Configure the bus. */
+	sdhci_set_clock(slot, ios->clock);
+	sdhci_set_power(slot, (ios->power_mode == power_off) ? 0 : ios->vdd);
+	if (ios->bus_width == bus_width_8) {
+		slot->hostctrl |= SDHCI_CTRL_8BITBUS;
+		slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
+	} else if (ios->bus_width == bus_width_4) {
+		slot->hostctrl &= ~SDHCI_CTRL_8BITBUS;
+		slot->hostctrl |= SDHCI_CTRL_4BITBUS;
+	} else if (ios->bus_width == bus_width_1) {
+		slot->hostctrl &= ~SDHCI_CTRL_8BITBUS;
+		slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
+	} else {
+		panic("Invalid bus width: %d", ios->bus_width);
+	}
+	if (ios->clock > SD_SDR12_MAX &&
+	    !(slot->quirks & SDHCI_QUIRK_DONT_SET_HISPD_BIT))
+		slot->hostctrl |= SDHCI_CTRL_HISPD;
+	else
+		slot->hostctrl &= ~SDHCI_CTRL_HISPD;
+	WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl);
+	SDHCI_SET_UHS_TIMING(brdev, slot);
+	/* Some controllers like reset after bus changes. */
+	if (slot->quirks & SDHCI_QUIRK_RESET_ON_IOS)
+		sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
+
+	SDHCI_UNLOCK(slot);
+	return (0);
+}
+
+int
+sdhci_generic_switch_vccq(device_t brdev __unused, device_t reqdev)
+{
+	struct sdhci_slot *slot = device_get_ivars(reqdev);
+	enum mmc_vccq vccq;
+	int err;
+	uint16_t hostctrl2;
+
+	if (slot->version < SDHCI_SPEC_300)
+		return (0);
+
+	err = 0;
+	vccq = slot->host.ios.vccq;
+	SDHCI_LOCK(slot);
+	sdhci_set_clock(slot, 0);
+	hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
+	switch (vccq) {
+	case vccq_330:
+		if (!(hostctrl2 & SDHCI_CTRL2_S18_ENABLE))
+			goto done;
+		hostctrl2 &= ~SDHCI_CTRL2_S18_ENABLE;
+		WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2);
+		DELAY(5000);
+		hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
+		if (!(hostctrl2 & SDHCI_CTRL2_S18_ENABLE))
+			goto done;
+		err = EAGAIN;
+		break;
+	case vccq_180:
+		if (!(slot->host.caps & MMC_CAP_SIGNALING_180)) {
+			err = EINVAL;
+			goto done;
+		}
+		if (hostctrl2 & SDHCI_CTRL2_S18_ENABLE)
+			goto done;
+		hostctrl2 |= SDHCI_CTRL2_S18_ENABLE;
+		WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2);
+		DELAY(5000);
+		hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
+		if (hostctrl2 & SDHCI_CTRL2_S18_ENABLE)
+			goto done;
+		err = EAGAIN;
+		break;
+	default:
+		slot_printf(slot,
+		    "Attempt to set unsupported signaling voltage\n");
+		err = EINVAL;
+		break;
+	}
+done:
+	sdhci_set_clock(slot, slot->host.ios.clock);
+	SDHCI_UNLOCK(slot);
+	return (err);
+}
+
+static void
+sdhci_req_done(struct sdhci_slot *slot)
+{
+	struct mmc_request *req;
+
+	if (slot->req != NULL && slot->curcmd != NULL) {
+		callout_stop(&slot->timeout_callout);
+		req = slot->req;
+		slot->req = NULL;
+		slot->curcmd = NULL;
+		req->done(req);
+	}
+}
+
+static void
+sdhci_timeout(void *arg)
+{
+	struct sdhci_slot *slot = arg;
+
+	if (slot->curcmd != NULL) {
+		slot_printf(slot, " Controller timeout\n");
+		sdhci_dumpregs(slot);
+		sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
+		slot->curcmd->error = MMC_ERR_TIMEOUT;
+		sdhci_req_done(slot);
+	} else {
+		slot_printf(slot, " Spurious timeout - no active command\n");
+	}
+}
+
+static void
+sdhci_set_transfer_mode(struct sdhci_slot *slot, struct mmc_data *data)
+{
+	uint16_t mode;
+
+	if (data == NULL)
+		return;
+
+	mode = SDHCI_TRNS_BLK_CNT_EN;
+	if (data->len > 512)
+		mode |= SDHCI_TRNS_MULTI;
+	if (data->flags & MMC_DATA_READ)
+		mode |= SDHCI_TRNS_READ;
+	if (slot->req->stop)
+		mode |= SDHCI_TRNS_ACMD12;
+	if (slot->flags & SDHCI_USE_DMA)
+		mode |= SDHCI_TRNS_DMA;
+
+	WR2(slot, SDHCI_TRANSFER_MODE, mode);
+}
+
+static void
+sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd)
+{
+	int flags, timeout;
+	uint32_t mask;
+
+	slot->curcmd = cmd;
+	slot->cmd_done = 0;
+
+	cmd->error = MMC_ERR_NONE;
+
+	/* This flags combination is not supported by controller. */
+	if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
+		slot_printf(slot, "Unsupported response type!\n");
+		cmd->error = MMC_ERR_FAILED;
+		sdhci_req_done(slot);
+		return;
+	}
+
+	/*
+	 * Do not issue command if there is no card, clock or power.
+	 * Controller will not detect timeout without clock active.
+	 */
+	if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot) ||
+	    slot->power == 0 ||
+	    slot->clock == 0) {
+		cmd->error = MMC_ERR_FAILED;
+		sdhci_req_done(slot);
+		return;
+	}
+	/* Always wait for free CMD bus. */
+	mask = SDHCI_CMD_INHIBIT;
+	/* Wait for free DAT if we have data or busy signal. */
+	if (cmd->data || (cmd->flags & MMC_RSP_BUSY))
+		mask |= SDHCI_DAT_INHIBIT;
+	/* We shouldn't wait for DAT for stop commands. */
+	if (cmd == slot->req->stop)
+		mask &= ~SDHCI_DAT_INHIBIT;
+	/*
+	 *  Wait for bus no more then 250 ms.  Typically there will be no wait
+	 *  here at all, but when writing a crash dump we may be bypassing the
+	 *  host platform's interrupt handler, and in some cases that handler
+	 *  may be working around hardware quirks such as not respecting r1b
+	 *  busy indications.  In those cases, this wait-loop serves the purpose
+	 *  of waiting for the prior command and data transfers to be done, and
+	 *  SD cards are allowed to take up to 250ms for write and erase ops.
+	 *  (It's usually more like 20-30ms in the real world.)
+	 */
+	timeout = 250;
+	while (mask & RD4(slot, SDHCI_PRESENT_STATE)) {
+		if (timeout == 0) {
+			slot_printf(slot, "Controller never released "
+			    "inhibit bit(s).\n");
+			sdhci_dumpregs(slot);
+			cmd->error = MMC_ERR_FAILED;
+			sdhci_req_done(slot);
+			return;
+		}
+		timeout--;
+		DELAY(1000);
+	}
+
+	/* Prepare command flags. */
+	if (!(cmd->flags & MMC_RSP_PRESENT))
+		flags = SDHCI_CMD_RESP_NONE;
+	else if (cmd->flags & MMC_RSP_136)
+		flags = SDHCI_CMD_RESP_LONG;
+	else if (cmd->flags & MMC_RSP_BUSY)
+		flags = SDHCI_CMD_RESP_SHORT_BUSY;
+	else
+		flags = SDHCI_CMD_RESP_SHORT;
+	if (cmd->flags & MMC_RSP_CRC)
+		flags |= SDHCI_CMD_CRC;
+	if (cmd->flags & MMC_RSP_OPCODE)
+		flags |= SDHCI_CMD_INDEX;
+	if (cmd->data)
+		flags |= SDHCI_CMD_DATA;
+	if (cmd->opcode == MMC_STOP_TRANSMISSION)
+		flags |= SDHCI_CMD_TYPE_ABORT;
+	/* Prepare data. */
+	sdhci_start_data(slot, cmd->data);
+	/*
+	 * Interrupt aggregation: To reduce total number of interrupts
+	 * group response interrupt with data interrupt when possible.
+	 * If there going to be data interrupt, mask response one.
+	 */
+	if (slot->data_done == 0) {
+		WR4(slot, SDHCI_SIGNAL_ENABLE,
+		    slot->intmask &= ~SDHCI_INT_RESPONSE);
+	}
+	/* Set command argument. */
+	WR4(slot, SDHCI_ARGUMENT, cmd->arg);
+	/* Set data transfer mode. */
+	sdhci_set_transfer_mode(slot, cmd->data);
+	/* Start command. */
+	WR2(slot, SDHCI_COMMAND_FLAGS, (cmd->opcode << 8) | (flags & 0xff));
+	/* Start timeout callout. */
+	callout_reset(&slot->timeout_callout, slot->timeout * hz,
+	    sdhci_timeout, slot);
+}
+
+static void
+sdhci_finish_command(struct sdhci_slot *slot)
+{
+	int i;
+	uint32_t val;
+	uint8_t extra;
+
+	slot->cmd_done = 1;
+	/*
+	 * Interrupt aggregation: Restore command interrupt.
+	 * Main restore point for the case when command interrupt
+	 * happened first.
+	 */
+	WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |= SDHCI_INT_RESPONSE);
+	/* In case of error - reset host and return. */
+	if (slot->curcmd->error) {
+		sdhci_reset(slot, SDHCI_RESET_CMD);
+		sdhci_reset(slot, SDHCI_RESET_DATA);
+		sdhci_start(slot);
+		return;
+	}
+	/* If command has response - fetch it. */
+	if (slot->curcmd->flags & MMC_RSP_PRESENT) {
+		if (slot->curcmd->flags & MMC_RSP_136) {
+			/* CRC is stripped so we need one byte shift. */
+			extra = 0;
+			for (i = 0; i < 4; i++) {
+				val = RD4(slot, SDHCI_RESPONSE + i * 4);
+				if (slot->quirks &
+				    SDHCI_QUIRK_DONT_SHIFT_RESPONSE)
+					slot->curcmd->resp[3 - i] = val;
+				else {
+					slot->curcmd->resp[3 - i] =
+					    (val << 8) | extra;
+					extra = val >> 24;
+				}
+			}
+		} else
+			slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE);
+	}
+	/* If data ready - finish. */
+	if (slot->data_done)
+		sdhci_start(slot);
+}
+
+static void
+sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data)
+{
+	uint32_t target_timeout, current_timeout;
+	uint8_t div;
+
+	if (data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) {
+		slot->data_done = 1;
+		return;
+	}
+
+	slot->data_done = 0;
+
+	/* Calculate and set data timeout.*/
+	/* XXX: We should have this from mmc layer, now assume 1 sec. */
+	if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) {
+		div = 0xE;
+	} else {
+		target_timeout = 1000000;
+		div = 0;
+		current_timeout = (1 << 13) * 1000 / slot->timeout_clk;
+		while (current_timeout < target_timeout && div < 0xE) {
+			++div;
+			current_timeout <<= 1;
+		}
+		/* Compensate for an off-by-one error in the CaFe chip.*/
+		if (div < 0xE &&
+		    (slot->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL)) {
+			++div;
+		}
+	}
+	WR1(slot, SDHCI_TIMEOUT_CONTROL, div);
+
+	if (data == NULL)
+		return;
+
+	/* Use DMA if possible. */
+	if ((slot->opt & SDHCI_HAVE_DMA))
+		slot->flags |= SDHCI_USE_DMA;
+	/* If data is small, broken DMA may return zeroes instead of data, */
+	if ((slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) &&
+	    (data->len <= 512))
+		slot->flags &= ~SDHCI_USE_DMA;
+	/* Some controllers require even block sizes. */
+	if ((slot->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) &&
+	    ((data->len) & 0x3))
+		slot->flags &= ~SDHCI_USE_DMA;
+	/* Load DMA buffer. */
+	if (slot->flags & SDHCI_USE_DMA) {
+		if (data->flags & MMC_DATA_READ)
+			bus_dmamap_sync(slot->dmatag, slot->dmamap,
+			    BUS_DMASYNC_PREREAD);
+		else {
+			memcpy(slot->dmamem, data->data,
+			    (data->len < DMA_BLOCK_SIZE) ?
+			    data->len : DMA_BLOCK_SIZE);
+			bus_dmamap_sync(slot->dmatag, slot->dmamap,
+			    BUS_DMASYNC_PREWRITE);
+		}
+		WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr);
+		/* Interrupt aggregation: Mask border interrupt
+		 * for the last page and unmask else. */
+		if (data->len == DMA_BLOCK_SIZE)
+			slot->intmask &= ~SDHCI_INT_DMA_END;
+		else
+			slot->intmask |= SDHCI_INT_DMA_END;
+		WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
+	}
+	/* Current data offset for both PIO and DMA. */
+	slot->offset = 0;
+	/* Set block size and request IRQ on 4K border. */
+	WR2(slot, SDHCI_BLOCK_SIZE, SDHCI_MAKE_BLKSZ(DMA_BOUNDARY,
+	    (data->len < 512) ? data->len : 512));
+	/* Set block count. */
+	WR2(slot, SDHCI_BLOCK_COUNT, (data->len + 511) / 512);
+}
+
+void
+sdhci_finish_data(struct sdhci_slot *slot)
+{
+	struct mmc_data *data = slot->curcmd->data;
+	size_t left;
+
+	/* Interrupt aggregation: Restore command interrupt.
+	 * Auxiliary restore point for the case when data interrupt
+	 * happened first. */
+	if (!slot->cmd_done) {
+		WR4(slot, SDHCI_SIGNAL_ENABLE,
+		    slot->intmask |= SDHCI_INT_RESPONSE);
+	}
+	/* Unload rest of data from DMA buffer. */
+	if (!slot->data_done && (slot->flags & SDHCI_USE_DMA)) {
+		if (data->flags & MMC_DATA_READ) {
+			left = data->len - slot->offset;
+			bus_dmamap_sync(slot->dmatag, slot->dmamap,
+			    BUS_DMASYNC_POSTREAD);
+			memcpy((u_char*)data->data + slot->offset, slot->dmamem,
+			    (left < DMA_BLOCK_SIZE) ? left : DMA_BLOCK_SIZE);
+		} else
+			bus_dmamap_sync(slot->dmatag, slot->dmamap,
+			    BUS_DMASYNC_POSTWRITE);
+	}
+	slot->data_done = 1;
+	/* If there was error - reset the host. */
+	if (slot->curcmd->error) {
+		sdhci_reset(slot, SDHCI_RESET_CMD);
+		sdhci_reset(slot, SDHCI_RESET_DATA);
+		sdhci_start(slot);
+		return;
+	}
+	/* If we already have command response - finish. */
+	if (slot->cmd_done)
+		sdhci_start(slot);
+}
+
+static void
+sdhci_start(struct sdhci_slot *slot)
+{
+	struct mmc_request *req;
+
+	req = slot->req;
+	if (req == NULL)
+		return;
+
+	if (!(slot->flags & CMD_STARTED)) {
+		slot->flags |= CMD_STARTED;
+		sdhci_start_command(slot, req->cmd);
+		return;
+	}
+/* 	We don't need this until using Auto-CMD12 feature
+	if (!(slot->flags & STOP_STARTED) && req->stop) {
+		slot->flags |= STOP_STARTED;
+		sdhci_start_command(slot, req->stop);
+		return;
+	}
+*/
+	if (sdhci_debug > 1)
+		slot_printf(slot, "result: %d\n", req->cmd->error);
+	if (!req->cmd->error &&
+	    (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) {
+		sdhci_reset(slot, SDHCI_RESET_CMD);
+		sdhci_reset(slot, SDHCI_RESET_DATA);
+	}
+
+	sdhci_req_done(slot);
+}
+
+int
+sdhci_generic_request(device_t brdev __unused, device_t reqdev,
+    struct mmc_request *req)
+{
+	struct sdhci_slot *slot = device_get_ivars(reqdev);
+
+	SDHCI_LOCK(slot);
+	if (slot->req != NULL) {
+		SDHCI_UNLOCK(slot);
+		return (EBUSY);
+	}
+	if (sdhci_debug > 1) {
+		slot_printf(slot,
+		    "CMD%u arg %#x flags %#x dlen %u dflags %#x\n",
+		    req->cmd->opcode, req->cmd->arg, req->cmd->flags,
+		    (req->cmd->data)?(u_int)req->cmd->data->len:0,
+		    (req->cmd->data)?req->cmd->data->flags:0);
+	}
+	slot->req = req;
+	slot->flags = 0;
+	sdhci_start(slot);
+	SDHCI_UNLOCK(slot);
+	if (dumping) {
+		while (slot->req != NULL) {
+			sdhci_generic_intr(slot);
+			DELAY(10);
+		}
+	}
+	return (0);
+}
+
+int
+sdhci_generic_get_ro(device_t brdev __unused, device_t reqdev)
+{
+	struct sdhci_slot *slot = device_get_ivars(reqdev);
+	uint32_t val;
+
+	SDHCI_LOCK(slot);
+	val = RD4(slot, SDHCI_PRESENT_STATE);
+	SDHCI_UNLOCK(slot);
+	return (!(val & SDHCI_WRITE_PROTECT));
+}
+
+int
+sdhci_generic_acquire_host(device_t brdev __unused, device_t reqdev)
+{
+	struct sdhci_slot *slot = device_get_ivars(reqdev);
+	int err = 0;
+
+	SDHCI_LOCK(slot);
+	while (slot->bus_busy)
+		msleep(slot, &slot->mtx, 0, "sdhciah", 0);
+	slot->bus_busy++;
+	/* Activate led. */
+	WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED);
+	SDHCI_UNLOCK(slot);
+	return (err);
+}
+
+int
+sdhci_generic_release_host(device_t brdev __unused, device_t reqdev)
+{
+	struct sdhci_slot *slot = device_get_ivars(reqdev);
+
+	SDHCI_LOCK(slot);
+	/* Deactivate led. */
+	WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED);
+	slot->bus_busy--;
+	SDHCI_UNLOCK(slot);
+	wakeup(slot);
+	return (0);
+}
+
+static void
+sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask)
+{
+
+	if (!slot->curcmd) {
+		slot_printf(slot, "Got command interrupt 0x%08x, but "
+		    "there is no active command.\n", intmask);
+		sdhci_dumpregs(slot);
+		return;
+	}
+	if (intmask & SDHCI_INT_TIMEOUT)
+		slot->curcmd->error = MMC_ERR_TIMEOUT;
+	else if (intmask & SDHCI_INT_CRC)
+		slot->curcmd->error = MMC_ERR_BADCRC;
+	else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX))
+		slot->curcmd->error = MMC_ERR_FIFO;
+
+	sdhci_finish_command(slot);
+}
+
+static void
+sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask)
+{
+	struct mmc_data *data;
+	size_t left;
+
+	if (!slot->curcmd) {
+		slot_printf(slot, "Got data interrupt 0x%08x, but "
+		    "there is no active command.\n", intmask);
+		sdhci_dumpregs(slot);
+		return;
+	}
+	if (slot->curcmd->data == NULL &&
+	    (slot->curcmd->flags & MMC_RSP_BUSY) == 0) {
+		slot_printf(slot, "Got data interrupt 0x%08x, but "
+		    "there is no active data operation.\n",
+		    intmask);
+		sdhci_dumpregs(slot);
+		return;
+	}
+	if (intmask & SDHCI_INT_DATA_TIMEOUT)
+		slot->curcmd->error = MMC_ERR_TIMEOUT;
+	else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
+		slot->curcmd->error = MMC_ERR_BADCRC;
+	if (slot->curcmd->data == NULL &&
+	    (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
+	    SDHCI_INT_DMA_END))) {
+		slot_printf(slot, "Got data interrupt 0x%08x, but "
+		    "there is busy-only command.\n", intmask);
+		sdhci_dumpregs(slot);
+		slot->curcmd->error = MMC_ERR_INVALID;
+	}
+	if (slot->curcmd->error) {
+		/* No need to continue after any error. */
+		goto done;
+	}
+
+	/* Handle PIO interrupt. */
+	if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) {
+		if ((slot->opt & SDHCI_PLATFORM_TRANSFER) &&
+		    SDHCI_PLATFORM_WILL_HANDLE(slot->bus, slot)) {
+			SDHCI_PLATFORM_START_TRANSFER(slot->bus, slot,
+			    &intmask);
+			slot->flags |= PLATFORM_DATA_STARTED;
+		} else
+			sdhci_transfer_pio(slot);
+	}
+	/* Handle DMA border. */
+	if (intmask & SDHCI_INT_DMA_END) {
+		data = slot->curcmd->data;
+
+		/* Unload DMA buffer ... */
+		left = data->len - slot->offset;
+		if (data->flags & MMC_DATA_READ) {
+			bus_dmamap_sync(slot->dmatag, slot->dmamap,
+			    BUS_DMASYNC_POSTREAD);
+			memcpy((u_char*)data->data + slot->offset, slot->dmamem,
+			    (left < DMA_BLOCK_SIZE) ? left : DMA_BLOCK_SIZE);
+		} else {
+			bus_dmamap_sync(slot->dmatag, slot->dmamap,
+			    BUS_DMASYNC_POSTWRITE);
+		}
+		/* ... and reload it again. */
+		slot->offset += DMA_BLOCK_SIZE;
+		left = data->len - slot->offset;
+		if (data->flags & MMC_DATA_READ) {
+			bus_dmamap_sync(slot->dmatag, slot->dmamap,
+			    BUS_DMASYNC_PREREAD);
+		} else {
+			memcpy(slot->dmamem, (u_char*)data->data + slot->offset,
+			    (left < DMA_BLOCK_SIZE)? left : DMA_BLOCK_SIZE);
+			bus_dmamap_sync(slot->dmatag, slot->dmamap,
+			    BUS_DMASYNC_PREWRITE);
+		}
+		/* Interrupt aggregation: Mask border interrupt
+		 * for the last page. */
+		if (left == DMA_BLOCK_SIZE) {
+			slot->intmask &= ~SDHCI_INT_DMA_END;
+			WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
+		}
+		/* Restart DMA. */
+		WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr);
+	}
+	/* We have got all data. */
+	if (intmask & SDHCI_INT_DATA_END) {
+		if (slot->flags & PLATFORM_DATA_STARTED) {
+			slot->flags &= ~PLATFORM_DATA_STARTED;
+			SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot);
+		} else
+			sdhci_finish_data(slot);
+	}
+done:
+	if (slot->curcmd != NULL && slot->curcmd->error != 0) {
+		if (slot->flags & PLATFORM_DATA_STARTED) {
+			slot->flags &= ~PLATFORM_DATA_STARTED;
+			SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot);
+		} else
+			sdhci_finish_data(slot);
+	}
+}
+
+static void
+sdhci_acmd_irq(struct sdhci_slot *slot)
+{
+	uint16_t err;
+
+	err = RD4(slot, SDHCI_ACMD12_ERR);
+	if (!slot->curcmd) {
+		slot_printf(slot, "Got AutoCMD12 error 0x%04x, but "
+		    "there is no active command.\n", err);
+		sdhci_dumpregs(slot);
+		return;
+	}
+	slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", err);
+	sdhci_reset(slot, SDHCI_RESET_CMD);
+}
+
+void
+sdhci_generic_intr(struct sdhci_slot *slot)
+{
+	uint32_t intmask, present;
+
+	SDHCI_LOCK(slot);
+	/* Read slot interrupt status. */
+	intmask = RD4(slot, SDHCI_INT_STATUS);
+	if (intmask == 0 || intmask == 0xffffffff) {
+		SDHCI_UNLOCK(slot);
+		return;
+	}
+	if (sdhci_debug > 2)
+		slot_printf(slot, "Interrupt %#x\n", intmask);
+
+	/* Handle card presence interrupts. */
+	if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
+		present = (intmask & SDHCI_INT_CARD_INSERT) != 0;
+		slot->intmask &=
+		    ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
+		slot->intmask |= present ? SDHCI_INT_CARD_REMOVE :
+		    SDHCI_INT_CARD_INSERT;
+		WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
+		WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
+		WR4(slot, SDHCI_INT_STATUS, intmask &
+		    (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE));
+		sdhci_handle_card_present_locked(slot, present);
+		intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
+	}
+	/* Handle command interrupts. */
+	if (intmask & SDHCI_INT_CMD_MASK) {
+		WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK);
+		sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK);
+	}
+	/* Handle data interrupts. */
+	if (intmask & SDHCI_INT_DATA_MASK) {
+		WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK);
+		/* Don't call data_irq in case of errored command. */
+		if ((intmask & SDHCI_INT_CMD_ERROR_MASK) == 0)
+			sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK);
+	}
+	/* Handle AutoCMD12 error interrupt. */
+	if (intmask & SDHCI_INT_ACMD12ERR) {
+		WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR);
+		sdhci_acmd_irq(slot);
+	}
+	intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
+	intmask &= ~SDHCI_INT_ACMD12ERR;
+	intmask &= ~SDHCI_INT_ERROR;
+	/* Handle bus power interrupt. */
+	if (intmask & SDHCI_INT_BUS_POWER) {
+		WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER);
+		slot_printf(slot,
+		    "Card is consuming too much power!\n");
+		intmask &= ~SDHCI_INT_BUS_POWER;
+	}
+	/* The rest is unknown. */
+	if (intmask) {
+		WR4(slot, SDHCI_INT_STATUS, intmask);
+		slot_printf(slot, "Unexpected interrupt 0x%08x.\n",
+		    intmask);
+		sdhci_dumpregs(slot);
+	}
+
+	SDHCI_UNLOCK(slot);
+}
+
+int
+sdhci_generic_read_ivar(device_t bus, device_t child, int which,
+    uintptr_t *result)
+{
+	struct sdhci_slot *slot = device_get_ivars(child);
+
+	switch (which) {
+	default:
+		return (EINVAL);
+	case MMCBR_IVAR_BUS_MODE:
+		*result = slot->host.ios.bus_mode;
+		break;
+	case MMCBR_IVAR_BUS_WIDTH:
+		*result = slot->host.ios.bus_width;
+		break;
+	case MMCBR_IVAR_CHIP_SELECT:
+		*result = slot->host.ios.chip_select;
+		break;
+	case MMCBR_IVAR_CLOCK:
+		*result = slot->host.ios.clock;
+		break;
+	case MMCBR_IVAR_F_MIN:
+		*result = slot->host.f_min;
+		break;
+	case MMCBR_IVAR_F_MAX:
+		*result = slot->host.f_max;
+		break;
+	case MMCBR_IVAR_HOST_OCR:
+		*result = slot->host.host_ocr;
+		break;
+	case MMCBR_IVAR_MODE:
+		*result = slot->host.mode;
+		break;
+	case MMCBR_IVAR_OCR:
+		*result = slot->host.ocr;
+		break;
+	case MMCBR_IVAR_POWER_MODE:
+		*result = slot->host.ios.power_mode;
+		break;
+	case MMCBR_IVAR_VDD:
+		*result = slot->host.ios.vdd;
+		break;
+	case MMCBR_IVAR_VCCQ:
+		*result = slot->host.ios.vccq;
+		break;
+	case MMCBR_IVAR_CAPS:
+		*result = slot->host.caps;
+		break;
+	case MMCBR_IVAR_TIMING:
+		*result = slot->host.ios.timing;
+		break;
+	case MMCBR_IVAR_MAX_DATA:
+		*result = 65535;
+		break;
+	case MMCBR_IVAR_MAX_BUSY_TIMEOUT:
+		/*
+		 * Currently, sdhci_start_data() hardcodes 1 s for all CMDs.
+		 */
+		*result = 1000000;
+		break;
+	}
+	return (0);
+}
+
+int
+sdhci_generic_write_ivar(device_t bus, device_t child, int which,
+    uintptr_t value)
+{
+	struct sdhci_slot *slot = device_get_ivars(child);
+	uint32_t clock, max_clock;
+	int i;
+
+	switch (which) {
+	default:
+		return (EINVAL);
+	case MMCBR_IVAR_BUS_MODE:
+		slot->host.ios.bus_mode = value;
+		break;
+	case MMCBR_IVAR_BUS_WIDTH:
+		slot->host.ios.bus_width = value;
+		break;
+	case MMCBR_IVAR_CHIP_SELECT:
+		slot->host.ios.chip_select = value;
+		break;
+	case MMCBR_IVAR_CLOCK:
+		if (value > 0) {
+			max_clock = slot->max_clk;
+			clock = max_clock;
+
+			if (slot->version < SDHCI_SPEC_300) {
+				for (i = 0; i < SDHCI_200_MAX_DIVIDER;
+				    i <<= 1) {
+					if (clock <= value)
+						break;
+					clock >>= 1;
+				}
+			} else {
+				for (i = 0; i < SDHCI_300_MAX_DIVIDER;
+				    i += 2) {
+					if (clock <= value)
+						break;
+					clock = max_clock / (i + 2);
+				}
+			}
+
+			slot->host.ios.clock = clock;
+		} else
+			slot->host.ios.clock = 0;
+		break;
+	case MMCBR_IVAR_MODE:
+		slot->host.mode = value;
+		break;
+	case MMCBR_IVAR_OCR:
+		slot->host.ocr = value;
+		break;
+	case MMCBR_IVAR_POWER_MODE:
+		slot->host.ios.power_mode = value;
+		break;
+	case MMCBR_IVAR_VDD:
+		slot->host.ios.vdd = value;
+		break;
+	case MMCBR_IVAR_VCCQ:
+		slot->host.ios.vccq = value;
+		break;
+	case MMCBR_IVAR_TIMING:
+		slot->host.ios.timing = value;
+		break;
+	case MMCBR_IVAR_CAPS:
+	case MMCBR_IVAR_HOST_OCR:
+	case MMCBR_IVAR_F_MIN:
+	case MMCBR_IVAR_F_MAX:
+	case MMCBR_IVAR_MAX_DATA:
+		return (EINVAL);
+	}
+	return (0);
+}
+
+MODULE_VERSION(sdhci, 1);
diff --git a/freebsd/sys/dev/sdhci/sdhci.h b/freebsd/sys/dev/sdhci/sdhci.h
new file mode 100644
index 00000000..0b299150
--- /dev/null
+++ b/freebsd/sys/dev/sdhci/sdhci.h
@@ -0,0 +1,394 @@
+/*-
+ * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef	__SDHCI_H__
+#define	__SDHCI_H__
+
+#define	DMA_BLOCK_SIZE	4096
+#define	DMA_BOUNDARY	0	/* DMA reload every 4K */
+
+/* Controller doesn't honor resets unless we touch the clock register */
+#define	SDHCI_QUIRK_CLOCK_BEFORE_RESET			(1 << 0)
+/* Controller really supports DMA */
+#define	SDHCI_QUIRK_FORCE_DMA				(1 << 1)
+/* Controller has unusable DMA engine */
+#define	SDHCI_QUIRK_BROKEN_DMA				(1 << 2)
+/* Controller doesn't like to be reset when there is no card inserted. */
+#define	SDHCI_QUIRK_NO_CARD_NO_RESET			(1 << 3)
+/* Controller has flaky internal state so reset it on each ios change */
+#define	SDHCI_QUIRK_RESET_ON_IOS			(1 << 4)
+/* Controller can only DMA chunk sizes that are a multiple of 32 bits */
+#define	SDHCI_QUIRK_32BIT_DMA_SIZE			(1 << 5)
+/* Controller needs to be reset after each request to stay stable */
+#define	SDHCI_QUIRK_RESET_AFTER_REQUEST			(1 << 6)
+/* Controller has an off-by-one issue with timeout value */
+#define	SDHCI_QUIRK_INCR_TIMEOUT_CONTROL		(1 << 7)
+/* Controller has broken read timings */
+#define	SDHCI_QUIRK_BROKEN_TIMINGS			(1 << 8)
+/* Controller needs lowered frequency */
+#define	SDHCI_QUIRK_LOWER_FREQUENCY			(1 << 9)
+/* Data timeout is invalid, should use SD clock */
+#define	SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK		(1 << 10)
+/* Timeout value is invalid, should be overriden */
+#define	SDHCI_QUIRK_BROKEN_TIMEOUT_VAL			(1 << 11)
+/* SDHCI_CAPABILITIES is invalid */
+#define	SDHCI_QUIRK_MISSING_CAPS			(1 << 12)
+/* Hardware shifts the 136-bit response, don't do it in software. */
+#define	SDHCI_QUIRK_DONT_SHIFT_RESPONSE			(1 << 13)
+/* Wait to see reset bit asserted before waiting for de-asserted  */
+#define	SDHCI_QUIRK_WAITFOR_RESET_ASSERTED		(1 << 14)
+/* Leave controller in standard mode when putting card in HS mode. */
+#define	SDHCI_QUIRK_DONT_SET_HISPD_BIT			(1 << 15)
+/* Alternate clock source is required when supplying a 400 KHz clock. */
+#define	SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC		(1 << 16)
+/* Card insert/remove interrupts don't work, polling required. */
+#define	SDHCI_QUIRK_POLL_CARD_PRESENT			(1 << 17)
+/* All controller slots are non-removable. */
+#define	SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE		(1 << 18)
+/* Issue custom Intel controller reset sequence after power-up. */
+#define	SDHCI_QUIRK_INTEL_POWER_UP_RESET		(1 << 19)
+/* Data timeout is invalid, use 1 MHz clock instead. */
+#define	SDHCI_QUIRK_DATA_TIMEOUT_1MHZ			(1 << 20)
+/* Controller doesn't allow access boot partitions. */
+#define	SDHCI_QUIRK_BOOT_NOACC				(1 << 21)
+/* Controller waits for busy responses. */
+#define	SDHCI_QUIRK_WAIT_WHILE_BUSY			(1 << 22)
+/* Controller supports eMMC DDR52 mode. */
+#define	SDHCI_QUIRK_MMC_DDR52				(1 << 23)
+/* Controller support for UHS DDR50 mode is broken. */
+#define	SDHCI_QUIRK_BROKEN_UHS_DDR50			(1 << 24)
+/* Controller support for eMMC HS200 mode is broken. */
+#define	SDHCI_QUIRK_BROKEN_MMC_HS200			(1 << 25)
+/* Controller reports support for eMMC HS400 mode as SDHCI_CAN_MMC_HS400. */
+#define	SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400		(1 << 26)
+/* Controller support for SDHCI_CTRL2_PRESET_VALUE is broken. */
+#define	SDHCI_QUIRK_PRESET_VALUE_BROKEN			(1 << 27)
+
+/*
+ * Controller registers
+ */
+#define	SDHCI_DMA_ADDRESS	0x00
+
+#define	SDHCI_BLOCK_SIZE	0x04
+#define	 SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
+
+#define	SDHCI_BLOCK_COUNT	0x06
+
+#define	SDHCI_ARGUMENT		0x08
+
+#define	SDHCI_TRANSFER_MODE	0x0C
+#define	 SDHCI_TRNS_DMA		0x01
+#define	 SDHCI_TRNS_BLK_CNT_EN	0x02
+#define	 SDHCI_TRNS_ACMD12	0x04
+#define	 SDHCI_TRNS_READ	0x10
+#define	 SDHCI_TRNS_MULTI	0x20
+
+#define	SDHCI_COMMAND_FLAGS	0x0E
+#define	 SDHCI_CMD_RESP_NONE	0x00
+#define	 SDHCI_CMD_RESP_LONG	0x01
+#define	 SDHCI_CMD_RESP_SHORT	0x02
+#define	 SDHCI_CMD_RESP_SHORT_BUSY 0x03
+#define	 SDHCI_CMD_RESP_MASK	0x03
+#define	 SDHCI_CMD_CRC		0x08
+#define	 SDHCI_CMD_INDEX	0x10
+#define	 SDHCI_CMD_DATA		0x20
+#define	 SDHCI_CMD_TYPE_NORMAL	0x00
+#define	 SDHCI_CMD_TYPE_SUSPEND	0x40
+#define	 SDHCI_CMD_TYPE_RESUME	0x80
+#define	 SDHCI_CMD_TYPE_ABORT	0xc0
+#define	 SDHCI_CMD_TYPE_MASK	0xc0
+
+#define	SDHCI_COMMAND		0x0F
+
+#define	SDHCI_RESPONSE		0x10
+
+#define	SDHCI_BUFFER		0x20
+
+#define	SDHCI_PRESENT_STATE	0x24
+#define	 SDHCI_CMD_INHIBIT	0x00000001
+#define	 SDHCI_DAT_INHIBIT	0x00000002
+#define	 SDHCI_DAT_ACTIVE	0x00000004
+#define	 SDHCI_RETUNE_REQUEST	0x00000008
+#define	 SDHCI_DOING_WRITE	0x00000100
+#define	 SDHCI_DOING_READ	0x00000200
+#define	 SDHCI_SPACE_AVAILABLE	0x00000400
+#define	 SDHCI_DATA_AVAILABLE	0x00000800
+#define	 SDHCI_CARD_PRESENT	0x00010000
+#define	 SDHCI_CARD_STABLE	0x00020000
+#define	 SDHCI_CARD_PIN		0x00040000
+#define	 SDHCI_WRITE_PROTECT	0x00080000
+#define	 SDHCI_STATE_DAT_MASK	0x00f00000
+#define	 SDHCI_STATE_CMD	0x01000000
+
+#define	SDHCI_HOST_CONTROL	0x28
+#define	 SDHCI_CTRL_LED		0x01
+#define	 SDHCI_CTRL_4BITBUS	0x02
+#define	 SDHCI_CTRL_HISPD	0x04
+#define	 SDHCI_CTRL_SDMA	0x08
+#define	 SDHCI_CTRL_ADMA2	0x10
+#define	 SDHCI_CTRL_ADMA264	0x18
+#define	 SDHCI_CTRL_DMA_MASK	0x18
+#define	 SDHCI_CTRL_8BITBUS	0x20
+#define	 SDHCI_CTRL_CARD_DET	0x40
+#define	 SDHCI_CTRL_FORCE_CARD	0x80
+
+#define	SDHCI_POWER_CONTROL	0x29
+#define	 SDHCI_POWER_ON		0x01
+#define	 SDHCI_POWER_180	0x0A
+#define	 SDHCI_POWER_300	0x0C
+#define	 SDHCI_POWER_330	0x0E
+
+#define	SDHCI_BLOCK_GAP_CONTROL	0x2A
+
+#define	SDHCI_WAKE_UP_CONTROL	0x2B
+
+#define	SDHCI_CLOCK_CONTROL	0x2C
+#define	 SDHCI_DIVIDER_MASK	0xff
+#define	 SDHCI_DIVIDER_MASK_LEN	8
+#define	 SDHCI_DIVIDER_SHIFT	8
+#define	 SDHCI_DIVIDER_HI_MASK	3
+#define	 SDHCI_DIVIDER_HI_SHIFT	6
+#define	 SDHCI_CLOCK_CARD_EN	0x0004
+#define	 SDHCI_CLOCK_INT_STABLE	0x0002
+#define	 SDHCI_CLOCK_INT_EN	0x0001
+#define	 SDHCI_DIVIDERS_MASK	\
+    ((SDHCI_DIVIDER_MASK << SDHCI_DIVIDER_SHIFT) | \
+    (SDHCI_DIVIDER_HI_MASK << SDHCI_DIVIDER_HI_SHIFT))
+
+#define	SDHCI_TIMEOUT_CONTROL	0x2E
+
+#define	SDHCI_SOFTWARE_RESET	0x2F
+#define	 SDHCI_RESET_ALL	0x01
+#define	 SDHCI_RESET_CMD	0x02
+#define	 SDHCI_RESET_DATA	0x04
+
+#define	SDHCI_INT_STATUS	0x30
+#define	SDHCI_INT_ENABLE	0x34
+#define	SDHCI_SIGNAL_ENABLE	0x38
+#define	 SDHCI_INT_RESPONSE	0x00000001
+#define	 SDHCI_INT_DATA_END	0x00000002
+#define	 SDHCI_INT_BLOCK_GAP	0x00000004
+#define	 SDHCI_INT_DMA_END	0x00000008
+#define	 SDHCI_INT_SPACE_AVAIL	0x00000010
+#define	 SDHCI_INT_DATA_AVAIL	0x00000020
+#define	 SDHCI_INT_CARD_INSERT	0x00000040
+#define	 SDHCI_INT_CARD_REMOVE	0x00000080
+#define	 SDHCI_INT_CARD_INT	0x00000100
+#define	 SDHCI_INT_INT_A	0x00000200
+#define	 SDHCI_INT_INT_B	0x00000400
+#define	 SDHCI_INT_INT_C	0x00000800
+#define	 SDHCI_INT_RETUNE	0x00001000
+#define	 SDHCI_INT_ERROR	0x00008000
+#define	 SDHCI_INT_TIMEOUT	0x00010000
+#define	 SDHCI_INT_CRC		0x00020000
+#define	 SDHCI_INT_END_BIT	0x00040000
+#define	 SDHCI_INT_INDEX	0x00080000
+#define	 SDHCI_INT_DATA_TIMEOUT	0x00100000
+#define	 SDHCI_INT_DATA_CRC	0x00200000
+#define	 SDHCI_INT_DATA_END_BIT	0x00400000
+#define	 SDHCI_INT_BUS_POWER	0x00800000
+#define	 SDHCI_INT_ACMD12ERR	0x01000000
+#define	 SDHCI_INT_ADMAERR	0x02000000
+#define	 SDHCI_INT_TUNEERR	0x04000000
+
+#define	 SDHCI_INT_NORMAL_MASK	0x00007FFF
+#define	 SDHCI_INT_ERROR_MASK	0xFFFF8000
+
+#define	 SDHCI_INT_CMD_ERROR_MASK	(SDHCI_INT_TIMEOUT | \
+		SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
+
+#define	 SDHCI_INT_CMD_MASK	(SDHCI_INT_RESPONSE | SDHCI_INT_CMD_ERROR_MASK)
+
+#define	 SDHCI_INT_DATA_MASK	(SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
+		SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
+		SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
+		SDHCI_INT_DATA_END_BIT)
+
+#define	SDHCI_ACMD12_ERR	0x3C
+
+#define	SDHCI_HOST_CONTROL2	0x3E
+#define	 SDHCI_CTRL2_PRESET_VALUE	0x8000
+#define	 SDHCI_CTRL2_ASYNC_INTR	0x4000
+#define	 SDHCI_CTRL2_SAMPLING_CLOCK	0x0080
+#define	 SDHCI_CTRL2_EXEC_TUNING	0x0040
+#define	 SDHCI_CTRL2_DRIVER_TYPE_MASK	0x0030
+#define	 SDHCI_CTRL2_DRIVER_TYPE_B	0x0000
+#define	 SDHCI_CTRL2_DRIVER_TYPE_A	0x0010
+#define	 SDHCI_CTRL2_DRIVER_TYPE_C	0x0020
+#define	 SDHCI_CTRL2_DRIVER_TYPE_D	0x0030
+#define	 SDHCI_CTRL2_S18_ENABLE	0x0008
+#define	 SDHCI_CTRL2_UHS_MASK	0x0007
+#define	 SDHCI_CTRL2_UHS_SDR12	0x0000
+#define	 SDHCI_CTRL2_UHS_SDR25	0x0001
+#define	 SDHCI_CTRL2_UHS_SDR50	0x0002
+#define	 SDHCI_CTRL2_UHS_SDR104	0x0003
+#define	 SDHCI_CTRL2_UHS_DDR50	0x0004
+#define	 SDHCI_CTRL2_MMC_HS400	0x0005	/* non-standard */
+
+#define	SDHCI_CAPABILITIES	0x40
+#define	 SDHCI_TIMEOUT_CLK_MASK	0x0000003F
+#define	 SDHCI_TIMEOUT_CLK_SHIFT 0
+#define	 SDHCI_TIMEOUT_CLK_UNIT	0x00000080
+#define	 SDHCI_CLOCK_BASE_MASK	0x00003F00
+#define	 SDHCI_CLOCK_V3_BASE_MASK	0x0000FF00
+#define	 SDHCI_CLOCK_BASE_SHIFT	8
+#define	 SDHCI_MAX_BLOCK_MASK	0x00030000
+#define	 SDHCI_MAX_BLOCK_SHIFT  16
+#define	 SDHCI_CAN_DO_8BITBUS	0x00040000
+#define	 SDHCI_CAN_DO_ADMA2	0x00080000
+#define	 SDHCI_CAN_DO_HISPD	0x00200000
+#define	 SDHCI_CAN_DO_DMA	0x00400000
+#define	 SDHCI_CAN_DO_SUSPEND	0x00800000
+#define	 SDHCI_CAN_VDD_330	0x01000000
+#define	 SDHCI_CAN_VDD_300	0x02000000
+#define	 SDHCI_CAN_VDD_180	0x04000000
+#define	 SDHCI_CAN_DO_64BIT	0x10000000
+#define	 SDHCI_CAN_ASYNC_INTR	0x20000000
+#define	 SDHCI_SLOTTYPE_MASK	0xC0000000
+#define	 SDHCI_SLOTTYPE_REMOVABLE	0x00000000
+#define	 SDHCI_SLOTTYPE_EMBEDDED	0x40000000
+#define	 SDHCI_SLOTTYPE_SHARED	0x80000000
+
+#define	SDHCI_CAPABILITIES2	0x44
+#define	 SDHCI_CAN_SDR50	0x00000001
+#define	 SDHCI_CAN_SDR104	0x00000002
+#define	 SDHCI_CAN_DDR50	0x00000004
+#define	 SDHCI_CAN_DRIVE_TYPE_A	0x00000010
+#define	 SDHCI_CAN_DRIVE_TYPE_C	0x00000020
+#define	 SDHCI_CAN_DRIVE_TYPE_D	0x00000040
+#define	 SDHCI_RETUNE_CNT_MASK	0x00000F00
+#define	 SDHCI_RETUNE_CNT_SHIFT	8
+#define	 SDHCI_TUNE_SDR50	0x00002000
+#define	 SDHCI_RETUNE_MODES_MASK  0x0000C000
+#define	 SDHCI_RETUNE_MODES_SHIFT 14
+#define	 SDHCI_CLOCK_MULT_MASK	0x00FF0000
+#define	 SDHCI_CLOCK_MULT_SHIFT	16
+#define	 SDHCI_CAN_MMC_HS400	0x80000000	/* non-standard */
+
+#define	SDHCI_MAX_CURRENT	0x48
+#define	SDHCI_FORCE_AUTO_EVENT	0x50
+#define	SDHCI_FORCE_INTR_EVENT	0x52
+
+#define	SDHCI_ADMA_ERR		0x54
+#define	 SDHCI_ADMA_ERR_LENGTH	0x04
+#define	 SDHCI_ADMA_ERR_STATE_MASK	0x03
+#define	 SDHCI_ADMA_ERR_STATE_STOP	0x00
+#define	 SDHCI_ADMA_ERR_STATE_FDS	0x01
+#define	 SDHCI_ADMA_ERR_STATE_TFR	0x03
+
+#define	SDHCI_ADMA_ADDRESS_LO	0x58
+#define	SDHCI_ADMA_ADDRESS_HI	0x5C
+
+#define	SDHCI_PRESET_VALUE	0x60
+#define	SDHCI_SHARED_BUS_CTRL	0xE0
+
+#define	SDHCI_SLOT_INT_STATUS	0xFC
+
+#define	SDHCI_HOST_VERSION	0xFE
+#define	 SDHCI_VENDOR_VER_MASK	0xFF00
+#define	 SDHCI_VENDOR_VER_SHIFT	8
+#define	 SDHCI_SPEC_VER_MASK	0x00FF
+#define	 SDHCI_SPEC_VER_SHIFT	0
+#define	SDHCI_SPEC_100		0
+#define	SDHCI_SPEC_200		1
+#define	SDHCI_SPEC_300		2
+#define	SDHCI_SPEC_400		3
+
+SYSCTL_DECL(_hw_sdhci);
+
+extern u_int sdhci_quirk_clear;
+extern u_int sdhci_quirk_set;
+
+struct sdhci_slot {
+	u_int		quirks;		/* Chip specific quirks */
+	u_int		caps;		/* Override SDHCI_CAPABILITIES */
+	u_int		caps2;		/* Override SDHCI_CAPABILITIES2 */
+	device_t	bus;		/* Bus device */
+	device_t	dev;		/* Slot device */
+	u_char		num;		/* Slot number */
+	u_char		opt;		/* Slot options */
+#define	SDHCI_HAVE_DMA			0x01
+#define	SDHCI_PLATFORM_TRANSFER		0x02
+#define	SDHCI_NON_REMOVABLE		0x04
+	u_char		version;
+	int		timeout;	/* Transfer timeout */
+	uint32_t	max_clk;	/* Max possible freq */
+	uint32_t	timeout_clk;	/* Timeout freq */
+	bus_dma_tag_t	dmatag;
+	bus_dmamap_t	dmamap;
+	u_char		*dmamem;
+	bus_addr_t	paddr;		/* DMA buffer address */
+	struct task	card_task;	/* Card presence check task */
+	struct timeout_task
+			card_delayed_task;/* Card insert delayed task */
+	struct callout	card_poll_callout;/* Card present polling callout */
+	struct callout	timeout_callout;/* Card command/data response timeout */
+	struct mmc_host host;		/* Host parameters */
+	struct mmc_request *req;	/* Current request */
+	struct mmc_command *curcmd;	/* Current command of current request */
+
+	uint32_t	intmask;	/* Current interrupt mask */
+	uint32_t	clock;		/* Current clock freq. */
+	size_t		offset;		/* Data buffer offset */
+	uint8_t		hostctrl;	/* Current host control register */
+	u_char		power;		/* Current power */
+	u_char		bus_busy;	/* Bus busy status */
+	u_char		cmd_done;	/* CMD command part done flag */
+	u_char		data_done;	/* DAT command part done flag */
+	u_char		flags;		/* Request execution flags */
+#define	CMD_STARTED		1
+#define	STOP_STARTED		2
+#define	SDHCI_USE_DMA		4	/* Use DMA for this req. */
+#define	PLATFORM_DATA_STARTED	8	/* Data xfer is handled by platform */
+	struct mtx	mtx;		/* Slot mutex */
+};
+
+int sdhci_generic_read_ivar(device_t bus, device_t child, int which,
+    uintptr_t *result);
+int sdhci_generic_write_ivar(device_t bus, device_t child, int which,
+    uintptr_t value);
+int sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num);
+void sdhci_start_slot(struct sdhci_slot *slot);
+/* performs generic clean-up for platform transfers */
+void sdhci_finish_data(struct sdhci_slot *slot);
+int sdhci_cleanup_slot(struct sdhci_slot *slot);
+int sdhci_generic_suspend(struct sdhci_slot *slot);
+int sdhci_generic_resume(struct sdhci_slot *slot);
+int sdhci_generic_update_ios(device_t brdev, device_t reqdev);
+int sdhci_generic_switch_vccq(device_t brdev, device_t reqdev);
+int sdhci_generic_request(device_t brdev, device_t reqdev,
+    struct mmc_request *req);
+int sdhci_generic_get_ro(device_t brdev, device_t reqdev);
+int sdhci_generic_acquire_host(device_t brdev, device_t reqdev);
+int sdhci_generic_release_host(device_t brdev, device_t reqdev);
+void sdhci_generic_intr(struct sdhci_slot *slot);
+uint32_t sdhci_generic_min_freq(device_t brdev, struct sdhci_slot *slot);
+bool sdhci_generic_get_card_present(device_t brdev, struct sdhci_slot *slot);
+void sdhci_generic_set_uhs_timing(device_t brdev, struct sdhci_slot *slot);
+void sdhci_handle_card_present(struct sdhci_slot *slot, bool is_present);
+
+#endif	/* __SDHCI_H__ */
diff --git a/freebsd/sys/dev/sdhci/sdhci_fdt_gpio.c b/freebsd/sys/dev/sdhci/sdhci_fdt_gpio.c
new file mode 100644
index 00000000..2490d49b
--- /dev/null
+++ b/freebsd/sys/dev/sdhci/sdhci_fdt_gpio.c
@@ -0,0 +1,268 @@
+#include <machine/rtems-bsd-kernel-space.h>
+
+/*-
+ * Copyright (c) 2017 Ian Lepore <ian@freebsd.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Support routines usable by any SoC sdhci bridge driver that uses gpio pins
+ * for card detect and write protect, and uses FDT data to describe those pins.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/gpio.h>
+#include <sys/sysctl.h>
+#include <sys/systm.h>
+#include <sys/taskqueue.h>
+
+#include <dev/gpio/gpiobusvar.h>
+#include <dev/mmc/bridge.h>
+#include <dev/ofw/ofw_bus.h>
+#include <dev/ofw/ofw_bus_subr.h>
+#include <dev/sdhci/sdhci.h>
+#include <dev/sdhci/sdhci_fdt_gpio.h>
+
+struct sdhci_fdt_gpio {
+	device_t		dev;
+	struct sdhci_slot *	slot;
+	gpio_pin_t		wp_pin;
+	gpio_pin_t		cd_pin;
+	void *			cd_ihandler;
+	struct resource *	cd_ires;
+	int			cd_irid;
+	bool			wp_disabled;
+	bool			wp_inverted;
+	bool			cd_disabled;
+	bool			cd_inverted;
+};
+
+/*
+ * Card detect interrupt handler.
+ */
+static void
+cd_intr(void *arg)
+{
+	struct sdhci_fdt_gpio *gpio = arg;
+
+	sdhci_handle_card_present(gpio->slot, sdhci_fdt_gpio_get_present(gpio));
+}
+
+/*
+ * Card detect setup.
+ */
+static void
+cd_setup(struct sdhci_fdt_gpio *gpio, phandle_t node)
+{
+	int pincaps;
+	device_t dev;
+	const char *cd_mode_str;
+
+	dev = gpio->dev;
+
+	/*
+	 * If the device is flagged as non-removable, set that slot option, and
+	 * set a flag to make sdhci_fdt_gpio_get_present() always return true.
+	 */
+	if (OF_hasprop(node, "non-removable")) {
+		gpio->slot->opt |= SDHCI_NON_REMOVABLE;
+		gpio->cd_disabled = true;
+		if (bootverbose)
+			device_printf(dev, "Non-removable media\n");
+		return;
+	}
+
+	/*
+	 * If there is no cd-gpios property, then presumably the hardware
+	 * PRESENT_STATE register and interrupts will reflect card state
+	 * properly, and there's nothing more for us to do.  Our get_present()
+	 * will return sdhci_generic_get_card_present() because cd_pin is NULL.
+	 *
+	 * If there is a property, make sure we can read the pin.
+	 */
+	if (gpio_pin_get_by_ofw_property(dev, node, "cd-gpios", &gpio->cd_pin))
+		return;
+
+	if (gpio_pin_getcaps(gpio->cd_pin, &pincaps) != 0 ||
+	    !(pincaps & GPIO_PIN_INPUT)) {
+		device_printf(dev, "Cannot read card-detect gpio pin; "
+		    "setting card-always-present flag.\n");
+		gpio->cd_disabled = true;
+		return;
+	}
+
+	if (OF_hasprop(node, "cd-inverted"))
+		gpio->cd_inverted = true;
+
+	/*
+	 * If the pin can trigger an interrupt on both rising and falling edges,
+	 * we can use it to detect card presence changes.  If not, we'll request
+	 * card presence polling instead of using interrupts.
+	 */
+	if (!(pincaps & GPIO_INTR_EDGE_BOTH)) {
+		if (bootverbose)
+			device_printf(dev, "Cannot configure "
+			    "GPIO_INTR_EDGE_BOTH for card detect\n");
+		goto without_interrupts;
+	}
+
+	/*
+	 * Create an interrupt resource from the pin and set up the interrupt.
+	 */
+	if ((gpio->cd_ires = gpio_alloc_intr_resource(dev, &gpio->cd_irid,
+	    RF_ACTIVE, gpio->cd_pin, GPIO_INTR_EDGE_BOTH)) == NULL) {
+		if (bootverbose)
+			device_printf(dev, "Cannot allocate an IRQ for card "
+			    "detect GPIO\n");
+		goto without_interrupts;
+	}
+
+	if (bus_setup_intr(dev, gpio->cd_ires, INTR_TYPE_BIO | INTR_MPSAFE,
+	    NULL, cd_intr, gpio, &gpio->cd_ihandler) != 0) {
+		device_printf(dev, "Unable to setup card-detect irq handler\n");
+		gpio->cd_ihandler = NULL;
+		goto without_interrupts;
+	}
+
+without_interrupts:
+
+	/*
+	 * If we have a readable gpio pin, but didn't successfully configure
+	 * gpio interrupts, ask the sdhci driver to poll from a callout.
+	 */
+	if (gpio->cd_ihandler == NULL) {
+		cd_mode_str = "polling";
+		gpio->slot->quirks |= SDHCI_QUIRK_POLL_CARD_PRESENT;
+	} else {
+		cd_mode_str = "interrupts";
+	}
+
+	if (bootverbose) {
+		device_printf(dev, "Card presence detect on %s pin %u, "
+		    "configured for %s.\n",
+		    device_get_nameunit(gpio->cd_pin->dev), gpio->cd_pin->pin,
+		    cd_mode_str);
+	}
+}
+
+/*
+ * Write protect setup.
+ */
+static void
+wp_setup(struct sdhci_fdt_gpio *gpio, phandle_t node)
+{
+	device_t dev;
+
+	dev = gpio->dev;
+
+	if (OF_hasprop(node, "wp-disable")) {
+		gpio->wp_disabled = true;
+		if (bootverbose)
+			device_printf(dev, "Write protect disabled\n");
+		return;
+	}
+
+	if (gpio_pin_get_by_ofw_property(dev, node, "wp-gpios", &gpio->wp_pin))
+		return;
+
+	if (OF_hasprop(node, "wp-inverted"))
+		gpio->wp_inverted = true;
+
+	if (bootverbose)
+		device_printf(dev, "Write protect switch on %s pin %u\n",
+		    device_get_nameunit(gpio->wp_pin->dev), gpio->wp_pin->pin);
+}
+
+struct sdhci_fdt_gpio *
+sdhci_fdt_gpio_setup(device_t dev, struct sdhci_slot *slot)
+{
+	phandle_t node;
+	struct sdhci_fdt_gpio *gpio;
+
+	gpio = malloc(sizeof(*gpio), M_DEVBUF, M_ZERO | M_WAITOK);
+	gpio->dev  = dev;
+	gpio->slot = slot;
+
+	node = ofw_bus_get_node(dev);
+
+	wp_setup(gpio, node);
+	cd_setup(gpio, node);
+
+	return (gpio);
+}
+
+void
+sdhci_fdt_gpio_teardown(struct sdhci_fdt_gpio *gpio)
+{
+
+	if (gpio == NULL)
+		return;
+
+	if (gpio->cd_ihandler != NULL)
+		bus_teardown_intr(gpio->dev, gpio->cd_ires, gpio->cd_ihandler);
+	if (gpio->wp_pin != NULL)
+		gpio_pin_release(gpio->wp_pin);
+	if (gpio->cd_pin != NULL)
+		gpio_pin_release(gpio->cd_pin);
+	if (gpio->cd_ires != NULL)
+		bus_release_resource(gpio->dev, SYS_RES_IRQ, 0, gpio->cd_ires);
+
+	free(gpio, M_DEVBUF);
+}
+
+bool
+sdhci_fdt_gpio_get_present(struct sdhci_fdt_gpio *gpio)
+{
+	bool pinstate;
+
+	if (gpio->cd_disabled)
+		return (true);
+
+	if (gpio->cd_pin == NULL)
+		return (sdhci_generic_get_card_present(gpio->slot->bus,
+		    gpio->slot));
+
+	gpio_pin_is_active(gpio->cd_pin, &pinstate);
+
+	return (pinstate ^ gpio->cd_inverted);
+}
+
+int
+sdhci_fdt_gpio_get_readonly(struct sdhci_fdt_gpio *gpio)
+{
+	bool pinstate;
+
+	if (gpio->wp_disabled)
+		return (false);
+
+	if (gpio->wp_pin == NULL)
+		return (sdhci_generic_get_ro(gpio->slot->bus, gpio->slot->dev));
+
+	gpio_pin_is_active(gpio->wp_pin, &pinstate);
+
+	return (pinstate ^ gpio->wp_inverted);
+}
diff --git a/freebsd/sys/dev/sdhci/sdhci_fdt_gpio.h b/freebsd/sys/dev/sdhci/sdhci_fdt_gpio.h
new file mode 100644
index 00000000..6d51737b
--- /dev/null
+++ b/freebsd/sys/dev/sdhci/sdhci_fdt_gpio.h
@@ -0,0 +1,69 @@
+/*-
+ * Copyright (c) 2017 Ian Lepore <ian@freebsd.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+/*
+ * Support routines usable by any SoC sdhci bridge driver that uses gpio pins
+ * for card detect and/or write protect, and uses FDT data to describe those
+ * pins.  A bridge driver need only supply a couple 2-line forwarding functions
+ * to connect the get_present and get_readonly accessors to the corresponding
+ * driver interface functions, and add setup/teardown calls to its attach and
+ * detach functions.
+ */
+
+#ifndef	_SDHCI_FDT_GPIO_H_
+#define	_SDHCI_FDT_GPIO_H_
+
+struct sdhci_slot;
+struct sdhci_fdt_gpio;
+
+/*
+ * sdhci_fdt_gpio_setup()
+ * sdhci_fdt_gpio_teardown()
+ *
+ * Process FDT properties that use gpio pins and set up interrupt handling (if
+ * supported by hardware) and accessor functions to read the pins.
+ *
+ * Setup cannot fail.  If the properties are not present, the accessors will
+ * return the values from standard sdhci registers.  If the gpio controller
+ * can't trigger interrupts on both edges, it configures the slot to use polling
+ * for card presence detection.  If it can't access the gpio pin at all it sets
+ * up the get_present() accessor to always return true.  Likewise the
+ * get_readonly() accessor always returns false if its pin can't be accessed.
+ */
+struct sdhci_fdt_gpio *sdhci_fdt_gpio_setup(device_t dev, struct sdhci_slot *slot);
+void sdhci_fdt_gpio_teardown(struct sdhci_fdt_gpio *gpio);
+
+/*
+ * sdhci_fdt_gpio_get_present()
+ * sdhci_fdt_gpio_get_readonly()
+ *
+ * Gpio pin state accessor functions.
+ */
+bool sdhci_fdt_gpio_get_present(struct sdhci_fdt_gpio *gpio);
+int  sdhci_fdt_gpio_get_readonly(struct sdhci_fdt_gpio *gpio);
+
+#endif