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authorPeng Fan <van.freenix@gmail.com>2013-09-05 10:14:42 +0800
committerPeng Fan <van.freenix@gmail.com>2013-09-05 13:47:39 +0800
commit2053ce659489720a98ef33ced6b2e63721cbc3f4 (patch)
treec55bdf87469307f1e5bae23680236c91402f9e42 /testcase
parent0b41f6ca89bb130b66f1acc0caffda9100f53f0f (diff)
M32r support
Signed-off-by: Peng Fan <van.freenix@gmail.com>
Diffstat (limited to 'testcase')
-rw-r--r--testcase/1.c29
-rw-r--r--testcase/Readme8
-rw-r--r--testcase/wscript13
3 files changed, 50 insertions, 0 deletions
diff --git a/testcase/1.c b/testcase/1.c
index 18e643b..58903bc 100644
--- a/testcase/1.c
+++ b/testcase/1.c
@@ -42,6 +42,10 @@ void hello(int arg)
printf("Just test 'beq hello, PCREL10', so just halt here\n");
while(1);
break;
+#elif defined (__m32r__)
+ case 18:
+ printf("beq r0, r4, hello, 18_PCREL_RELA pass\n");
+ break;
#else
#endif
@@ -277,6 +281,31 @@ int rtems(int argc, char **argv)
"cmp $r0, $r1\n\t"
"beq hello\n\t");
+#elif defined (__m32r__)
+#if 1
+ __asm__ volatile (
+ "push r0\n\t"
+ "push r4\n\t"
+ "push r14\n\t"
+ "ld24 r14, 2f\n\t"
+ "ldi r0, #18\n\t"
+ "ldi r4, #18\n\t"
+ "beq r0, r4, hello\n\t"
+ "1:\n\t"
+ ".word global\n\t"
+ "2:\n\t"
+ "ld24 r0, 1b\n\t"
+ "ld r4, @r0\n\t"
+ "ldi r0, #22\n\t"
+ "st r0, @r4\n\t"
+ "pop r14\n\t"
+ "pop r4\n\t"
+ "pop r0\n\t"
+ );
+ if (global == 22)
+ printf("R_M32R_32_RELA, .word global pass\n");
+
+#endif
#else
/* other archs */
#endif
diff --git a/testcase/Readme b/testcase/Readme
index 364b163..5735dc2 100644
--- a/testcase/Readme
+++ b/testcase/Readme
@@ -51,3 +51,11 @@ v850:
Simulator:
v850sim-gdb build/v850-rtems4.11-v850sim/rtld
+
+m32r:
+ One can choose different cflags in wscript for m32r to see what happens.
+
+ configure --rtems=/opt/rtems-4.11 --rtems-tools=/opt/rtems-4.11 --rtems-archs=m32r
+
+ Simulator:
+ m32rsim-gdb build/m32r-rtems4.11-m32rsim/rtld
diff --git a/testcase/wscript b/testcase/wscript
index f38c124..cad0613 100644
--- a/testcase/wscript
+++ b/testcase/wscript
@@ -108,6 +108,19 @@ def build(bld):
'--entry', '_my_main'],
source = ['1.c', '2.c'])
+ elif arch == 'm32r':
+# cflags = '-fno-common, -mmodel=large',
+# cflags = '-fno-common -mmodel=medium',
+ bld(target = 'test.rap',
+ features = 'c rap',
+ xxxx = 'hello',
+
+ cflags = '-fno-common',
+
+ rtems_linkflags = ['--base', 'rtld.prelink',
+ '--entry', 'my_main'],
+ source = ['1.c', '2.c'])
+
bld(target = '../test.rap',
source = ['test.rap'],
rule = 'cp ${SRC} ${TGT}')