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author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2017-11-20 07:45:15 +0100 |
---|---|---|
committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2017-11-20 07:53:09 +0100 |
commit | 5018894ee176d1b05daf156a8b858b3db0d457f4 (patch) | |
tree | 015c2090e55ed21b0c0e49251fb8f1033e685619 | |
parent | 3d374d90f8f2814a7ae6549d4c0fb83d4cc75511 (diff) |
bsps/powerpc: Fix PPC_EXC_CONFIG_USE_FIXED_HANDLER
For the SPE support we must store the upper half of r3 as well.
Update #3085.
4 files changed, 17 insertions, 12 deletions
diff --git a/c/src/lib/libbsp/powerpc/qoriq/start/start.S b/c/src/lib/libbsp/powerpc/qoriq/start/start.S index 2d275e3c2b..02505a6262 100644 --- a/c/src/lib/libbsp/powerpc/qoriq/start/start.S +++ b/c/src/lib/libbsp/powerpc/qoriq/start/start.S @@ -379,7 +379,7 @@ bsp_exc_vector_base: START_NOP_FOR_LINKER_TOC_POINTER_RESTORE /* External input */ PPC_REG_STORE_UPDATE r1, -PPC_EXC_INTERRUPT_FRAME_SIZE(r1) - PPC_REG_STORE r3, GPR3_OFFSET(r1) + PPC_REG_STORE r3, PPC_EXC_GPR3_PROLOGUE_OFFSET(r1) li r3, 4 b ppc_exc_interrupt START_NOP_FOR_LINKER_TOC_POINTER_RESTORE @@ -420,14 +420,13 @@ bsp_exc_vector_base: /* Decrementer */ #ifdef QORIQ_IS_HYPERVISOR_GUEST PPC_REG_STORE_UPDATE r1, -PPC_EXC_INTERRUPT_FRAME_SIZE(r1) + PPC_REG_STORE r3, PPC_EXC_GPR3_PROLOGUE_OFFSET(r1) + li r3, 10 + b ppc_exc_interrupt #else PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1) -#endif PPC_REG_STORE r3, GPR3_OFFSET(r1) li r3, 10 -#ifdef QORIQ_IS_HYPERVISOR_GUEST - b ppc_exc_interrupt -#else b ppc_exc_fatal_normal #endif START_NOP_FOR_LINKER_TOC_POINTER_RESTORE @@ -491,14 +490,13 @@ bsp_exc_vector_base: /* Processor doorbell interrupt */ #if defined(QORIQ_IS_HYPERVISOR_GUEST) && defined(RTEMS_SMP) PPC_REG_STORE_UPDATE r1, -PPC_EXC_INTERRUPT_FRAME_SIZE(r1) + PPC_REG_STORE r3, PPC_EXC_GPR3_PROLOGUE_OFFSET(r1) + li r3, 36 + b ppc_exc_interrupt #else PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1) -#endif PPC_REG_STORE r3, GPR3_OFFSET(r1) li r3, 36 -#if defined(QORIQ_IS_HYPERVISOR_GUEST) && defined(RTEMS_SMP) - b ppc_exc_interrupt -#else b ppc_exc_fatal_normal #endif START_NOP_FOR_LINKER_TOC_POINTER_RESTORE diff --git a/c/src/lib/libbsp/powerpc/t32mppc/start/start.S b/c/src/lib/libbsp/powerpc/t32mppc/start/start.S index 6e4df3cf44..7c32343f3d 100644 --- a/c/src/lib/libbsp/powerpc/t32mppc/start/start.S +++ b/c/src/lib/libbsp/powerpc/t32mppc/start/start.S @@ -147,7 +147,7 @@ bsp_exc_vector_base: b ppc_exc_fatal_normal /* Decrementer */ PPC_REG_STORE_UPDATE r1, -PPC_EXC_INTERRUPT_FRAME_SIZE(r1) - PPC_REG_STORE r3, GPR3_OFFSET(r1) + PPC_REG_STORE r3, PPC_EXC_GPR3_PROLOGUE_OFFSET(r1) li r3, 10 b ppc_exc_interrupt /* Fixed-interval timer interrupt */ diff --git a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_async_normal.S b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_async_normal.S index 32b867b735..4b318e5e16 100644 --- a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_async_normal.S +++ b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_async_normal.S @@ -88,6 +88,13 @@ ppc_exc_interrupt: oris FRAME_REGISTER, FRAME_REGISTER, MSR_SPE >> 16 mtmsr FRAME_REGISTER isync + + /* + * Save high order part of SCRATCH_1_REGISTER here. The low order part + * was saved in the minimal prologue. + */ + evmergehi SCRATCH_1_REGISTER, SCRATCH_1_REGISTER, FRAME_REGISTER + PPC_REG_STORE FRAME_REGISTER, GPR3_OFFSET(r1) #endif #if defined(PPC_MULTILIB_FPU) || defined(PPC_MULTILIB_ALTIVEC) diff --git a/cpukit/score/cpu/powerpc/rtems/score/cpuimpl.h b/cpukit/score/cpu/powerpc/rtems/score/cpuimpl.h index c292feb6fd..792a8111ad 100644 --- a/cpukit/score/cpu/powerpc/rtems/score/cpuimpl.h +++ b/cpukit/score/cpu/powerpc/rtems/score/cpuimpl.h @@ -42,7 +42,7 @@ #ifndef __SPE__ #define PPC_EXC_GPR_OFFSET(gpr) \ ((gpr) * PPC_GPR_SIZE + PPC_EXC_INTERRUPT_FRAME_OFFSET + PPC_REG_SIZE) - #define PPC_EXC_VECTOR_PROLOGUE_OFFSET PPC_EXC_GPR_OFFSET(4) + #define PPC_EXC_GPR3_PROLOGUE_OFFSET PPC_EXC_GPR_OFFSET(3) #if defined(PPC_MULTILIB_ALTIVEC) && defined(PPC_MULTILIB_FPU) #define PPC_EXC_VRSAVE_OFFSET PPC_EXC_GPR_OFFSET(33) #define PPC_EXC_VSCR_OFFSET (PPC_EXC_VRSAVE_OFFSET + 28) @@ -82,7 +82,7 @@ #define PPC_EXC_SPEFSCR_OFFSET 44 #define PPC_EXC_ACC_OFFSET 48 #define PPC_EXC_GPR_OFFSET(gpr) ((gpr) * PPC_GPR_SIZE + 56) - #define PPC_EXC_VECTOR_PROLOGUE_OFFSET (PPC_EXC_GPR_OFFSET(4) + 4) + #define PPC_EXC_GPR3_PROLOGUE_OFFSET (PPC_EXC_GPR_OFFSET(3) + 4) #define CPU_INTERRUPT_FRAME_SIZE (160 + PPC_STACK_RED_ZONE_SIZE) #define PPC_EXC_FRAME_SIZE 320 #endif |