4 files changed, 698 insertions, 0 deletions
diff --git a/include/arm/stm32f105rc/bsp/i2c.h b/include/arm/stm32f105rc/bsp/i2c.h
new file mode 100644
index 0000000000..fa18b1f92f
--- /dev/null
+++ b/include/arm/stm32f105rc/bsp/i2c.h
@@ -0,0 +1,96 @@
+/**
+ * @file
+ * @ingroup stm32f4_i2c I2C Support
+ * @brief I2C-module.
+ */
+
+/*
+ * Copyright (c) 2013 Christian Mauderer.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Obere Lagerstr. 30
+ *  82178 Puchheim
+ *  Germany
+ *  <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+/* The I2C-module can not run with libi2c. The reason for this is, that libi2c
+ * needs a possibility to generate a stop condition separately. This controller
+ * wants to generate the condition automatically when sending or receiving data.
+ */
+
+#ifndef LIBBSP_ARM_STM32F4_I2C_H
+#define LIBBSP_ARM_STM32F4_I2C_H
+
+#include <rtems.h>
+
+#include <bsp/io.h>
+#include <bsp/stm32f4.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/**
+ * @defgroup stm32f4_i2c I2C Support
+ * @ingroup arm_stm32f4
+ * @brief I2C Module
+ * @{
+ */
+
+typedef struct {
+  /**
+   * @brief The address of the slave without the read write bit.
+   * A 7-Bit address should be placed in the bits [6..0]
+   */
+  uint16_t addr;
+  /** @brief Read (true) or write (false) data */
+  bool read;
+  /** @brief Size of data to read or write */
+  size_t len;
+  /** @brief Buffer for data */
+  uint8_t *buf;
+} stm32f4_i2c_message;
+
+typedef struct {
+  volatile stm32f4_i2c *regs;
+  size_t index;
+  rtems_vector_number vector;
+  rtems_id mutex;
+  rtems_id task_id;
+  uint8_t *data;
+  uint8_t *last;
+  size_t len;
+  bool read;
+  uint8_t addr_with_rw;
+} stm32f4_i2c_bus_entry;
+
+/** @brief Initialise the i2c module. */
+rtems_status_code stm32f4_i2c_init(stm32f4_i2c_bus_entry *e);
+
+/** @brief Process a i2c message */
+rtems_status_code stm32f4_i2c_process_message(
+  stm32f4_i2c_bus_entry *e,
+  stm32f4_i2c_message *msg
+);
+
+/** @brief Set another baud rate than the default one */
+rtems_status_code stm32f4_i2c_set_bitrate(
+  stm32f4_i2c_bus_entry *e,
+  uint32_t br
+);
+
+extern stm32f4_i2c_bus_entry *const stm32f4_i2c1;
+extern stm32f4_i2c_bus_entry *const stm32f4_i2c2;
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_ARM_STM32F4_I2C_H */
diff --git a/include/arm/stm32f105rc/bsp/io.h b/include/arm/stm32f105rc/bsp/io.h
new file mode 100644
index 0000000000..b7f8669cba
--- /dev/null
+++ b/include/arm/stm32f105rc/bsp/io.h
@@ -0,0 +1,416 @@
+/**
+ * @file
+ * @ingroup stm32f4_io
+ * @brief IO support.
+ */
+
+/*
+ * Copyright (c) 2012 Sebastian Huber.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Obere Lagerstr. 30
+ *  82178 Puchheim
+ *  Germany
+ *  <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_STM32F4_IO_H
+#define LIBBSP_ARM_STM32F4_IO_H
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <bspopts.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/**
+ * @defgroup stm32f4_io IO Support
+ * @ingroup arm_stm32f4
+ * @brief IO Support
+ * @{
+ */
+
+#define STM32F4_GPIO_PIN(port, index) ((((port) << 4) | (index)) & 0xff)
+
+#define STM32F4_GPIO_PORT_OF_PIN(pin) (((pin) >> 4) & 0xf)
+
+#define STM32F4_GPIO_INDEX_OF_PIN(pin) ((pin) & 0xf)
+
+#ifdef STM32F4_FAMILY_F4XXXX
+
+/**
+ * @name Family F4XXXX
+ * @{
+ */
+
+typedef enum {
+  STM32F4_GPIO_MODE_INPUT,
+  STM32F4_GPIO_MODE_OUTPUT,
+  STM32F4_GPIO_MODE_AF,
+  STM32F4_GPIO_MODE_ANALOG
+} stm32f4_gpio_mode;
+
+typedef enum {
+  STM32F4_GPIO_OTYPE_PUSH_PULL,
+  STM32F4_GPIO_OTYPE_OPEN_DRAIN
+} stm32f4_gpio_otype;
+
+typedef enum {
+  STM32F4_GPIO_OSPEED_2_MHZ,
+  STM32F4_GPIO_OSPEED_25_MHZ,
+  STM32F4_GPIO_OSPEED_50_MHZ,
+  STM32F4_GPIO_OSPEED_100_MHZ
+} stm32f4_gpio_ospeed;
+
+typedef enum {
+  STM32F4_GPIO_NO_PULL,
+  STM32F4_GPIO_PULL_UP,
+  STM32F4_GPIO_PULL_DOWN
+} stm32f4_gpio_pull;
+
+typedef enum {
+  STM32F4_GPIO_AF_SYSTEM = 0,
+  STM32F4_GPIO_AF_TIM1 = 1,
+  STM32F4_GPIO_AF_TIM2 = 1,
+  STM32F4_GPIO_AF_TIM3 = 2,
+  STM32F4_GPIO_AF_TIM4 = 2,
+  STM32F4_GPIO_AF_TIM5 = 2,
+  STM32F4_GPIO_AF_TIM8 = 3,
+  STM32F4_GPIO_AF_TIM9 = 3,
+  STM32F4_GPIO_AF_TIM10 = 3,
+  STM32F4_GPIO_AF_TIM11 = 3,
+  STM32F4_GPIO_AF_I2C1 = 4,
+  STM32F4_GPIO_AF_I2C2 = 4,
+  STM32F4_GPIO_AF_I2C3 = 4,
+  STM32F4_GPIO_AF_SPI1 = 5,
+  STM32F4_GPIO_AF_SPI2 = 5,
+  STM32F4_GPIO_AF_SPI3 = 6,
+  STM32F4_GPIO_AF_USART1 = 7,
+  STM32F4_GPIO_AF_USART2 = 7,
+  STM32F4_GPIO_AF_USART3 = 7,
+  STM32F4_GPIO_AF_UART4 = 8,
+  STM32F4_GPIO_AF_UART5 = 8,
+  STM32F4_GPIO_AF_USART6 = 8,
+  STM32F4_GPIO_AF_CAN1 = 9,
+  STM32F4_GPIO_AF_CAN2 = 9,
+  STM32F4_GPIO_AF_TIM12 = 9,
+  STM32F4_GPIO_AF_TIM13 = 9,
+  STM32F4_GPIO_AF_TIM14 = 9,
+  STM32F4_GPIO_AF_OTG_FS = 10,
+  STM32F4_GPIO_AF_OTG_HS = 10,
+  STM32F4_GPIO_AF_ETH = 11,
+  STM32F4_GPIO_AF_FSMC = 12,
+  STM32F4_GPIO_AF_OTG_HS_FS = 12,
+  STM32F4_GPIO_AF_SDIO = 12,
+  STM32F4_GPIO_AF_DCMI = 13,
+  STM32F4_GPIO_AF_EVENTOUT = 15
+} stm32f4_gpio_af;
+
+typedef union {
+  struct {
+    uint32_t pin_first : 8;
+    uint32_t pin_last : 8;
+    uint32_t mode : 2;
+    uint32_t otype : 1;
+    uint32_t ospeed : 2;
+    uint32_t pupd : 2;
+    uint32_t output : 1;
+    uint32_t af : 4;
+    uint32_t reserved : 4;
+  } fields;
+
+  uint32_t value;
+} stm32f4_gpio_config;
+
+#define STM32F4_GPIO_CONFIG_TERMINAL \
+  { { 0xff, 0xff, 0x3, 0x1, 0x3, 0x3, 0x1, 0xf, 0xf } }
+
+/** @} */
+
+#endif /* STM32F4_FAMILY_F4XXXX */
+#ifdef STM32F4_FAMILY_F10XXX
+
+/**
+ * @name Family F10XXX
+ * @{
+ */
+
+typedef enum {
+  STM32F4_GPIO_MODE_INPUT,
+  STM32F4_GPIO_MODE_OUTPUT_10MHz,
+  STM32F4_GPIO_MODE_OUTPUT_2MHz,
+  STM32F4_GPIO_MODE_OUTPUT_50MHz
+} stm32f4_gpio_mode;
+
+typedef enum {
+  STM32F4_GPIO_CNF_IN_ANALOG = 0,
+  STM32F4_GPIO_CNF_IN_FLOATING = 1,
+  STM32F4_GPIO_CNF_IN_PULL_UPDOWN = 2,
+
+  STM32F4_GPIO_CNF_OUT_GPIO_PP = 0,
+  STM32F4_GPIO_CNF_OUT_GPIO_OD = 1,
+  STM32F4_GPIO_CNF_OUT_AF_PP = 2,
+  STM32F4_GPIO_CNF_OUT_AF_OD = 3,
+} stm32f4_gpio_cnf;
+
+typedef enum {
+  STM32F4_GPIO_REMAP_DONT_CHANGE,
+  STM32F4_GPIO_REMAP_SPI1_0,
+  STM32F4_GPIO_REMAP_SPI1_1,
+  STM32F4_GPIO_REMAP_I2C1_0,
+  STM32F4_GPIO_REMAP_I2C1_1,
+  STM32F4_GPIO_REMAP_USART1_0,
+  STM32F4_GPIO_REMAP_USART1_1,
+  STM32F4_GPIO_REMAP_USART2_0,
+  STM32F4_GPIO_REMAP_USART2_1,
+  STM32F4_GPIO_REMAP_USART3_0,
+  STM32F4_GPIO_REMAP_USART3_1,
+  STM32F4_GPIO_REMAP_USART3_3,
+  STM32F4_GPIO_REMAP_TIM1_0,
+  STM32F4_GPIO_REMAP_TIM1_1,
+  STM32F4_GPIO_REMAP_TIM1_3,
+  STM32F4_GPIO_REMAP_TIM2_0,
+  STM32F4_GPIO_REMAP_TIM2_1,
+  STM32F4_GPIO_REMAP_TIM2_2,
+  STM32F4_GPIO_REMAP_TIM2_3,
+  STM32F4_GPIO_REMAP_TIM3_0,
+  STM32F4_GPIO_REMAP_TIM3_2,
+  STM32F4_GPIO_REMAP_TIM3_3,
+  STM32F4_GPIO_REMAP_TIM4_0,
+  STM32F4_GPIO_REMAP_TIM4_1,
+  STM32F4_GPIO_REMAP_CAN1_0,
+  STM32F4_GPIO_REMAP_CAN1_2,
+  STM32F4_GPIO_REMAP_CAN1_3,
+  STM32F4_GPIO_REMAP_PD01_0,
+  STM32F4_GPIO_REMAP_PD01_1,
+  STM32F4_GPIO_REMAP_TIM5CH4_0,
+  STM32F4_GPIO_REMAP_TIM5CH4_1,
+  STM32F4_GPIO_REMAP_ADC1_ETRGINJ_0,
+  STM32F4_GPIO_REMAP_ADC1_ETRGINJ_1,
+  STM32F4_GPIO_REMAP_ADC1_ETRGREG_0,
+  STM32F4_GPIO_REMAP_ADC1_ETRGREG_1,
+  STM32F4_GPIO_REMAP_ADC2_ETRGINJ_0,
+  STM32F4_GPIO_REMAP_ADC2_ETRGINJ_1,
+  STM32F4_GPIO_REMAP_ADC2_ETRGREG_0,
+  STM32F4_GPIO_REMAP_ADC2_ETRGREG_1,
+  STM32F4_GPIO_REMAP_ETH_0,
+  STM32F4_GPIO_REMAP_ETH_1,
+  STM32F4_GPIO_REMAP_CAN2_0,
+  STM32F4_GPIO_REMAP_CAN2_1,
+  STM32F4_GPIO_REMAP_MII_RMII_0,
+  STM32F4_GPIO_REMAP_MII_RMII_1,
+  STM32F4_GPIO_REMAP_SWJ_0,
+  STM32F4_GPIO_REMAP_SWJ_1,
+  STM32F4_GPIO_REMAP_SWJ_2,
+  STM32F4_GPIO_REMAP_SWJ_4,
+  STM32F4_GPIO_REMAP_SPI3_0,
+  STM32F4_GPIO_REMAP_SPI3_1,
+  STM32F4_GPIO_REMAP_TIM2ITR1_0,
+  STM32F4_GPIO_REMAP_TIM2ITR1_1,
+  STM32F4_GPIO_REMAP_PTP_PPS_0,
+  STM32F4_GPIO_REMAP_PTP_PPS_1,
+  STM32F4_GPIO_REMAP_TIM15_0,
+  STM32F4_GPIO_REMAP_TIM15_1,
+  STM32F4_GPIO_REMAP_TIM16_0,
+  STM32F4_GPIO_REMAP_TIM16_1,
+  STM32F4_GPIO_REMAP_TIM17_0,
+  STM32F4_GPIO_REMAP_TIM17_1,
+  STM32F4_GPIO_REMAP_CEC_0,
+  STM32F4_GPIO_REMAP_CEC_1,
+  STM32F4_GPIO_REMAP_TIM1_DMA_0,
+  STM32F4_GPIO_REMAP_TIM1_DMA_1,
+  STM32F4_GPIO_REMAP_TIM9_0,
+  STM32F4_GPIO_REMAP_TIM9_1,
+  STM32F4_GPIO_REMAP_TIM10_0,
+  STM32F4_GPIO_REMAP_TIM10_1,
+  STM32F4_GPIO_REMAP_TIM11_0,
+  STM32F4_GPIO_REMAP_TIM11_1,
+  STM32F4_GPIO_REMAP_TIM13_0,
+  STM32F4_GPIO_REMAP_TIM13_1,
+  STM32F4_GPIO_REMAP_TIM14_0,
+  STM32F4_GPIO_REMAP_TIM14_1,
+  STM32F4_GPIO_REMAP_FSMC_0,
+  STM32F4_GPIO_REMAP_FSMC_1,
+  STM32F4_GPIO_REMAP_TIM67_DAC_DMA_0,
+  STM32F4_GPIO_REMAP_TIM67_DAC_DMA_1,
+  STM32F4_GPIO_REMAP_TIM12_0,
+  STM32F4_GPIO_REMAP_TIM12_1,
+  STM32F4_GPIO_REMAP_MISC_0,
+  STM32F4_GPIO_REMAP_MISC_1,
+} stm32f4_gpio_remap;
+
+typedef union {
+  struct {
+    uint32_t pin_first : 8;
+    uint32_t pin_last : 8;
+    uint32_t mode : 2;
+    uint32_t cnf : 2;
+    uint32_t output : 1;
+    uint32_t remap : 8;
+    uint32_t reserved : 3;
+  } fields;
+
+  uint32_t value;
+} stm32f4_gpio_config;
+
+#define STM32F4_GPIO_CONFIG_TERMINAL \
+  { { 0xff, 0xff, 0x3, 0x3, 0x1, 0xff, 0x7 } }
+
+/** @} */
+
+#endif /* STM32F4_FAMILY_F10XXX */
+
+extern const stm32f4_gpio_config stm32f4_start_config_gpio [];
+
+void stm32f4_gpio_set_clock(int pin, bool set);
+
+void stm32f4_gpio_set_config(const stm32f4_gpio_config *config);
+
+/**
+ * @brief Sets the GPIO configuration of an array terminated by
+ * STM32F4_GPIO_CONFIG_TERMINAL.
+ */
+void stm32f4_gpio_set_config_array(const stm32f4_gpio_config *configs);
+
+void stm32f4_gpio_set_output(int pin, bool set);
+
+bool stm32f4_gpio_get_input(int pin);
+
+#ifdef STM32F4_FAMILY_F4XXXX
+
+/**
+ * @name Family F4XXXX
+ * @{
+ */
+
+#define STM32F4_PIN_USART(port, idx, altfunc) \
+  { \
+    { \
+      .pin_first = STM32F4_GPIO_PIN(port, idx), \
+      .pin_last = STM32F4_GPIO_PIN(port, idx), \
+      .mode = STM32F4_GPIO_MODE_AF, \
+      .otype = STM32F4_GPIO_OTYPE_PUSH_PULL, \
+      .ospeed = STM32F4_GPIO_OSPEED_2_MHZ, \
+      .pupd = STM32F4_GPIO_PULL_UP, \
+      .af = altfunc \
+    } \
+  }
+
+#define STM32F4_PIN_USART1_TX_PA9 STM32F4_PIN_USART(0, 9, STM32F4_GPIO_AF_USART1)
+#define STM32F4_PIN_USART1_TX_PB6 STM32F4_PIN_USART(1, 6, STM32F4_GPIO_AF_USART1)
+#define STM32F4_PIN_USART1_RX_PA10 STM32F4_PIN_USART(0, 10, STM32F4_GPIO_AF_USART1)
+#define STM32F4_PIN_USART1_RX_PB7 STM32F4_PIN_USART(1, 7, STM32F4_GPIO_AF_USART1)
+
+#define STM32F4_PIN_USART2_TX_PA2 STM32F4_PIN_USART(0, 2, STM32F4_GPIO_AF_USART2)
+#define STM32F4_PIN_USART2_TX_PD5 STM32F4_PIN_USART(3, 5, STM32F4_GPIO_AF_USART2)
+#define STM32F4_PIN_USART2_RX_PA3 STM32F4_PIN_USART(0, 3, STM32F4_GPIO_AF_USART2)
+#define STM32F4_PIN_USART2_RX_PD6 STM32F4_PIN_USART(3, 6, STM32F4_GPIO_AF_USART2)
+
+#define STM32F4_PIN_USART3_TX_PC10 STM32F4_PIN_USART(2, 10, STM32F4_GPIO_AF_USART3)
+#define STM32F4_PIN_USART3_TX_PD8 STM32F4_PIN_USART(3, 8, STM32F4_GPIO_AF_USART3)
+#define STM32F4_PIN_USART3_RX_PC11 STM32F4_PIN_USART(2, 11, STM32F4_GPIO_AF_USART3)
+#define STM32F4_PIN_USART3_RX_PD9 STM32F4_PIN_USART(3, 9, STM32F4_GPIO_AF_USART3)
+
+#define STM32F4_PIN_UART4_TX_PA0 STM32F4_PIN_USART(0, 0, STM32F4_GPIO_AF_UART4)
+#define STM32F4_PIN_UART4_TX_PC10 STM32F4_PIN_USART(2, 10, STM32F4_GPIO_AF_UART4)
+#define STM32F4_PIN_UART4_RX_PA1 STM32F4_PIN_USART(0, 1, STM32F4_GPIO_AF_UART4)
+#define STM32F4_PIN_UART4_RX_PC11 STM32F4_PIN_USART(2, 11, STM32F4_GPIO_AF_UART4)
+
+#define STM32F4_PIN_UART5_TX_PC12 STM32F4_PIN_USART(2, 12, STM32F4_GPIO_AF_UART5)
+#define STM32F4_PIN_UART5_RX_PD2 STM32F4_PIN_USART(3, 2, STM32F4_GPIO_AF_UART5)
+
+#define STM32F4_PIN_USART6_TX_PC6 STM32F4_PIN_USART(2, 6, STM32F4_GPIO_AF_USART6)
+#define STM32F4_PIN_USART6_RX_PC7 STM32F4_PIN_USART(2, 7, STM32F4_GPIO_AF_USART6)
+
+/** @} */
+
+#endif /* STM32F4_FAMILY_F4XXXX */
+#ifdef STM32F4_FAMILY_F10XXX
+
+/**
+ * @name Family F10XXX
+ * @{
+ */
+
+#define STM32F4_PIN_USART_TX(port, idx, remapvalue) \
+  { \
+    { \
+      .pin_first = STM32F4_GPIO_PIN(port, idx), \
+      .pin_last = STM32F4_GPIO_PIN(port, idx), \
+      .mode = STM32F4_GPIO_MODE_OUTPUT_2MHz, \
+      .cnf = STM32F4_GPIO_CNF_OUT_AF_PP, \
+      .output = 0, \
+      .remap = remapvalue \
+    } \
+  }
+
+#define STM32F4_PIN_USART_RX(port, idx, remapvalue) \
+  { \
+    { \
+      .pin_first = STM32F4_GPIO_PIN(port, idx), \
+      .pin_last = STM32F4_GPIO_PIN(port, idx), \
+      .mode = STM32F4_GPIO_MODE_INPUT, \
+      .cnf = STM32F4_GPIO_CNF_IN_FLOATING, \
+      .output = 0, \
+      .remap = remapvalue \
+    } \
+  }
+
+#define STM32F4_PIN_USART1_TX_MAP_0 STM32F4_PIN_USART_TX(0,  9, STM32F4_GPIO_REMAP_USART1_0)
+#define STM32F4_PIN_USART1_RX_MAP_0 STM32F4_PIN_USART_RX(0, 10, STM32F4_GPIO_REMAP_USART1_0)
+#define STM32F4_PIN_USART1_TX_MAP_1 STM32F4_PIN_USART_TX(1,  6, STM32F4_GPIO_REMAP_USART1_1)
+#define STM32F4_PIN_USART1_RX_MAP_1 STM32F4_PIN_USART_RX(1,  7, STM32F4_GPIO_REMAP_USART1_1)
+
+#define STM32F4_PIN_USART2_TX_MAP_0 STM32F4_PIN_USART_TX(0,  2, STM32F4_GPIO_REMAP_USART2_0)
+#define STM32F4_PIN_USART2_RX_MAP_0 STM32F4_PIN_USART_RX(0,  3, STM32F4_GPIO_REMAP_USART2_0)
+#define STM32F4_PIN_USART2_TX_MAP_1 STM32F4_PIN_USART_TX(3,  5, STM32F4_GPIO_REMAP_USART2_1)
+#define STM32F4_PIN_USART2_RX_MAP_1 STM32F4_PIN_USART_RX(3,  6, STM32F4_GPIO_REMAP_USART2_1)
+
+#define STM32F4_PIN_USART3_TX_MAP_0 STM32F4_PIN_USART_TX(1, 10, STM32F4_GPIO_REMAP_USART3_0)
+#define STM32F4_PIN_USART3_RX_MAP_0 STM32F4_PIN_USART_RX(1, 11, STM32F4_GPIO_REMAP_USART3_0)
+#define STM32F4_PIN_USART3_TX_MAP_1 STM32F4_PIN_USART_TX(2, 10, STM32F4_GPIO_REMAP_USART3_1)
+#define STM32F4_PIN_USART3_RX_MAP_1 STM32F4_PIN_USART_RX(2, 11, STM32F4_GPIO_REMAP_USART3_1)
+#define STM32F4_PIN_USART3_TX_MAP_3 STM32F4_PIN_USART_TX(3,  8, STM32F4_GPIO_REMAP_USART3_3)
+#define STM32F4_PIN_USART3_RX_MAP_3 STM32F4_PIN_USART_RX(3,  9, STM32F4_GPIO_REMAP_USART3_3)
+
+#define STM32F4_PIN_UART4_TX        STM32F4_PIN_USART_TX(2, 10, STM32F4_GPIO_REMAP_DONT_CHANGE)
+#define STM32F4_PIN_UART4_RX        STM32F4_PIN_USART_RX(2, 11, STM32F4_GPIO_REMAP_DONT_CHANGE)
+
+#define STM32F4_PIN_UART5_TX        STM32F4_PIN_USART_TX(2, 12, STM32F4_GPIO_REMAP_DONT_CHANGE)
+#define STM32F4_PIN_UART5_RX        STM32F4_PIN_USART_RX(3,  2, STM32F4_GPIO_REMAP_DONT_CHANGE)
+
+#define STM32F4_PIN_I2C(port, idx, remapvalue) \
+  { \
+    { \
+      .pin_first = STM32F4_GPIO_PIN(port, idx), \
+      .pin_last = STM32F4_GPIO_PIN(port, idx), \
+      .mode = STM32F4_GPIO_MODE_OUTPUT_2MHz, \
+      .cnf = STM32F4_GPIO_CNF_OUT_AF_OD, \
+      .output = 0, \
+      .remap = remapvalue \
+    } \
+  }
+
+#define STM32F4_PIN_I2C1_SCL_MAP0 STM32F4_PIN_I2C(1, 6, STM32F4_GPIO_REMAP_I2C1_0)
+#define STM32F4_PIN_I2C1_SDA_MAP0 STM32F4_PIN_I2C(1, 7, STM32F4_GPIO_REMAP_I2C1_0)
+#define STM32F4_PIN_I2C1_SCL_MAP1 STM32F4_PIN_I2C(1, 8, STM32F4_GPIO_REMAP_I2C1_1)
+#define STM32F4_PIN_I2C1_SDA_MAP1 STM32F4_PIN_I2C(1, 9, STM32F4_GPIO_REMAP_I2C1_1)
+
+#define STM32F4_PIN_I2C2_SCL      STM32F4_PIN_I2C(1, 10, STM32F4_GPIO_REMAP_DONT_CHANGE)
+#define STM32F4_PIN_I2C2_SDA      STM32F4_PIN_I2C(1, 11, STM32F4_GPIO_REMAP_DONT_CHANGE)
+
+/** @} */
+
+#endif /* STM32F4_FAMILY_F10XXX */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_ARM_STM32F4_IO_H */
diff --git a/include/arm/stm32f105rc/bsp/irq.h b/include/arm/stm32f105rc/bsp/irq.h
new file mode 100644
index 0000000000..4771f521fe
--- /dev/null
+++ b/include/arm/stm32f105rc/bsp/irq.h
@@ -0,0 +1,141 @@
+/**
+ * @file
+ * @ingroup stm32f4_interrupt
+ * @brief Interrupt definitions.
+ */
+
+/*
+ * Copyright (c) 2012 Sebastian Huber.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Obere Lagerstr. 30
+ *  82178 Puchheim
+ *  Germany
+ *  <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_STM32F4_IRQ_H
+#define LIBBSP_ARM_STM32F4_IRQ_H
+
+#ifndef ASM
+
+#include <rtems.h>
+#include <rtems/irq.h>
+#include <rtems/irq-extension.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* ASM */
+
+/**
+ * @defgroup stm32f4_interrupt Interrupt Support
+ * @ingroup arm_stm32f4
+ * @brief Interrupt Support
+ * @{
+ */
+
+#define STM32F4_IRQ_WWDG 0
+#define STM32F4_IRQ_PVD 1
+#define STM32F4_IRQ_TAMP_STAMP 2
+#define STM32F4_IRQ_RTC_WKUP 3
+#define STM32F4_IRQ_FLASH 4
+#define STM32F4_IRQ_RCC 5
+#define STM32F4_IRQ_EXTI0 6
+#define STM32F4_IRQ_EXTI1 7
+#define STM32F4_IRQ_EXTI2 8
+#define STM32F4_IRQ_EXTI3 9
+#define STM32F4_IRQ_EXTI4 10
+#define STM32F4_IRQ_DMA1_STREAM0 11
+#define STM32F4_IRQ_DMA1_STREAM1 12
+#define STM32F4_IRQ_DMA1_STREAM2 13
+#define STM32F4_IRQ_DMA1_STREAM3 14
+#define STM32F4_IRQ_DMA1_STREAM4 15
+#define STM32F4_IRQ_DMA1_STREAM5 16
+#define STM32F4_IRQ_DMA1_STREAM6 17
+#define STM32F4_IRQ_ADC 18
+#define STM32F4_IRQ_CAN1_TX 19
+#define STM32F4_IRQ_CAN1_RX0 20
+#define STM32F4_IRQ_CAN1_RX1 21
+#define STM32F4_IRQ_CAN1_SCE 22
+#define STM32F4_IRQ_EXTI9_5 23
+#define STM32F4_IRQ_TIM1_BRK_TIM9 24
+#define STM32F4_IRQ_TIM1_UP_TIM10 25
+#define STM32F4_IRQ_TIM1_TRG_COM_TIM11 26
+#define STM32F4_IRQ_TIM1_CC 27
+#define STM32F4_IRQ_TIM2 28
+#define STM32F4_IRQ_TIM3 29
+#define STM32F4_IRQ_TIM4 30
+#define STM32F4_IRQ_I2C1_EV 31
+#define STM32F4_IRQ_I2C1_ER 32
+#define STM32F4_IRQ_I2C2_EV 33
+#define STM32F4_IRQ_I2C2_ER 34
+#define STM32F4_IRQ_SPI1 35
+#define STM32F4_IRQ_SPI2 36
+#define STM32F4_IRQ_USART1 37
+#define STM32F4_IRQ_USART2 38
+#define STM32F4_IRQ_USART3 39
+#define STM32F4_IRQ_EXTI15_10 40
+#define STM32F4_IRQ_RTC_ALARM 41
+#define STM32F4_IRQ_OTG_FS_WKUP 42
+#define STM32F4_IRQ_TIM8_BRK_TIM12 43
+#define STM32F4_IRQ_TIM8_UP_TIM13 44
+#define STM32F4_IRQ_TIM8_TRG_COM_TIM14 45
+#define STM32F4_IRQ_TIM8_CC 46
+#define STM32F4_IRQ_DMA1_STREAM7 47
+#define STM32F4_IRQ_FSMC 48
+#define STM32F4_IRQ_SDIO 49
+#define STM32F4_IRQ_TIM5 50
+#define STM32F4_IRQ_SPI3 51
+#define STM32F4_IRQ_UART4 52
+#define STM32F4_IRQ_UART5 53
+#define STM32F4_IRQ_TIM6_DAC 54
+#define STM32F4_IRQ_TIM7 55
+#define STM32F4_IRQ_DMA2_STREAM0 56
+#define STM32F4_IRQ_DMA2_STREAM1 57
+#define STM32F4_IRQ_DMA2_STREAM2 58
+#define STM32F4_IRQ_DMA2_STREAM3 59
+#define STM32F4_IRQ_DMA2_STREAM4 60
+#define STM32F4_IRQ_ETH 61
+#define STM32F4_IRQ_ETH_WKUP 62
+#define STM32F4_IRQ_CAN2_TX 63
+#define STM32F4_IRQ_CAN2_RX0 64
+#define STM32F4_IRQ_CAN2_RX1 65
+#define STM32F4_IRQ_CAN2_SCE 66
+#define STM32F4_IRQ_OTG_FS 67
+#define STM32F4_IRQ_DMA2_STREAM5 68
+#define STM32F4_IRQ_DMA2_STREAM6 69
+#define STM32F4_IRQ_DMA2_STREAM7 70
+#define STM32F4_IRQ_USART6 71
+#define STM32F4_IRQ_I2C3_EV 72
+#define STM32F4_IRQ_I2C3_ER 73
+#define STM32F4_IRQ_OTG_HS_EP1_OUT 74
+#define STM32F4_IRQ_OTG_HS_EP1_IN 75
+#define STM32F4_IRQ_OTG_HS_WKUP 76
+#define STM32F4_IRQ_OTG_HS 77
+#define STM32F4_IRQ_DCMI 78
+#define STM32F4_IRQ_CRYP 79
+#define STM32F4_IRQ_HASH_RNG 80
+#define STM32F4_IRQ_FPU 81
+
+#define STM32F4_IRQ_PRIORITY_VALUE_MIN 0
+#define STM32F4_IRQ_PRIORITY_VALUE_MAX 15
+#define STM32F4_IRQ_PRIORITY_COUNT (STM32F4_IRQ_PRIORITY_VALUE_MAX + 1)
+#define STM32F4_IRQ_PRIORITY_HIGHEST STM32F4_IRQ_PRIORITY_VALUE_MIN
+#define STM32F4_IRQ_PRIORITY_LOWEST STM32F4_IRQ_PRIORITY_VALUE_MAX
+
+#define BSP_INTERRUPT_VECTOR_MIN 0
+#define BSP_INTERRUPT_VECTOR_MAX 81
+
+/** @} */
+
+#endif /* LIBBSP_ARM_STM32F4_IRQ_H */
diff --git a/include/arm/stm32f105rc/bsp/usart.h b/include/arm/stm32f105rc/bsp/usart.h
new file mode 100644
index 0000000000..bac0f6845a
--- /dev/null
+++ b/include/arm/stm32f105rc/bsp/usart.h
@@ -0,0 +1,45 @@
+/**
+ * @file
+ * @ingroup stm32f4_usart
+ * @brief USART (universal synchronous/asynchronous receiver/transmitter) support.
+ */
+
+/*
+ * Copyright (c) 2012 Sebastian Huber.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Obere Lagerstr. 30
+ *  82178 Puchheim
+ *  Germany
+ *  <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_STM32F4_USART_H
+#define LIBBSP_ARM_STM32F4_USART_H
+
+#include <libchip/serial.h>
+
+/**
+ * @defgroup stm32f4_usart USART Support
+ * @ingroup arm_stm32f4
+ * @brief USART Support
+ * @{
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+extern const console_fns stm32f4_usart_fns;
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_ARM_STM32F4_USART_H */