diff options
| author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2008-08-15 20:18:41 +0000 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2008-08-15 20:18:41 +0000 |
| commit | 30abd24b7e7bc1f66b22527792931cf4468b06b8 (patch) | |
| tree | fba359b7e4b04fdd1f008f54fcca7b69d810bab6 /c/src/lib/libcpu/bfin/include/sicRegs.h | |
| parent | b035bdc3a88256a4354d3b8dc302b08ab9d43cad (diff) | |
2008-08-15 Allan Hessenflow <allanh@kallisti.com>
* ChangeLog, Makefile.am, README, configure.ac, preinstall.am,
cache/cache.c, cache/cache_.h, clock/clock.c, clock/rtc.c,
clock/tod.h, include/bf533.h, include/bf537.h, include/cecRegs.h,
include/coreTimerRegs.h, include/dmaRegs.h, include/ebiuRegs.h,
include/ethernetRegs.h, include/gpioRegs.h, include/memoryRegs.h,
include/mmuRegs.h, include/ppiRegs.h, include/rtcRegs.h,
include/sicRegs.h, include/spiRegs.h, include/sportRegs.h,
include/timerRegs.h, include/twiRegs.h, include/uartRegs.h,
include/wdogRegs.h, interrupt/interrupt.c, interrupt/interrupt.h,
mmu/mmu.c, mmu/mmu.h, network/ethernet.c, network/ethernet.h,
serial/spi.c, serial/spi.h, serial/sport.c, serial/sport.h,
serial/twi.c, serial/twi.h, serial/uart.c, serial/uart.h,
timer/timer.c: New files.
Diffstat (limited to 'c/src/lib/libcpu/bfin/include/sicRegs.h')
| -rw-r--r-- | c/src/lib/libcpu/bfin/include/sicRegs.h | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/c/src/lib/libcpu/bfin/include/sicRegs.h b/c/src/lib/libcpu/bfin/include/sicRegs.h new file mode 100644 index 0000000000..a3c6c391e1 --- /dev/null +++ b/c/src/lib/libcpu/bfin/include/sicRegs.h @@ -0,0 +1,35 @@ +/* Blackfin System Interrupt Controller Registers + * + * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA + * written by Allan Hessenflow <allanh@kallisti.com> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * $Id$ + */ + +#ifndef _sicRegs_h_ +#define _sicRegs_h_ + +/* register addresses */ + +#define SIC_IMASK (SIC_BASE_ADDRESS + 0x000c) +#define SIC_IAR_BASE_ADDRESS (SIC_BASE_ADDRESS + 0x0010) +#define SIC_IAR_COUNT 4 +#define SIC_IAR_PITCH 0x04 +#define SIC_IAR0 (SIC_BASE_ADDRESS + 0x0010) +#define SIC_IAR1 (SIC_BASE_ADDRESS + 0x0014) +#define SIC_IAR2 (SIC_BASE_ADDRESS + 0x0018) +#define SIC_IAR3 (SIC_BASE_ADDRESS + 0x001c) +#define SIC_ISR (SIC_BASE_ADDRESS + 0x0020) +#define SIC_IWR (SIC_BASE_ADDRESS + 0x0024) + + +/* register fields */ + + + +#endif /* _sicRegs_h_ */ + |