1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
|
/**
* @file
*
* @brief CPU Port Implementation API
*/
/*
* Copyright (c) 2013, 2018 embedded brains GmbH
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _RTEMS_SCORE_CPUIMPL_H
#define _RTEMS_SCORE_CPUIMPL_H
#include <rtems/score/cpu.h>
#define CPU_PER_CPU_CONTROL_SIZE 0
#if __riscv_xlen == 32
#define RISCV_CONTEXT_ISR_DISPATCH_DISABLE 128
#define CPU_INTERRUPT_FRAME_SIZE 140
#elif __riscv_xlen == 64
#define RISCV_CONTEXT_ISR_DISPATCH_DISABLE 256
#define CPU_INTERRUPT_FRAME_SIZE 280
#endif /* __riscv_xlen */
#ifndef ASM
#ifdef __cplusplus
extern "C" {
#endif
typedef struct {
unsigned long x[32];
unsigned long mstatus;
unsigned long mcause;
unsigned long mepc;
} CPU_Interrupt_frame;
#ifdef RTEMS_SMP
static inline struct Per_CPU_Control *_RISCV_Get_current_per_CPU_control( void )
{
struct Per_CPU_Control *cpu_self;
__asm__ volatile ( "csrr %0, mscratch" : "=r" ( cpu_self ) );
return cpu_self;
}
#define _CPU_Get_current_per_CPU_control() _RISCV_Get_current_per_CPU_control()
#endif /* RTEMS_SMP */
#ifdef __cplusplus
}
#endif
#endif /* ASM */
#endif /* _RTEMS_SCORE_CPUIMPL_H */
|
