blob: 53e75595dfb08e577bcfc1e24e266b9733602ea3 (
plain) (
blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
|
/**
* @file
*
* Instantiate the clock driver shell.
*
* This uses the TOY (Time of Year) timer to implement the clock.
*/
/*
* Copyright (c) 2005 by Cogent Computer Systems
* Written by Jay Monkman <jtm@lopingdog.com>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <rtems.h>
#include <bsp.h>
#include <bsp/irq.h>
#include <rtems/bspIo.h>
uint32_t tick_interval;
uint32_t last_match;
void au1x00_clock_init(void);
#define CLOCK_VECTOR AU1X00_IRQ_TOY_MATCH2
#define Clock_driver_support_at_tick() \
do { \
while (AU1X00_SYS_CNTCTRL(AU1X00_SYS_ADDR) & AU1X00_SYS_CNTCTRL_TM0); \
last_match = AU1X00_SYS_TOYREAD(AU1X00_SYS_ADDR); \
AU1X00_SYS_TOYMATCH2(AU1X00_SYS_ADDR) = last_match + tick_interval; \
au_sync(); \
} while(0)
/* Set for rising edge interrupt */
#define Clock_driver_support_install_isr( _new, _old ) \
do { \
rtems_interrupt_handler_install( \
CLOCK_VECTOR, \
"clock", \
0, \
_new, \
NULL \
); \
AU1X00_IC_MASKCLR(AU1X00_IC0_ADDR) = AU1X00_IC_IRQ_TOY_MATCH2; \
AU1X00_IC_SRCSET(AU1X00_IC0_ADDR) = AU1X00_IC_IRQ_TOY_MATCH2; \
AU1X00_IC_CFG0SET(AU1X00_IC0_ADDR) = AU1X00_IC_IRQ_TOY_MATCH2; \
AU1X00_IC_CFG1CLR(AU1X00_IC0_ADDR) = AU1X00_IC_IRQ_TOY_MATCH2; \
AU1X00_IC_CFG2CLR(AU1X00_IC0_ADDR) = AU1X00_IC_IRQ_TOY_MATCH2; \
AU1X00_IC_ASSIGNSET(AU1X00_IC0_ADDR) = AU1X00_IC_IRQ_TOY_MATCH2; \
} while(0)
void au1x00_clock_init(void)
{
uint32_t wakemask;
/* Clear the trim register */
AU1X00_SYS_TOYTRIM(AU1X00_SYS_ADDR) = 0;
/* Clear the TOY counter */
while (AU1X00_SYS_CNTCTRL(AU1X00_SYS_ADDR) & AU1X00_SYS_CNTCTRL_TS);
AU1X00_SYS_TOYWRITE(AU1X00_SYS_ADDR) = 0;
while (AU1X00_SYS_CNTCTRL(AU1X00_SYS_ADDR) & AU1X00_SYS_CNTCTRL_TS);
wakemask = AU1X00_SYS_WAKEMSK(AU1X00_SYS_ADDR);
wakemask |= AU1X00_SYS_WAKEMSK_M20;
AU1X00_SYS_WAKEMSK(AU1X00_SYS_ADDR) = wakemask;
AU1X00_IC_WAKESET(AU1X00_IC0_ADDR) = AU1X00_IC_IRQ_TOY_MATCH2;
tick_interval = 32768 * rtems_configuration_get_microseconds_per_tick();
tick_interval = tick_interval / 1000000;
last_match = AU1X00_SYS_TOYREAD(AU1X00_SYS_ADDR);
AU1X00_SYS_TOYMATCH2(AU1X00_SYS_ADDR) = last_match + (50*tick_interval);
AU1X00_IC_MASKSET(AU1X00_IC0_ADDR) = AU1X00_IC_IRQ_TOY_MATCH2;
while (AU1X00_SYS_CNTCTRL(AU1X00_SYS_ADDR) & AU1X00_SYS_CNTCTRL_TM0);
}
#define Clock_driver_support_initialize_hardware() \
do { \
au1x00_clock_init(); \
} while(0)
#define Clock_driver_support_shutdown_hardware()
#define CLOCK_DRIVER_USE_DUMMY_TIMECOUNTER
#include "../../../shared/clockdrv_shell.h"
|