blob: 718a2625e8e81bee336ff07029e7b1fd374ffef6 (
plain) (
blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
|
/*
* Copyright (c) 2016 embedded brains GmbH Huber. All rights reserved.
*
* embedded brains GmbH
* Dornierstr. 4
* 82178 Puchheim
* Germany
* <rtems@embedded-brains.de>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <bsp.h>
#include <bsp/start.h>
#include <bsp/pin-config.h>
#include <chip.h>
#include <include/board_lowlevel.h>
#include <include/board_memories.h>
void BSP_START_TEXT_SECTION bsp_start_hook_0(void)
{
system_init_flash(BOARD_MCK);
SystemInit();
PIO_Configure(&atsam_pin_config[0], atsam_pin_config_count);
MATRIX->CCFG_SYSIO = atsam_matrix_ccfg_sysio;
if (!PMC_IsPeriphEnabled(ID_SDRAMC)) {
BOARD_ConfigureSdram();
}
if ((SCB->CCR & SCB_CCR_IC_Msk) == 0) {
SCB_EnableICache();
}
if ((SCB->CCR & SCB_CCR_DC_Msk) == 0) {
SCB_EnableDCache();
}
_SetupMemoryRegion();
}
void BSP_START_TEXT_SECTION bsp_start_hook_1(void)
{
bsp_start_copy_sections_compact();
SCB_CleanDCache();
SCB_InvalidateICache();
bsp_start_clear_bss();
WDT_Disable(WDT);
}
|