diff options
Diffstat (limited to 'cpukit/score/cpu/riscv/riscv-context-switch.S')
| -rw-r--r-- | cpukit/score/cpu/riscv/riscv-context-switch.S | 91 |
1 files changed, 29 insertions, 62 deletions
diff --git a/cpukit/score/cpu/riscv/riscv-context-switch.S b/cpukit/score/cpu/riscv/riscv-context-switch.S index b6de9e6f2b..1b82e2aa79 100644 --- a/cpukit/score/cpu/riscv/riscv-context-switch.S +++ b/cpukit/score/cpu/riscv/riscv-context-switch.S @@ -45,75 +45,42 @@ SYM(_CPU_Context_switch): GET_SELF_CPU_CONTROL a2 lw a3, PER_CPU_ISR_DISPATCH_DISABLE(a2) - SREG x1, (1 * CPU_SIZEOF_POINTER)(a0) - SREG x2, (2 * CPU_SIZEOF_POINTER)(a0) - SREG x4, (4 * CPU_SIZEOF_POINTER)(a0) - SREG x5, (5 * CPU_SIZEOF_POINTER)(a0) - SREG x6, (6 * CPU_SIZEOF_POINTER)(a0) - SREG x7, (7 * CPU_SIZEOF_POINTER)(a0) - SREG x8, (8 * CPU_SIZEOF_POINTER)(a0) - SREG x9, (9 * CPU_SIZEOF_POINTER)(a0) - SREG x10, (10 * CPU_SIZEOF_POINTER)(a0) - SREG x11, (11 * CPU_SIZEOF_POINTER)(a0) - SREG x12, (12 * CPU_SIZEOF_POINTER)(a0) - SREG x13, (13 * CPU_SIZEOF_POINTER)(a0) - SREG x14, (14 * CPU_SIZEOF_POINTER)(a0) - SREG x15, (15 * CPU_SIZEOF_POINTER)(a0) - SREG x16, (16 * CPU_SIZEOF_POINTER)(a0) - SREG x17, (17 * CPU_SIZEOF_POINTER)(a0) - SREG x18, (18 * CPU_SIZEOF_POINTER)(a0) - SREG x19, (19 * CPU_SIZEOF_POINTER)(a0) - SREG x20, (20 * CPU_SIZEOF_POINTER)(a0) - SREG x21, (21 * CPU_SIZEOF_POINTER)(a0) - SREG x22, (22 * CPU_SIZEOF_POINTER)(a0) - SREG x23, (23 * CPU_SIZEOF_POINTER)(a0) - SREG x24, (24 * CPU_SIZEOF_POINTER)(a0) - SREG x25, (25 * CPU_SIZEOF_POINTER)(a0) - SREG x26, (26 * CPU_SIZEOF_POINTER)(a0) - SREG x27, (27 * CPU_SIZEOF_POINTER)(a0) - SREG x28, (28 * CPU_SIZEOF_POINTER)(a0) - SREG x29, (28 * CPU_SIZEOF_POINTER)(a0) - SREG x30, (30 * CPU_SIZEOF_POINTER)(a0) - SREG x31, (31 * CPU_SIZEOF_POINTER)(a0) + SREG ra, RISCV_CONTEXT_RA(a0) + SREG sp, RISCV_CONTEXT_SP(a0) + SREG s0, RISCV_CONTEXT_S0(a0) + SREG s1, RISCV_CONTEXT_S1(a0) + SREG s2, RISCV_CONTEXT_S2(a0) + SREG s3, RISCV_CONTEXT_S3(a0) + SREG s4, RISCV_CONTEXT_S4(a0) + SREG s5, RISCV_CONTEXT_S5(a0) + SREG s6, RISCV_CONTEXT_S6(a0) + SREG s7, RISCV_CONTEXT_S7(a0) + SREG s8, RISCV_CONTEXT_S8(a0) + SREG s9, RISCV_CONTEXT_S9(a0) + SREG s10, RISCV_CONTEXT_S10(a0) + SREG s11, RISCV_CONTEXT_S11(a0) sw a3, RISCV_CONTEXT_ISR_DISPATCH_DISABLE(a0) .Lrestore: lw a3, RISCV_CONTEXT_ISR_DISPATCH_DISABLE(a1) - sw a3, PER_CPU_ISR_DISPATCH_DISABLE(a2) - - LREG x1, (1 * CPU_SIZEOF_POINTER)(a1) - LREG x2, (2 * CPU_SIZEOF_POINTER)(a1) - LREG x4, (4 * CPU_SIZEOF_POINTER)(a1) - LREG x5, (5 * CPU_SIZEOF_POINTER)(a1) - LREG x6, (6 * CPU_SIZEOF_POINTER)(a1) - LREG x7, (7 * CPU_SIZEOF_POINTER)(a1) - LREG x8, (8 * CPU_SIZEOF_POINTER)(a1) - LREG x9, (9 * CPU_SIZEOF_POINTER)(a1) - LREG x10, (10 * CPU_SIZEOF_POINTER)(a1) - /* Skip a1/x11 */ - LREG x12, (12 * CPU_SIZEOF_POINTER)(a1) - LREG x13, (13 * CPU_SIZEOF_POINTER)(a1) - LREG x14, (14 * CPU_SIZEOF_POINTER)(a1) - LREG x15, (15 * CPU_SIZEOF_POINTER)(a1) - LREG x16, (16 * CPU_SIZEOF_POINTER)(a1) - LREG x17, (17 * CPU_SIZEOF_POINTER)(a1) - LREG x18, (18 * CPU_SIZEOF_POINTER)(a1) - LREG x19, (19 * CPU_SIZEOF_POINTER)(a1) - LREG x20, (20 * CPU_SIZEOF_POINTER)(a1) - LREG x21, (21 * CPU_SIZEOF_POINTER)(a1) - LREG x22, (22 * CPU_SIZEOF_POINTER)(a1) - LREG x23, (23 * CPU_SIZEOF_POINTER)(a1) - LREG x24, (24 * CPU_SIZEOF_POINTER)(a1) - LREG x25, (25 * CPU_SIZEOF_POINTER)(a1) - LREG x26, (26 * CPU_SIZEOF_POINTER)(a1) - LREG x27, (27 * CPU_SIZEOF_POINTER)(a1) - LREG x28, (28 * CPU_SIZEOF_POINTER)(a1) - LREG x29, (29 * CPU_SIZEOF_POINTER)(a1) - LREG x30, (30 * CPU_SIZEOF_POINTER)(a1) + LREG ra, RISCV_CONTEXT_RA(a1) + LREG sp, RISCV_CONTEXT_SP(a1) + LREG s0, RISCV_CONTEXT_S0(a1) + LREG s1, RISCV_CONTEXT_S1(a1) + LREG s2, RISCV_CONTEXT_S2(a1) + LREG s3, RISCV_CONTEXT_S3(a1) + LREG s4, RISCV_CONTEXT_S4(a1) + LREG s5, RISCV_CONTEXT_S5(a1) + LREG s6, RISCV_CONTEXT_S6(a1) + LREG s7, RISCV_CONTEXT_S7(a1) + LREG s8, RISCV_CONTEXT_S8(a1) + LREG s9, RISCV_CONTEXT_S9(a1) + LREG s10, RISCV_CONTEXT_S10(a1) + LREG s11, RISCV_CONTEXT_S11(a1) - LREG x11, (11 * CPU_SIZEOF_POINTER)(a1) + sw a3, PER_CPU_ISR_DISPATCH_DISABLE(a2) ret |