diff options
Diffstat (limited to 'cpukit/score/cpu/riscv/cpu.c')
| -rw-r--r-- | cpukit/score/cpu/riscv/cpu.c | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/cpukit/score/cpu/riscv/cpu.c b/cpukit/score/cpu/riscv/cpu.c index c5d309a5d6..87e61f1ec9 100644 --- a/cpukit/score/cpu/riscv/cpu.c +++ b/cpukit/score/cpu/riscv/cpu.c @@ -40,6 +40,56 @@ ) RISCV_ASSERT_CONTEXT_OFFSET( isr_dispatch_disable, ISR_DISPATCH_DISABLE ); +#ifdef RTEMS_SMP +RISCV_ASSERT_CONTEXT_OFFSET( is_executing, IS_EXECUTING ); +#endif +RISCV_ASSERT_CONTEXT_OFFSET( ra, RA ); +RISCV_ASSERT_CONTEXT_OFFSET( sp, SP ); +RISCV_ASSERT_CONTEXT_OFFSET( tp, TP ); +RISCV_ASSERT_CONTEXT_OFFSET( s0, S0 ); +RISCV_ASSERT_CONTEXT_OFFSET( s1, S1 ); +RISCV_ASSERT_CONTEXT_OFFSET( s2, S2 ); +RISCV_ASSERT_CONTEXT_OFFSET( s3, S3 ); +RISCV_ASSERT_CONTEXT_OFFSET( s4, S4 ); +RISCV_ASSERT_CONTEXT_OFFSET( s5, S5 ); +RISCV_ASSERT_CONTEXT_OFFSET( s6, S6 ); +RISCV_ASSERT_CONTEXT_OFFSET( s7, S7 ); +RISCV_ASSERT_CONTEXT_OFFSET( s8, S8 ); +RISCV_ASSERT_CONTEXT_OFFSET( s9, S9 ); +RISCV_ASSERT_CONTEXT_OFFSET( s10, S10 ); +RISCV_ASSERT_CONTEXT_OFFSET( s11, S11 ); + +#define RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( field, off ) \ + RTEMS_STATIC_ASSERT( \ + offsetof( CPU_Interrupt_frame, field) == RISCV_INTERRUPT_FRAME_ ## off, \ + riscv_interrupt_frame_offset_ ## field \ + ) + +RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( mstatus, MSTATUS ); +RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( mepc, MEPC ); +RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( a2, A2 ); +RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( s0, S0 ); +RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( s1, S1 ); +RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( ra, RA ); +RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( a3, A3 ); +RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( a4, A4 ); +RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( a5, A5 ); +RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( a6, A6 ); +RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( a7, A7 ); +RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( t0, T0 ); +RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( t1, T1 ); +RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( t2, T2 ); +RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( t3, T3 ); +RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( t4, T4 ); +RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( t5, T5 ); +RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( t6, T6 ); +RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( a0, A0 ); +RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( a1, A1 ); + +RTEMS_STATIC_ASSERT( + sizeof( CPU_Interrupt_frame ) % CPU_STACK_ALIGNMENT == 0, + riscv_interrupt_frame_size +); /* bsp_start_vector_table_begin is the start address of the vector table * containing addresses to ISR Handlers. It's defined at the BSP linkcmds |