diff options
Diffstat (limited to 'cpukit/score/cpu/moxie/rtems/score/cpu.h')
| -rw-r--r-- | cpukit/score/cpu/moxie/rtems/score/cpu.h | 31 |
1 files changed, 22 insertions, 9 deletions
diff --git a/cpukit/score/cpu/moxie/rtems/score/cpu.h b/cpukit/score/cpu/moxie/rtems/score/cpu.h index cf226011d4..4b204cbb43 100644 --- a/cpukit/score/cpu/moxie/rtems/score/cpu.h +++ b/cpukit/score/cpu/moxie/rtems/score/cpu.h @@ -570,9 +570,12 @@ SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; * * MOXIE Specific Information: * - * XXX + * TODO: As of 7 October 2014, this method is not implemented. */ -#define _CPU_ISR_Disable( _isr_cookie ) (_isr_cookie) = 0 +#define _CPU_ISR_Disable( _isr_cookie ) \ + do { \ + (_isr_cookie) = 0; \ + } while (0) /* * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). @@ -581,9 +584,12 @@ SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; * * MOXIE Specific Information: * - * XXX + * TODO: As of 7 October 2014, this method is not implemented. */ -#define _CPU_ISR_Enable( _isr_cookie ) +#define _CPU_ISR_Enable( _isr_cookie ) \ + do { \ + (_isr_cookie) = (_isr_cookie); \ + } while (0) /* * This temporarily restores the interrupt to _level before immediately @@ -593,9 +599,13 @@ SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; * * MOXIE Specific Information: * - * XXX + * TODO: As of 7 October 2014, this method is not implemented. */ -#define _CPU_ISR_Flash( _isr_cookie ) +#define _CPU_ISR_Flash( _isr_cookie ) \ + do { \ + _CPU_ISR_Enable( _isr_cookie ); \ + _CPU_ISR_Disable( _isr_cookie ); \ + } while (0) /* * Map interrupt level in task mode onto the hardware that the CPU @@ -609,7 +619,7 @@ SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; * * MOXIE Specific Information: * - * XXX + * TODO: As of 7 October 2014, this method is not implemented. */ #define _CPU_ISR_Set_level( _new_level ) \ { \ @@ -645,7 +655,8 @@ uint32_t _CPU_ISR_Get_level( void ); * * MOXIE Specific Information: * - * XXX + * TODO: As of 7 October 2014, this method does not ensure that the context + * is set up with interrupts disabled/enabled as requested. */ #define CPU_CCR_INTERRUPTS_ON 0x80 #define CPU_CCR_INTERRUPTS_OFF 0x00 @@ -656,6 +667,8 @@ uint32_t _CPU_ISR_Get_level( void ); do { \ uintptr_t _stack; \ \ + (void) _is_fp; /* avoid warning for being unused */ \ + (void) _isr; /* avoid warning for being unused */ \ _stack = ((uintptr_t)(_stack_base)) + (_size) - 8; \ *((proc_ptr *)(_stack)) = (_entry_point); \ _stack -= 4; \ @@ -948,7 +961,7 @@ void _CPU_Context_switch( */ void _CPU_Context_restore( Context_Control *new_context -); +) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE; /* * _CPU_Context_save_fp |