diff options
Diffstat (limited to 'c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_fatal.S')
| -rw-r--r-- | c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_fatal.S | 90 |
1 files changed, 45 insertions, 45 deletions
diff --git a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_fatal.S b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_fatal.S index 31774a792a..0bfba57352 100644 --- a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_fatal.S +++ b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_fatal.S @@ -26,80 +26,80 @@ ppc_exc_fatal_critical: - stw SCRATCH_REGISTER_1, GPR4_OFFSET(r1) + PPC_REG_STORE SCRATCH_REGISTER_1, GPR4_OFFSET(r1) mfcsrr0 SCRATCH_REGISTER_1 - stw SCRATCH_REGISTER_1, SRR0_FRAME_OFFSET(r1) + PPC_REG_STORE SCRATCH_REGISTER_1, SRR0_FRAME_OFFSET(r1) mfcsrr1 SCRATCH_REGISTER_1 - stw SCRATCH_REGISTER_1, SRR1_FRAME_OFFSET(r1) + PPC_REG_STORE SCRATCH_REGISTER_1, SRR1_FRAME_OFFSET(r1) b .Lppc_exc_fatal ppc_exc_fatal_machine_check: - stw SCRATCH_REGISTER_1, GPR4_OFFSET(r1) + PPC_REG_STORE SCRATCH_REGISTER_1, GPR4_OFFSET(r1) mfmcsrr0 SCRATCH_REGISTER_1 - stw SCRATCH_REGISTER_1, SRR0_FRAME_OFFSET(r1) + PPC_REG_STORE SCRATCH_REGISTER_1, SRR0_FRAME_OFFSET(r1) mfmcsrr1 SCRATCH_REGISTER_1 - stw SCRATCH_REGISTER_1, SRR1_FRAME_OFFSET(r1) + PPC_REG_STORE SCRATCH_REGISTER_1, SRR1_FRAME_OFFSET(r1) b .Lppc_exc_fatal ppc_exc_fatal_debug: - stw SCRATCH_REGISTER_1, GPR4_OFFSET(r1) + PPC_REG_STORE SCRATCH_REGISTER_1, GPR4_OFFSET(r1) mfspr SCRATCH_REGISTER_1, BOOKE_DSRR0 - stw SCRATCH_REGISTER_1, SRR0_FRAME_OFFSET(r1) + PPC_REG_STORE SCRATCH_REGISTER_1, SRR0_FRAME_OFFSET(r1) mfspr SCRATCH_REGISTER_1, BOOKE_DSRR1 - stw SCRATCH_REGISTER_1, SRR1_FRAME_OFFSET(r1) + PPC_REG_STORE SCRATCH_REGISTER_1, SRR1_FRAME_OFFSET(r1) b .Lppc_exc_fatal ppc_exc_fatal_normal: - stw SCRATCH_REGISTER_1, GPR4_OFFSET(r1) + PPC_REG_STORE SCRATCH_REGISTER_1, GPR4_OFFSET(r1) mfsrr0 SCRATCH_REGISTER_1 - stw SCRATCH_REGISTER_1, SRR0_FRAME_OFFSET(r1) + PPC_REG_STORE SCRATCH_REGISTER_1, SRR0_FRAME_OFFSET(r1) mfsrr1 SCRATCH_REGISTER_1 - stw SCRATCH_REGISTER_1, SRR1_FRAME_OFFSET(r1) + PPC_REG_STORE SCRATCH_REGISTER_1, SRR1_FRAME_OFFSET(r1) .Lppc_exc_fatal: stw r3, EXCEPTION_NUMBER_OFFSET(r1) mfcr SCRATCH_REGISTER_1 stw SCRATCH_REGISTER_1, EXC_CR_OFFSET(r1) - mfctr SCRATCH_REGISTER_1 - stw SCRATCH_REGISTER_1, EXC_CTR_OFFSET(r1) mfxer SCRATCH_REGISTER_1 stw SCRATCH_REGISTER_1, EXC_XER_OFFSET(r1) + mfctr SCRATCH_REGISTER_1 + PPC_REG_STORE SCRATCH_REGISTER_1, EXC_CTR_OFFSET(r1) mflr SCRATCH_REGISTER_1 - stw SCRATCH_REGISTER_1, EXC_LR_OFFSET(r1) - stw r0, GPR0_OFFSET(r1) - stw r1, GPR1_OFFSET(r1) - stw r2, GPR2_OFFSET(r1) - stw r5, GPR5_OFFSET(r1) - stw r6, GPR6_OFFSET(r1) - stw r7, GPR7_OFFSET(r1) - stw r8, GPR8_OFFSET(r1) - stw r9, GPR9_OFFSET(r1) - stw r10, GPR10_OFFSET(r1) - stw r11, GPR11_OFFSET(r1) - stw r12, GPR12_OFFSET(r1) - stw r13, GPR13_OFFSET(r1) - stw r14, GPR14_OFFSET(r1) - stw r15, GPR15_OFFSET(r1) - stw r16, GPR16_OFFSET(r1) - stw r17, GPR17_OFFSET(r1) - stw r18, GPR18_OFFSET(r1) - stw r19, GPR19_OFFSET(r1) - stw r20, GPR20_OFFSET(r1) - stw r21, GPR21_OFFSET(r1) - stw r22, GPR22_OFFSET(r1) - stw r23, GPR23_OFFSET(r1) - stw r24, GPR24_OFFSET(r1) - stw r25, GPR25_OFFSET(r1) - stw r26, GPR26_OFFSET(r1) - stw r27, GPR27_OFFSET(r1) - stw r28, GPR28_OFFSET(r1) - stw r29, GPR29_OFFSET(r1) - stw r30, GPR30_OFFSET(r1) - stw r31, GPR31_OFFSET(r1) + PPC_REG_STORE SCRATCH_REGISTER_1, EXC_LR_OFFSET(r1) + PPC_REG_STORE r0, GPR0_OFFSET(r1) + PPC_REG_STORE r1, GPR1_OFFSET(r1) + PPC_REG_STORE r2, GPR2_OFFSET(r1) + PPC_REG_STORE r5, GPR5_OFFSET(r1) + PPC_REG_STORE r6, GPR6_OFFSET(r1) + PPC_REG_STORE r7, GPR7_OFFSET(r1) + PPC_REG_STORE r8, GPR8_OFFSET(r1) + PPC_REG_STORE r9, GPR9_OFFSET(r1) + PPC_REG_STORE r10, GPR10_OFFSET(r1) + PPC_REG_STORE r11, GPR11_OFFSET(r1) + PPC_REG_STORE r12, GPR12_OFFSET(r1) + PPC_REG_STORE r13, GPR13_OFFSET(r1) + PPC_REG_STORE r14, GPR14_OFFSET(r1) + PPC_REG_STORE r15, GPR15_OFFSET(r1) + PPC_REG_STORE r16, GPR16_OFFSET(r1) + PPC_REG_STORE r17, GPR17_OFFSET(r1) + PPC_REG_STORE r18, GPR18_OFFSET(r1) + PPC_REG_STORE r19, GPR19_OFFSET(r1) + PPC_REG_STORE r20, GPR20_OFFSET(r1) + PPC_REG_STORE r21, GPR21_OFFSET(r1) + PPC_REG_STORE r22, GPR22_OFFSET(r1) + PPC_REG_STORE r23, GPR23_OFFSET(r1) + PPC_REG_STORE r24, GPR24_OFFSET(r1) + PPC_REG_STORE r25, GPR25_OFFSET(r1) + PPC_REG_STORE r26, GPR26_OFFSET(r1) + PPC_REG_STORE r27, GPR27_OFFSET(r1) + PPC_REG_STORE r28, GPR28_OFFSET(r1) + PPC_REG_STORE r29, GPR29_OFFSET(r1) + PPC_REG_STORE r30, GPR30_OFFSET(r1) + PPC_REG_STORE r31, GPR31_OFFSET(r1) /* Enable FPU and/or AltiVec */ #if defined(PPC_MULTILIB_FPU) || defined(PPC_MULTILIB_ALTIVEC) |