diff options
Diffstat (limited to 'c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_async_normal.S')
| -rw-r--r-- | c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_async_normal.S | 74 |
1 files changed, 32 insertions, 42 deletions
diff --git a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_async_normal.S b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_async_normal.S index 7a137a526d..c131bf0de0 100644 --- a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_async_normal.S +++ b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_async_normal.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011, 2016 embedded brains GmbH. All rights reserved. + * Copyright (c) 2011, 2017 embedded brains GmbH. All rights reserved. * * embedded brains GmbH * Dornierstr. 4 @@ -40,19 +40,9 @@ #define SCRATCH_3_OFFSET GPR10_OFFSET #define SCRATCH_4_OFFSET GPR11_OFFSET #define SCRATCH_5_OFFSET GPR12_OFFSET - -/* - * The register 2 slot is free, since this is the read-only small data anchor. - */ -#define FRAME_OFFSET GPR2_OFFSET +#define FRAME_OFFSET PPC_EXC_INTERRUPT_FRAME_OFFSET #ifdef RTEMS_PROFILING -/* - * The CPU_INTERRUPT_FRAME_SIZE is enough to store this additional register. - */ -#define ENTRY_INSTANT_REGISTER r15 -#define ENTRY_INSTANT_OFFSET GPR13_OFFSET - .macro GET_TIME_BASE REG #if defined(__PPC_CPU_E6500__) mfspr \REG, FSL_EIS_ATBL @@ -88,17 +78,15 @@ ppc_exc_min_prolog_async_tmpl_normal: ppc_exc_interrupt: -#ifdef RTEMS_PROFILING - /* Save non-volatile ENTRY_INSTANT_REGISTER */ - stw ENTRY_INSTANT_REGISTER, ENTRY_INSTANT_OFFSET(r1) + /* Save non-volatile FRAME_REGISTER */ + PPC_REG_STORE FRAME_REGISTER, FRAME_OFFSET(r1) +#ifdef RTEMS_PROFILING /* Get entry instant */ - GET_TIME_BASE ENTRY_INSTANT_REGISTER + GET_TIME_BASE FRAME_REGISTER + stw FRAME_REGISTER, PPC_EXC_INTERRUPT_ENTRY_INSTANT_OFFSET(r1) #endif /* RTEMS_PROFILING */ - /* Save non-volatile FRAME_REGISTER */ - stw FRAME_REGISTER, FRAME_OFFSET(r1) - #ifdef __SPE__ /* Enable SPE */ mfmsr FRAME_REGISTER @@ -162,25 +150,29 @@ ppc_exc_interrupt: lwzx HANDLER_REGISTER, HANDLER_REGISTER, SCRATCH_0_REGISTER #endif /* PPC_EXC_CONFIG_USE_FIXED_HANDLER */ +#ifdef __powerpc64__ + PPC_GPR_STORE r2, GPR2_OFFSET(r1) + LA32 r2, .TOC. +#endif PPC_GPR_STORE SCRATCH_1_REGISTER, SCRATCH_1_OFFSET(r1) PPC_GPR_STORE SCRATCH_2_REGISTER, SCRATCH_2_OFFSET(r1) PPC_GPR_STORE SCRATCH_3_REGISTER, SCRATCH_3_OFFSET(r1) PPC_GPR_STORE SCRATCH_4_REGISTER, SCRATCH_4_OFFSET(r1) PPC_GPR_STORE SCRATCH_5_REGISTER, SCRATCH_5_OFFSET(r1) - /* Save SRR0, SRR1, CR, CTR, XER, and LR */ + /* Save SRR0, SRR1, CR, XER, CTR, and LR */ mfsrr0 SCRATCH_0_REGISTER mfsrr1 SCRATCH_1_REGISTER mfcr SCRATCH_2_REGISTER - mfctr SCRATCH_3_REGISTER - mfxer SCRATCH_4_REGISTER + mfxer SCRATCH_3_REGISTER + mfctr SCRATCH_4_REGISTER mflr SCRATCH_5_REGISTER - stw SCRATCH_0_REGISTER, SRR0_FRAME_OFFSET(r1) - stw SCRATCH_1_REGISTER, SRR1_FRAME_OFFSET(r1) + PPC_REG_STORE SCRATCH_0_REGISTER, SRR0_FRAME_OFFSET(r1) + PPC_REG_STORE SCRATCH_1_REGISTER, SRR1_FRAME_OFFSET(r1) stw SCRATCH_2_REGISTER, EXC_CR_OFFSET(r1) - stw SCRATCH_3_REGISTER, EXC_CTR_OFFSET(r1) - stw SCRATCH_4_REGISTER, EXC_XER_OFFSET(r1) - stw SCRATCH_5_REGISTER, EXC_LR_OFFSET(r1) + stw SCRATCH_3_REGISTER, EXC_XER_OFFSET(r1) + PPC_REG_STORE SCRATCH_4_REGISTER, EXC_CTR_OFFSET(r1) + PPC_REG_STORE SCRATCH_5_REGISTER, EXC_LR_OFFSET(r1) #ifdef __SPE__ /* Save SPEFSCR and ACC */ @@ -292,7 +284,7 @@ ppc_exc_interrupt: /* Update profiling data if necessary */ bne cr2, .Lprofiling_done GET_SELF_CPU_CONTROL r3 - mr r4, ENTRY_INSTANT_REGISTER + lwz r4, PPC_EXC_INTERRUPT_ENTRY_INSTANT_OFFSET(FRAME_REGISTER) GET_TIME_BASE r5 bl _Profiling_Outer_most_interrupt_entry_and_exit .Lprofiling_done: @@ -310,7 +302,7 @@ ppc_exc_interrupt: * on the IRQ stack) and restore FRAME_REGISTER. */ mr r1, FRAME_REGISTER - lwz FRAME_REGISTER, FRAME_OFFSET(r1) + PPC_REG_LOAD FRAME_REGISTER, FRAME_OFFSET(r1) /* Decrement levels and determine thread dispatch state */ xori SCRATCH_0_REGISTER, SCRATCH_0_REGISTER, 1 @@ -458,13 +450,13 @@ ppc_exc_interrupt: li SCRATCH_0_REGISTER, FRAME_OFFSET stwcx. SCRATCH_0_REGISTER, r1, SCRATCH_0_REGISTER - /* Load SRR0, SRR1, CR, CTR, XER, and LR */ - lwz SCRATCH_0_REGISTER, SRR0_FRAME_OFFSET(r1) - lwz SCRATCH_1_REGISTER, SRR1_FRAME_OFFSET(r1) + /* Load SRR0, SRR1, CR, XER, CTR, and LR */ + PPC_REG_LOAD SCRATCH_0_REGISTER, SRR0_FRAME_OFFSET(r1) + PPC_REG_LOAD SCRATCH_1_REGISTER, SRR1_FRAME_OFFSET(r1) lwz SCRATCH_2_REGISTER, EXC_CR_OFFSET(r1) - lwz SCRATCH_3_REGISTER, EXC_CTR_OFFSET(r1) - lwz SCRATCH_4_REGISTER, EXC_XER_OFFSET(r1) - lwz SCRATCH_5_REGISTER, EXC_LR_OFFSET(r1) + lwz SCRATCH_3_REGISTER, EXC_XER_OFFSET(r1) + PPC_REG_LOAD SCRATCH_4_REGISTER, EXC_CTR_OFFSET(r1) + PPC_REG_LOAD SCRATCH_5_REGISTER, EXC_LR_OFFSET(r1) PPC_GPR_LOAD VECTOR_REGISTER, VECTOR_OFFSET(r1) PPC_GPR_LOAD SELF_CPU_REGISTER, SELF_CPU_OFFSET(r1) @@ -486,21 +478,19 @@ ppc_exc_interrupt: mtsrr0 SCRATCH_0_REGISTER PPC_GPR_LOAD SCRATCH_0_REGISTER, SCRATCH_0_OFFSET(r1) mtsrr1 SCRATCH_1_REGISTER +#ifdef __powerpc64__ + PPC_GPR_LOAD r2, GPR2_OFFSET(r1) +#endif PPC_GPR_LOAD SCRATCH_1_REGISTER, SCRATCH_1_OFFSET(r1) mtcr SCRATCH_2_REGISTER PPC_GPR_LOAD SCRATCH_2_REGISTER, SCRATCH_2_OFFSET(r1) - mtctr SCRATCH_3_REGISTER + mtxer SCRATCH_3_REGISTER PPC_GPR_LOAD SCRATCH_3_REGISTER, SCRATCH_3_OFFSET(r1) - mtxer SCRATCH_4_REGISTER + mtctr SCRATCH_4_REGISTER PPC_GPR_LOAD SCRATCH_4_REGISTER, SCRATCH_4_OFFSET(r1) mtlr SCRATCH_5_REGISTER PPC_GPR_LOAD SCRATCH_5_REGISTER, SCRATCH_5_OFFSET(r1) -#ifdef RTEMS_PROFILING - /* Restore ENTRY_INSTANT_REGISTER */ - lwz ENTRY_INSTANT_REGISTER, ENTRY_INSTANT_OFFSET(r1) -#endif /* RTEMS_PROFILING */ - /* Pop stack */ addi r1, r1, PPC_EXC_INTERRUPT_FRAME_SIZE |