diff options
Diffstat (limited to 'c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_asm_macros.h')
| -rw-r--r-- | c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_asm_macros.h | 247 |
1 files changed, 245 insertions, 2 deletions
diff --git a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_asm_macros.h b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_asm_macros.h index 0e3bc96895..c89046619b 100644 --- a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_asm_macros.h +++ b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_asm_macros.h @@ -426,6 +426,19 @@ wrap_no_save_frame_register_\_FLVR: /* Check exception type and remember it in non-volatile CR_TYPE */ cmpwi CR_TYPE, VECTOR_REGISTER, 0 +#if defined(PPC_MULTILIB_FPU) || defined(PPC_MULTILIB_ALTIVEC) + /* Enable FPU and/or AltiVec */ + mfmsr SCRATCH_REGISTER_0 +#ifdef PPC_MULTILIB_FPU + ori SCRATCH_REGISTER_0, SCRATCH_REGISTER_0, MSR_FP +#endif +#ifdef PPC_MULTILIB_ALTIVEC + oris SCRATCH_REGISTER_0, SCRATCH_REGISTER_0, MSR_VE >> 16 +#endif + mtmsr SCRATCH_REGISTER_0 + isync +#endif + /* * Depending on the exception type we do now save the non-volatile * registers or disable thread dispatching and switch to the ISR stack. @@ -545,7 +558,7 @@ wrap_change_msr_done_\_FLVR: #endif /* PPC_EXC_CONFIG_BOOKE_ONLY */ -#ifdef __ALTIVEC__ +#if defined(__ALTIVEC__) && !defined(PPC_MULTILIB_ALTIVEC) LA SCRATCH_REGISTER_0, _CPU_save_altivec_volatile mtctr SCRATCH_REGISTER_0 addi r3, FRAME_REGISTER, EXC_VEC_OFFSET @@ -566,6 +579,71 @@ wrap_change_msr_done_\_FLVR: lwz VECTOR_REGISTER, EXCEPTION_NUMBER_OFFSET(FRAME_REGISTER) #endif +#ifdef PPC_MULTILIB_ALTIVEC + li SCRATCH_REGISTER_0, PPC_EXC_VR_OFFSET(0) + stvx v0, FRAME_REGISTER, SCRATCH_REGISTER_0 + mfvscr v0 + li SCRATCH_REGISTER_0, PPC_EXC_VR_OFFSET(1) + stvx v1, FRAME_REGISTER, SCRATCH_REGISTER_0 + li SCRATCH_REGISTER_0, PPC_EXC_VR_OFFSET(2) + stvx v2, FRAME_REGISTER, SCRATCH_REGISTER_0 + li SCRATCH_REGISTER_0, PPC_EXC_VR_OFFSET(3) + stvx v3, FRAME_REGISTER, SCRATCH_REGISTER_0 + li SCRATCH_REGISTER_0, PPC_EXC_VR_OFFSET(4) + stvx v4, FRAME_REGISTER, SCRATCH_REGISTER_0 + li SCRATCH_REGISTER_0, PPC_EXC_VR_OFFSET(5) + stvx v5, FRAME_REGISTER, SCRATCH_REGISTER_0 + li SCRATCH_REGISTER_0, PPC_EXC_VR_OFFSET(6) + stvx v6, FRAME_REGISTER, SCRATCH_REGISTER_0 + li SCRATCH_REGISTER_0, PPC_EXC_VR_OFFSET(7) + stvx v7, FRAME_REGISTER, SCRATCH_REGISTER_0 + li SCRATCH_REGISTER_0, PPC_EXC_VR_OFFSET(8) + stvx v8, FRAME_REGISTER, SCRATCH_REGISTER_0 + li SCRATCH_REGISTER_0, PPC_EXC_VR_OFFSET(9) + stvx v9, FRAME_REGISTER, SCRATCH_REGISTER_0 + li SCRATCH_REGISTER_0, PPC_EXC_VR_OFFSET(0) + stvx v10, FRAME_REGISTER, SCRATCH_REGISTER_0 + li SCRATCH_REGISTER_0, PPC_EXC_VR_OFFSET(11) + stvx v11, FRAME_REGISTER, SCRATCH_REGISTER_0 + li SCRATCH_REGISTER_0, PPC_EXC_VR_OFFSET(12) + stvx v12, FRAME_REGISTER, SCRATCH_REGISTER_0 + li SCRATCH_REGISTER_0, PPC_EXC_VR_OFFSET(13) + stvx v13, FRAME_REGISTER, SCRATCH_REGISTER_0 + li SCRATCH_REGISTER_0, PPC_EXC_VR_OFFSET(14) + stvx v14, FRAME_REGISTER, SCRATCH_REGISTER_0 + li SCRATCH_REGISTER_0, PPC_EXC_VR_OFFSET(15) + stvx v15, FRAME_REGISTER, SCRATCH_REGISTER_0 + li SCRATCH_REGISTER_0, PPC_EXC_VR_OFFSET(16) + stvx v16, FRAME_REGISTER, SCRATCH_REGISTER_0 + li SCRATCH_REGISTER_0, PPC_EXC_VR_OFFSET(17) + stvx v17, FRAME_REGISTER, SCRATCH_REGISTER_0 + li SCRATCH_REGISTER_0, PPC_EXC_VR_OFFSET(18) + stvx v18, FRAME_REGISTER, SCRATCH_REGISTER_0 + li SCRATCH_REGISTER_0, PPC_EXC_VR_OFFSET(19) + stvx v19, FRAME_REGISTER, SCRATCH_REGISTER_0 + li SCRATCH_REGISTER_0, PPC_EXC_VSCR_OFFSET + stvewx v0, r1, SCRATCH_REGISTER_0 +#endif + +#ifdef PPC_MULTILIB_FPU + stfd f0, PPC_EXC_FR_OFFSET(0)(FRAME_REGISTER) + mffs f0 + stfd f1, PPC_EXC_FR_OFFSET(1)(FRAME_REGISTER) + stfd f2, PPC_EXC_FR_OFFSET(2)(FRAME_REGISTER) + stfd f3, PPC_EXC_FR_OFFSET(3)(FRAME_REGISTER) + stfd f4, PPC_EXC_FR_OFFSET(4)(FRAME_REGISTER) + stfd f5, PPC_EXC_FR_OFFSET(5)(FRAME_REGISTER) + stfd f6, PPC_EXC_FR_OFFSET(6)(FRAME_REGISTER) + stfd f7, PPC_EXC_FR_OFFSET(7)(FRAME_REGISTER) + stfd f8, PPC_EXC_FR_OFFSET(8)(FRAME_REGISTER) + stfd f9, PPC_EXC_FR_OFFSET(9)(FRAME_REGISTER) + stfd f10, PPC_EXC_FR_OFFSET(10)(FRAME_REGISTER) + stfd f11, PPC_EXC_FR_OFFSET(11)(FRAME_REGISTER) + stfd f12, PPC_EXC_FR_OFFSET(12)(FRAME_REGISTER) + stfd f13, PPC_EXC_FR_OFFSET(13)(FRAME_REGISTER) + stfd f0, PPC_EXC_FPSCR_OFFSET(FRAME_REGISTER) +#endif + /* * Call high level exception handler */ @@ -666,13 +744,78 @@ wrap_handler_done_\_FLVR: wrap_thread_dispatching_done_\_FLVR: -#ifdef __ALTIVEC__ +#if defined(__ALTIVEC__) && !defined(PPC_MULTILIB_ALTIVEC) LA SCRATCH_REGISTER_0, _CPU_load_altivec_volatile mtctr SCRATCH_REGISTER_0 addi r3, FRAME_REGISTER, EXC_VEC_OFFSET bctrl #endif +#ifdef PPC_MULTILIB_ALTIVEC + li SCRATCH_REGISTER_0, PPC_EXC_MIN_VSCR_OFFSET + lvewx v0, r1, SCRATCH_REGISTER_0 + mtvscr v0 + li SCRATCH_REGISTER_0, PPC_EXC_VR_OFFSET(0) + lvx v0, FRAME_REGISTER, SCRATCH_REGISTER_0 + li SCRATCH_REGISTER_0, PPC_EXC_VR_OFFSET(1) + lvx v1, FRAME_REGISTER, SCRATCH_REGISTER_0 + li SCRATCH_REGISTER_0, PPC_EXC_VR_OFFSET(2) + lvx v2, FRAME_REGISTER, SCRATCH_REGISTER_0 + li SCRATCH_REGISTER_0, PPC_EXC_VR_OFFSET(3) + lvx v3, FRAME_REGISTER, SCRATCH_REGISTER_0 + li SCRATCH_REGISTER_0, PPC_EXC_VR_OFFSET(4) + lvx v4, FRAME_REGISTER, SCRATCH_REGISTER_0 + li SCRATCH_REGISTER_0, PPC_EXC_VR_OFFSET(5) + lvx v5, FRAME_REGISTER, SCRATCH_REGISTER_0 + li SCRATCH_REGISTER_0, PPC_EXC_VR_OFFSET(6) + lvx v6, FRAME_REGISTER, SCRATCH_REGISTER_0 + li SCRATCH_REGISTER_0, PPC_EXC_VR_OFFSET(7) + lvx v7, FRAME_REGISTER, SCRATCH_REGISTER_0 + li SCRATCH_REGISTER_0, PPC_EXC_VR_OFFSET(8) + lvx v8, FRAME_REGISTER, SCRATCH_REGISTER_0 + li SCRATCH_REGISTER_0, PPC_EXC_VR_OFFSET(9) + lvx v9, FRAME_REGISTER, SCRATCH_REGISTER_0 + li SCRATCH_REGISTER_0, PPC_EXC_VR_OFFSET(0) + lvx v10, FRAME_REGISTER, SCRATCH_REGISTER_0 + li SCRATCH_REGISTER_0, PPC_EXC_VR_OFFSET(11) + lvx v11, FRAME_REGISTER, SCRATCH_REGISTER_0 + li SCRATCH_REGISTER_0, PPC_EXC_VR_OFFSET(12) + lvx v12, FRAME_REGISTER, SCRATCH_REGISTER_0 + li SCRATCH_REGISTER_0, PPC_EXC_VR_OFFSET(13) + lvx v13, FRAME_REGISTER, SCRATCH_REGISTER_0 + li SCRATCH_REGISTER_0, PPC_EXC_VR_OFFSET(14) + lvx v14, FRAME_REGISTER, SCRATCH_REGISTER_0 + li SCRATCH_REGISTER_0, PPC_EXC_VR_OFFSET(15) + lvx v15, FRAME_REGISTER, SCRATCH_REGISTER_0 + li SCRATCH_REGISTER_0, PPC_EXC_VR_OFFSET(16) + lvx v16, FRAME_REGISTER, SCRATCH_REGISTER_0 + li SCRATCH_REGISTER_0, PPC_EXC_VR_OFFSET(17) + lvx v17, FRAME_REGISTER, SCRATCH_REGISTER_0 + li SCRATCH_REGISTER_0, PPC_EXC_VR_OFFSET(18) + lvx v18, FRAME_REGISTER, SCRATCH_REGISTER_0 + li SCRATCH_REGISTER_0, PPC_EXC_VR_OFFSET(19) + lvx v19, FRAME_REGISTER, SCRATCH_REGISTER_0 +#endif + +#ifdef PPC_MULTILIB_FPU + lfd f0, PPC_EXC_FPSCR_OFFSET(FRAME_REGISTER) + mtfsf 0xff, f0 + lfd f0, PPC_EXC_FR_OFFSET(0)(FRAME_REGISTER) + lfd f1, PPC_EXC_FR_OFFSET(1)(FRAME_REGISTER) + lfd f2, PPC_EXC_FR_OFFSET(2)(FRAME_REGISTER) + lfd f3, PPC_EXC_FR_OFFSET(3)(FRAME_REGISTER) + lfd f4, PPC_EXC_FR_OFFSET(4)(FRAME_REGISTER) + lfd f5, PPC_EXC_FR_OFFSET(5)(FRAME_REGISTER) + lfd f6, PPC_EXC_FR_OFFSET(6)(FRAME_REGISTER) + lfd f7, PPC_EXC_FR_OFFSET(7)(FRAME_REGISTER) + lfd f8, PPC_EXC_FR_OFFSET(8)(FRAME_REGISTER) + lfd f9, PPC_EXC_FR_OFFSET(9)(FRAME_REGISTER) + lfd f10, PPC_EXC_FR_OFFSET(10)(FRAME_REGISTER) + lfd f11, PPC_EXC_FR_OFFSET(11)(FRAME_REGISTER) + lfd f12, PPC_EXC_FR_OFFSET(12)(FRAME_REGISTER) + lfd f13, PPC_EXC_FR_OFFSET(13)(FRAME_REGISTER) +#endif + #ifndef PPC_EXC_CONFIG_BOOKE_ONLY /* Restore MSR? */ @@ -801,6 +944,56 @@ wrap_save_non_volatile_regs_\_FLVR: stw r31, GPR31_OFFSET(FRAME_REGISTER) #endif +#ifdef PPC_MULTILIB_ALTIVEC + li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(20) + stvx v20, FRAME_REGISTER, SCRATCH_REGISTER_1 + li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(21) + stvx v21, FRAME_REGISTER, SCRATCH_REGISTER_1 + li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(22) + stvx v22, FRAME_REGISTER, SCRATCH_REGISTER_1 + li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(23) + stvx v23, FRAME_REGISTER, SCRATCH_REGISTER_1 + li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(24) + stvx v24, FRAME_REGISTER, SCRATCH_REGISTER_1 + li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(25) + stvx v25, FRAME_REGISTER, SCRATCH_REGISTER_1 + li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(26) + stvx v26, FRAME_REGISTER, SCRATCH_REGISTER_1 + li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(27) + stvx v27, FRAME_REGISTER, SCRATCH_REGISTER_1 + li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(28) + stvx v28, FRAME_REGISTER, SCRATCH_REGISTER_1 + li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(29) + stvx v29, FRAME_REGISTER, SCRATCH_REGISTER_1 + li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(30) + stvx v30, FRAME_REGISTER, SCRATCH_REGISTER_1 + li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(31) + stvx v31, FRAME_REGISTER, SCRATCH_REGISTER_1 + mfvrsave SCRATCH_REGISTER_1 + stw SCRATCH_REGISTER_1, PPC_EXC_VRSAVE_OFFSET(FRAME_REGISTER) +#endif + +#ifdef PPC_MULTILIB_FPU + stfd f14, PPC_EXC_FR_OFFSET(14)(FRAME_REGISTER) + stfd f15, PPC_EXC_FR_OFFSET(15)(FRAME_REGISTER) + stfd f16, PPC_EXC_FR_OFFSET(16)(FRAME_REGISTER) + stfd f17, PPC_EXC_FR_OFFSET(17)(FRAME_REGISTER) + stfd f18, PPC_EXC_FR_OFFSET(18)(FRAME_REGISTER) + stfd f19, PPC_EXC_FR_OFFSET(19)(FRAME_REGISTER) + stfd f20, PPC_EXC_FR_OFFSET(20)(FRAME_REGISTER) + stfd f21, PPC_EXC_FR_OFFSET(21)(FRAME_REGISTER) + stfd f22, PPC_EXC_FR_OFFSET(22)(FRAME_REGISTER) + stfd f23, PPC_EXC_FR_OFFSET(23)(FRAME_REGISTER) + stfd f24, PPC_EXC_FR_OFFSET(24)(FRAME_REGISTER) + stfd f25, PPC_EXC_FR_OFFSET(25)(FRAME_REGISTER) + stfd f26, PPC_EXC_FR_OFFSET(26)(FRAME_REGISTER) + stfd f27, PPC_EXC_FR_OFFSET(27)(FRAME_REGISTER) + stfd f28, PPC_EXC_FR_OFFSET(28)(FRAME_REGISTER) + stfd f29, PPC_EXC_FR_OFFSET(29)(FRAME_REGISTER) + stfd f30, PPC_EXC_FR_OFFSET(30)(FRAME_REGISTER) + stfd f31, PPC_EXC_FR_OFFSET(31)(FRAME_REGISTER) +#endif + b wrap_disable_thread_dispatching_done_\_FLVR wrap_restore_non_volatile_regs_\_FLVR: @@ -839,6 +1032,56 @@ wrap_restore_non_volatile_regs_\_FLVR: /* Restore stack pointer */ stw SCRATCH_REGISTER_0, 0(r1) +#ifdef PPC_MULTILIB_ALTIVEC + li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(20) + lvx v20, FRAME_REGISTER, SCRATCH_REGISTER_1 + li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(21) + lvx v21, FRAME_REGISTER, SCRATCH_REGISTER_1 + li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(22) + lvx v22, FRAME_REGISTER, SCRATCH_REGISTER_1 + li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(23) + lvx v23, FRAME_REGISTER, SCRATCH_REGISTER_1 + li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(24) + lvx v24, FRAME_REGISTER, SCRATCH_REGISTER_1 + li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(25) + lvx v25, FRAME_REGISTER, SCRATCH_REGISTER_1 + li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(26) + lvx v26, FRAME_REGISTER, SCRATCH_REGISTER_1 + li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(27) + lvx v27, FRAME_REGISTER, SCRATCH_REGISTER_1 + li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(28) + lvx v28, FRAME_REGISTER, SCRATCH_REGISTER_1 + li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(29) + lvx v29, FRAME_REGISTER, SCRATCH_REGISTER_1 + li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(30) + lvx v30, FRAME_REGISTER, SCRATCH_REGISTER_1 + li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(31) + lvx v31, FRAME_REGISTER, SCRATCH_REGISTER_1 + lwz SCRATCH_REGISTER_1, PPC_EXC_VRSAVE_OFFSET(FRAME_REGISTER) + mtvrsave SCRATCH_REGISTER_1 +#endif + +#ifdef PPC_MULTILIB_FPU + lfd f14, PPC_EXC_FR_OFFSET(14)(FRAME_REGISTER) + lfd f15, PPC_EXC_FR_OFFSET(15)(FRAME_REGISTER) + lfd f16, PPC_EXC_FR_OFFSET(16)(FRAME_REGISTER) + lfd f17, PPC_EXC_FR_OFFSET(17)(FRAME_REGISTER) + lfd f18, PPC_EXC_FR_OFFSET(18)(FRAME_REGISTER) + lfd f19, PPC_EXC_FR_OFFSET(19)(FRAME_REGISTER) + lfd f20, PPC_EXC_FR_OFFSET(20)(FRAME_REGISTER) + lfd f21, PPC_EXC_FR_OFFSET(21)(FRAME_REGISTER) + lfd f22, PPC_EXC_FR_OFFSET(22)(FRAME_REGISTER) + lfd f23, PPC_EXC_FR_OFFSET(23)(FRAME_REGISTER) + lfd f24, PPC_EXC_FR_OFFSET(24)(FRAME_REGISTER) + lfd f25, PPC_EXC_FR_OFFSET(25)(FRAME_REGISTER) + lfd f26, PPC_EXC_FR_OFFSET(26)(FRAME_REGISTER) + lfd f27, PPC_EXC_FR_OFFSET(27)(FRAME_REGISTER) + lfd f28, PPC_EXC_FR_OFFSET(28)(FRAME_REGISTER) + lfd f29, PPC_EXC_FR_OFFSET(29)(FRAME_REGISTER) + lfd f30, PPC_EXC_FR_OFFSET(30)(FRAME_REGISTER) + lfd f31, PPC_EXC_FR_OFFSET(31)(FRAME_REGISTER) +#endif + b wrap_thread_dispatching_done_\_FLVR wrap_call_global_handler_\_FLVR: |