diff options
Diffstat (limited to 'c/src/lib/libbsp/sparc/shared/pci/gr_rasta_tmtc.c')
| -rw-r--r-- | c/src/lib/libbsp/sparc/shared/pci/gr_rasta_tmtc.c | 68 |
1 files changed, 51 insertions, 17 deletions
diff --git a/c/src/lib/libbsp/sparc/shared/pci/gr_rasta_tmtc.c b/c/src/lib/libbsp/sparc/shared/pci/gr_rasta_tmtc.c index c8ba4c4962..6ca3c6be1a 100644 --- a/c/src/lib/libbsp/sparc/shared/pci/gr_rasta_tmtc.c +++ b/c/src/lib/libbsp/sparc/shared/pci/gr_rasta_tmtc.c @@ -23,6 +23,7 @@ #include <bsp.h> #include <rtems/bspIo.h> +#include <rtems/score/isrlock.h> /* spin-lock */ #include <pci.h> #include <ambapp.h> @@ -35,6 +36,16 @@ #include <bsp/gr_rasta_tmtc.h> +/* map via rtems_interrupt_lock_* API: */ +#define SPIN_DECLARE(lock) RTEMS_INTERRUPT_LOCK_MEMBER(lock) +#define SPIN_INIT(lock, name) rtems_interrupt_lock_initialize(lock, name) +#define SPIN_LOCK(lock, level) rtems_interrupt_lock_acquire_isr(lock, &level) +#define SPIN_LOCK_IRQ(lock, level) rtems_interrupt_lock_acquire(lock, &level) +#define SPIN_UNLOCK(lock, level) rtems_interrupt_lock_release_isr(lock, &level) +#define SPIN_UNLOCK_IRQ(lock, level) rtems_interrupt_lock_release(lock, &level) +#define SPIN_IRQFLAGS(k) rtems_interrupt_lock_context k +#define SPIN_ISR_IRQFLAGS(k) SPIN_IRQFLAGS(k) + /* Determines which PCI address the AHB masters will access, it should be * set so that the masters can access the CPU RAM. Default is base of CPU RAM, * CPU RAM is mapped 1:1 to PCI space. @@ -104,8 +115,9 @@ struct gr_rasta_tmtc_ver { /* Private data structure for driver */ struct gr_rasta_tmtc_priv { /* Driver management */ - struct drvmgr_dev *dev; + struct drvmgr_dev *dev; char prefix[20]; + SPIN_DECLARE(devlock); /* PCI */ pci_dev_t pcidev; @@ -224,10 +236,13 @@ void gr_rasta_tmtc_isr (void *arg) struct gr_rasta_tmtc_priv *priv = arg; unsigned int status, tmp; int irq; + SPIN_ISR_IRQFLAGS(irqflags); + tmp = status = priv->irq->ipend; /* printk("GR-RASTA-TMTC: IRQ 0x%x\n",status); */ + SPIN_LOCK(&priv->devlock, irqflags); for(irq=0; irq<32; irq++) { if ( status & (1<<irq) ) { genirq_doirq(priv->genirq, irq); @@ -237,6 +252,7 @@ void gr_rasta_tmtc_isr (void *arg) break; } } + SPIN_UNLOCK(&priv->devlock, irqflags); /* ACK interrupt, this is because PCI is Level, so the IRQ Controller still drives the IRQ. */ if ( tmp ) @@ -602,6 +618,12 @@ int gr_rasta_tmtc_init1(struct drvmgr_dev *dev) if ((bar0_size == 0) || (bar1_size == 0)) return DRVMGR_ENORES; + /* Initialize spin-lock for this PCI peripheral device. This is to + * protect the Interrupt Controller Registers. The genirq layer is + * protecting its own internals and ISR dispatching. + */ + SPIN_INIT(&priv->devlock, priv->prefix); + /* Let user override which PCI address the AHB masters of the * GR-RASTA-TMTC board access when doing DMA to CPU RAM. The AHB masters * access the PCI Window of the AMBA bus, the MSB 4-bits of that address @@ -689,12 +711,17 @@ int ambapp_rasta_tmtc_int_register( void *arg) { struct gr_rasta_tmtc_priv *priv = dev->parent->dev->priv; - rtems_interrupt_level level; + SPIN_IRQFLAGS(irqflags); int status; + void *h; - rtems_interrupt_disable(level); + h = genirq_alloc_handler(handler, arg); + if ( h == NULL ) + return DRVMGR_FAIL; - status = genirq_register(priv->genirq, irq, handler, arg); + SPIN_LOCK_IRQ(&priv->devlock, irqflags); + + status = genirq_register(priv->genirq, irq, h); if ( status == 0 ) { /* Disable and clear IRQ for first registered handler */ priv->irq->iclear = (1<<irq); @@ -702,7 +729,8 @@ int ambapp_rasta_tmtc_int_register( status = 0; if (status != 0) { - rtems_interrupt_enable(level); + SPIN_UNLOCK_IRQ(&priv->devlock, irqflags); + genirq_free_handler(h); return DRVMGR_FAIL; } @@ -713,7 +741,7 @@ int ambapp_rasta_tmtc_int_register( } else if ( status == 1 ) status = 0; - rtems_interrupt_enable(level); + SPIN_UNLOCK_IRQ(&priv->devlock, irqflags); return status; } @@ -725,10 +753,11 @@ int ambapp_rasta_tmtc_int_unregister( void *arg) { struct gr_rasta_tmtc_priv *priv = dev->parent->dev->priv; - rtems_interrupt_level level; + SPIN_IRQFLAGS(irqflags); int status; + void *handler; - rtems_interrupt_disable(level); + SPIN_LOCK_IRQ(&priv->devlock, irqflags); status = genirq_disable(priv->genirq, irq, isr, arg); if ( status == 0 ) { @@ -737,11 +766,16 @@ int ambapp_rasta_tmtc_int_unregister( } else if ( status == 1 ) status = 0; - status = genirq_unregister(priv->genirq, irq, isr, arg); - if ( status != 0 ) + handler = genirq_unregister(priv->genirq, irq, isr, arg); + if ( handler == NULL ) status = DRVMGR_FAIL; + else + status = DRVMGR_OK; + + SPIN_UNLOCK_IRQ(&priv->devlock, irqflags); - rtems_interrupt_enable(level); + if (handler) + genirq_free_handler(handler); return status; } @@ -751,19 +785,19 @@ int ambapp_rasta_tmtc_int_unmask( int irq) { struct gr_rasta_tmtc_priv *priv = dev->parent->dev->priv; - rtems_interrupt_level level; + SPIN_IRQFLAGS(irqflags); DBG("RASTA-TMTC IRQ %d: unmask\n", irq); if ( genirq_check(priv->genirq, irq) ) return DRVMGR_EINVAL; - rtems_interrupt_disable(level); + SPIN_LOCK_IRQ(&priv->devlock, irqflags); /* Enable IRQ */ priv->irq->mask[0] |= (1<<irq); /* unmask interrupt source */ - rtems_interrupt_enable(level); + SPIN_UNLOCK_IRQ(&priv->devlock, irqflags); return DRVMGR_OK; } @@ -773,19 +807,19 @@ int ambapp_rasta_tmtc_int_mask( int irq) { struct gr_rasta_tmtc_priv *priv = dev->parent->dev->priv; - rtems_interrupt_level level; + SPIN_IRQFLAGS(irqflags); DBG("RASTA-TMTC IRQ %d: mask\n", irq); if ( genirq_check(priv->genirq, irq) ) return DRVMGR_EINVAL; - rtems_interrupt_disable(level); + SPIN_LOCK_IRQ(&priv->devlock, irqflags); /* Disable IRQ */ priv->irq->mask[0] &= ~(1<<irq); /* mask interrupt source */ - rtems_interrupt_enable(level); + SPIN_UNLOCK_IRQ(&priv->devlock, irqflags); return DRVMGR_OK; } |