1 files changed, 12 insertions, 106 deletions
diff --git a/c/src/lib/libbsp/m68k/av5282/startup/bspstart.c b/c/src/lib/libbsp/m68k/av5282/startup/bspstart.c
index e85ea4c53b..c2dd362a6d 100644
--- a/c/src/lib/libbsp/m68k/av5282/startup/bspstart.c
+++ b/c/src/lib/libbsp/m68k/av5282/startup/bspstart.c
@@ -27,106 +27,6 @@
 #define FLASH_BASE      0xFF800000
 #define FLASH_SIZE      (8*1024*1024)
 
-/*
- * CPU-space access
- */
-#define m68k_set_acr0(_acr0) __asm__ volatile ("movec %0,%%acr0" : : "d" (_acr0))
-#define m68k_set_acr1(_acr1) __asm__ volatile ("movec %0,%%acr1" : : "d" (_acr1))
-
-/*
- * Read/write copy of common cache
- *   Split I/D cache
- *   Allow CPUSHL to invalidate a cache line
- *   Enable buffered writes
- *   No burst transfers on non-cacheable accesses
- *   Default cache mode is *disabled* (cache only ACRx areas)
- */
-static uint32_t cacr_mode = MCF5XXX_CACR_CENB |
-                              MCF5XXX_CACR_DBWE |
-                              MCF5XXX_CACR_DCM;
-/*
- * Cannot be frozen
- */
-void _CPU_cache_freeze_data(void) {}
-void _CPU_cache_unfreeze_data(void) {}
-void _CPU_cache_freeze_instruction(void) {}
-void _CPU_cache_unfreeze_instruction(void) {}
-
-/*
- * Write-through data cache -- flushes are unnecessary
- */
-void _CPU_cache_flush_1_data_line(const void *d_addr) {}
-void _CPU_cache_flush_entire_data(void) {}
-
-void _CPU_cache_enable_instruction(void)
-{
-    rtems_interrupt_level level;
-
-    rtems_interrupt_disable(level);
-    cacr_mode &= ~MCF5XXX_CACR_DIDI;
-    m68k_set_cacr(cacr_mode);
-    rtems_interrupt_enable(level);
-}
-
-void _CPU_cache_disable_instruction(void)
-{
-    rtems_interrupt_level level;
-
-    rtems_interrupt_disable(level);
-    cacr_mode |= MCF5XXX_CACR_DIDI;
-    m68k_set_cacr(cacr_mode);
-    rtems_interrupt_enable(level);
-}
-
-void _CPU_cache_invalidate_entire_instruction(void)
-{
-    m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI);
-}
-
-void _CPU_cache_invalidate_1_instruction_line(const void *addr)
-{
-    /*
-     * Top half of cache is I-space
-     */
-    addr = (void *)((int)addr | 0x400);
-    __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (addr));
-}
-
-void _CPU_cache_enable_data(void)
-{
-    rtems_interrupt_level level;
-
-    rtems_interrupt_disable(level);
-    cacr_mode &= ~MCF5XXX_CACR_DISD;
-    m68k_set_cacr(cacr_mode);
-    rtems_interrupt_enable(level);
-}
-
-void _CPU_cache_disable_data(void)
-{
-    rtems_interrupt_level level;
-
-    rtems_interrupt_disable(level);
-    rtems_interrupt_disable(level);
-    cacr_mode |= MCF5XXX_CACR_DISD;
-    m68k_set_cacr(cacr_mode);
-    rtems_interrupt_enable(level);
-}
-
-void _CPU_cache_invalidate_entire_data(void)
-{
-    m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD);
-}
-
-void _CPU_cache_invalidate_1_data_line(const void *addr)
-{
-    /*
-     * Bottom half of cache is D-space
-     */
-    addr = (void *)((int)addr & ~0x400);
-    __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (addr));
-}
-
 void bsp_start( void )
 {
   /*
@@ -139,16 +39,22 @@ void bsp_start( void )
   /*
    * Cache SDRAM and FLASH
    */
-  m68k_set_acr0(MCF5XXX_ACR_AB(SDRAM_BASE)    |
-                MCF5XXX_ACR_AM(SDRAM_SIZE-1)  |
-                MCF5XXX_ACR_EN                |
-                MCF5XXX_ACR_BWE               |
-                MCF5XXX_ACR_SM_IGNORE);
+  m68k_set_acr0(
+    MCF5XXX_ACR_AB(SDRAM_BASE)    |
+    MCF5XXX_ACR_AM(SDRAM_SIZE-1)  |
+    MCF5XXX_ACR_EN                |
+    MCF5XXX_ACR_BWE               |
+    MCF5XXX_ACR_SM_IGNORE
+  );
 
   /*
    * Enable the cache
    */
-  m68k_set_cacr(cacr_mode);
+  mcf5xxx_initialize_cacr(
+    MCF5XXX_CACR_CENB |
+    MCF5XXX_CACR_DBWE |
+    MCF5XXX_CACR_DCM
+  );
 }
 
 extern char _CPUClockSpeed[];