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Diffstat (limited to 'c/src/lib/libbsp/arm/stm32f4/include')
-rw-r--r--c/src/lib/libbsp/arm/stm32f4/include/io.h114
-rw-r--r--c/src/lib/libbsp/arm/stm32f4/include/rcc.h103
-rw-r--r--c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h93
3 files changed, 263 insertions, 47 deletions
diff --git a/c/src/lib/libbsp/arm/stm32f4/include/io.h b/c/src/lib/libbsp/arm/stm32f4/include/io.h
new file mode 100644
index 0000000000..539bba567e
--- /dev/null
+++ b/c/src/lib/libbsp/arm/stm32f4/include/io.h
@@ -0,0 +1,114 @@
+/*
+ * Copyright (c) 2012 Sebastian Huber. All rights reserved.
+ *
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * 82178 Puchheim
+ * Germany
+ * <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_STM32F4_IO_H
+#define LIBBSP_ARM_STM32F4_IO_H
+
+#include <stdbool.h>
+
+#include <bsp/stm32f4.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+typedef enum {
+ STM32F4_GPIO_MODE_INPUT,
+ STM32F4_GPIO_MODE_OUTPUT,
+ STM32F4_GPIO_MODE_AF,
+ STM32F4_GPIO_MODE_ANALOG
+} stm32f4_gpio_mode;
+
+typedef enum {
+ STM32F4_GPIO_OTYPE_PUSH_PULL,
+ STM32F4_GPIO_OTYPE_OPEN_DRAIN
+} stm32f4_gpio_otype;
+
+typedef enum {
+ STM32F4_GPIO_OSPEED_2_MHZ,
+ STM32F4_GPIO_OSPEED_25_MHZ,
+ STM32F4_GPIO_OSPEED_50_MHZ,
+ STM32F4_GPIO_OSPEED_100_MHZ
+} stm32f4_gpio_ospeed;
+
+typedef enum {
+ STM32F4_GPIO_NO_PULL,
+ STM32F4_GPIO_PULL_UP,
+ STM32F4_GPIO_PULL_DOWN
+} stm32f4_gpio_pull;
+
+typedef enum {
+ STM32F4_GPIO_AF_SYSTEM = 0,
+ STM32F4_GPIO_AF_TIM1 = 1,
+ STM32F4_GPIO_AF_TIM2 = 1,
+ STM32F4_GPIO_AF_TIM3 = 2,
+ STM32F4_GPIO_AF_TIM4 = 2,
+ STM32F4_GPIO_AF_TIM5 = 2,
+ STM32F4_GPIO_AF_TIM8 = 3,
+ STM32F4_GPIO_AF_TIM9 = 3,
+ STM32F4_GPIO_AF_TIM10 = 3,
+ STM32F4_GPIO_AF_TIM11 = 3,
+ STM32F4_GPIO_AF_I2C1 = 4,
+ STM32F4_GPIO_AF_I2C2 = 4,
+ STM32F4_GPIO_AF_I2C3 = 4,
+ STM32F4_GPIO_AF_SPI1 = 5,
+ STM32F4_GPIO_AF_SPI2 = 5,
+ STM32F4_GPIO_AF_SPI3 = 6,
+ STM32F4_GPIO_AF_USART1 = 7,
+ STM32F4_GPIO_AF_USART2 = 7,
+ STM32F4_GPIO_AF_USART3 = 7,
+ STM32F4_GPIO_AF_UART4 = 8,
+ STM32F4_GPIO_AF_UART5 = 8,
+ STM32F4_GPIO_AF_USART6 = 8,
+ STM32F4_GPIO_AF_CAN1 = 9,
+ STM32F4_GPIO_AF_CAN2 = 9,
+ STM32F4_GPIO_AF_TIM12 = 9,
+ STM32F4_GPIO_AF_TIM13 = 9,
+ STM32F4_GPIO_AF_TIM14 = 9,
+ STM32F4_GPIO_AF_OTG_FS = 10,
+ STM32F4_GPIO_AF_OTG_HS = 10,
+ STM32F4_GPIO_AF_ETH = 11,
+ STM32F4_GPIO_AF_FSMC = 12,
+ STM32F4_GPIO_AF_OTG_HS_FS = 12,
+ STM32F4_GPIO_AF_SDIO = 12,
+ STM32F4_GPIO_AF_DCMI = 13,
+ STM32F4_GPIO_AF_EVENTOUT = 15
+} stm32f4_gpio_af;
+
+#define STM32F4_GPIO_PIN(port, index) ((((port) << 4) | (index)) & 0xff)
+
+#define STM32F4_GPIO_PORT_OF_PIN(pin) (((pin) >> 4) & 0xf)
+
+#define STM32F4_GPIO_INDEX_OF_PIN(pin) ((pin) & 0xf)
+
+typedef struct {
+ uint32_t pin : 8;
+ uint32_t mode : 2;
+ uint32_t otype : 1;
+ uint32_t ospeed : 2;
+ uint32_t pupd : 2;
+ uint32_t af : 4;
+} stm32f4_gpio_config;
+
+void stm32f4_gpio_set_config(const stm32f4_gpio_config *config);
+
+void stm32f4_gpio_set_output(int pin, bool set);
+
+bool stm32f4_gpio_get_input(int pin);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_ARM_STM32F4_IO_H */
diff --git a/c/src/lib/libbsp/arm/stm32f4/include/rcc.h b/c/src/lib/libbsp/arm/stm32f4/include/rcc.h
new file mode 100644
index 0000000000..e2e4d13c79
--- /dev/null
+++ b/c/src/lib/libbsp/arm/stm32f4/include/rcc.h
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2012 Sebastian Huber. All rights reserved.
+ *
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * 82178 Puchheim
+ * Germany
+ * <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_STM32F4_RCC_H
+#define LIBBSP_ARM_STM32F4_RCC_H
+
+#include <stdbool.h>
+
+#include <bsp/stm32f4.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#define STM32F4_RCC_INDEX(reg, idx) (((reg) << 5) | (idx))
+
+typedef enum {
+ STM32F4_RCC_OTGHS = STM32F4_RCC_INDEX(0, 29),
+ STM32F4_RCC_ETHMAC = STM32F4_RCC_INDEX(0, 25),
+ STM32F4_RCC_DMA2 = STM32F4_RCC_INDEX(0, 22),
+ STM32F4_RCC_DMA1 = STM32F4_RCC_INDEX(0, 21),
+ STM32F4_RCC_CRC = STM32F4_RCC_INDEX(0, 12),
+ STM32F4_RCC_GPIOI = STM32F4_RCC_INDEX(0, 8),
+ STM32F4_RCC_GPIOH = STM32F4_RCC_INDEX(0, 7),
+ STM32F4_RCC_GPIOG = STM32F4_RCC_INDEX(0, 6),
+ STM32F4_RCC_GPIOF = STM32F4_RCC_INDEX(0, 5),
+ STM32F4_RCC_GPIOE = STM32F4_RCC_INDEX(0, 4),
+ STM32F4_RCC_GPIOD = STM32F4_RCC_INDEX(0, 3),
+ STM32F4_RCC_GPIOC = STM32F4_RCC_INDEX(0, 2),
+ STM32F4_RCC_GPIOB = STM32F4_RCC_INDEX(0, 1),
+ STM32F4_RCC_GPIOA = STM32F4_RCC_INDEX(0, 0),
+
+ STM32F4_RCC_OTGFS = STM32F4_RCC_INDEX(1, 7),
+ STM32F4_RCC_RNG = STM32F4_RCC_INDEX(1, 6),
+ STM32F4_RCC_HASH = STM32F4_RCC_INDEX(1, 5),
+ STM32F4_RCC_CRYP = STM32F4_RCC_INDEX(1, 4),
+ STM32F4_RCC_DCMI = STM32F4_RCC_INDEX(1, 0),
+
+ STM32F4_RCC_FSMCR = STM32F4_RCC_INDEX(2, 0),
+
+ STM32F4_RCC_DAC = STM32F4_RCC_INDEX(4, 29),
+ STM32F4_RCC_PWR = STM32F4_RCC_INDEX(4, 28),
+ STM32F4_RCC_CAN2 = STM32F4_RCC_INDEX(4, 26),
+ STM32F4_RCC_CAN1 = STM32F4_RCC_INDEX(4, 25),
+ STM32F4_RCC_I2C3 = STM32F4_RCC_INDEX(4, 23),
+ STM32F4_RCC_I2C2 = STM32F4_RCC_INDEX(4, 22),
+ STM32F4_RCC_I2C1 = STM32F4_RCC_INDEX(4, 21),
+ STM32F4_RCC_UART5 = STM32F4_RCC_INDEX(4, 20),
+ STM32F4_RCC_UART4 = STM32F4_RCC_INDEX(4, 19),
+ STM32F4_RCC_USART3 = STM32F4_RCC_INDEX(4, 18),
+ STM32F4_RCC_USART2 = STM32F4_RCC_INDEX(4, 17),
+ STM32F4_RCC_SPI3 = STM32F4_RCC_INDEX(4, 15),
+ STM32F4_RCC_SPI2 = STM32F4_RCC_INDEX(4, 14),
+ STM32F4_RCC_WWDG = STM32F4_RCC_INDEX(4, 11),
+ STM32F4_RCC_TIM14 = STM32F4_RCC_INDEX(4, 8),
+ STM32F4_RCC_TIM13 = STM32F4_RCC_INDEX(4, 7),
+ STM32F4_RCC_TIM12 = STM32F4_RCC_INDEX(4, 6),
+ STM32F4_RCC_TIM7 = STM32F4_RCC_INDEX(4, 5),
+ STM32F4_RCC_TIM6 = STM32F4_RCC_INDEX(4, 4),
+ STM32F4_RCC_TIM5 = STM32F4_RCC_INDEX(4, 3),
+ STM32F4_RCC_TIM4 = STM32F4_RCC_INDEX(4, 2),
+ STM32F4_RCC_TIM3 = STM32F4_RCC_INDEX(4, 1),
+ STM32F4_RCC_TIM2 = STM32F4_RCC_INDEX(4, 0),
+
+ STM32F4_RCC_TIM11 = STM32F4_RCC_INDEX(5, 18),
+ STM32F4_RCC_TIM10 = STM32F4_RCC_INDEX(5, 17),
+ STM32F4_RCC_TIM9 = STM32F4_RCC_INDEX(5, 16),
+ STM32F4_RCC_SYSCFG = STM32F4_RCC_INDEX(5, 14),
+ STM32F4_RCC_SPI1 = STM32F4_RCC_INDEX(5, 12),
+ STM32F4_RCC_SDIO = STM32F4_RCC_INDEX(5, 11),
+ STM32F4_RCC_ADC3 = STM32F4_RCC_INDEX(5, 10),
+ STM32F4_RCC_ADC2 = STM32F4_RCC_INDEX(5, 9),
+ STM32F4_RCC_ADC1 = STM32F4_RCC_INDEX(5, 8),
+ STM32F4_RCC_USART6 = STM32F4_RCC_INDEX(5, 5),
+ STM32F4_RCC_USART1 = STM32F4_RCC_INDEX(5, 4),
+ STM32F4_RCC_TIM8 = STM32F4_RCC_INDEX(5, 1),
+ STM32F4_RCC_TIM1 = STM32F4_RCC_INDEX(5, 0),
+} stm32f4_rcc_index;
+
+void stm32f4_rcc_reset(stm32f4_rcc_index index, bool set);
+
+void stm32f4_rcc_set_clock(stm32f4_rcc_index index, bool set);
+
+void stm32f4_rcc_set_gpio_clock(int pin, bool set);
+
+void stm32f4_rcc_set_low_power_clock(stm32f4_rcc_index index, bool set);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_ARM_STM32F4_RCC_H */
diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h
index 683012b08a..b07933f16b 100644
--- a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h
+++ b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h
@@ -20,48 +20,45 @@
#define STM32F4_BASE 0x00
typedef struct {
- uint32_t reserved_00 [16];
- uint32_t apb1enr;
-#define STM32F4_RCC_APB1ENR_DAC_EN BSP_BIT32(29)
-#define STM32F4_RCC_APB1ENR_PWR_EN BSP_BIT32(28)
-#define STM32F4_RCC_APB1ENR_CAN2_EN BSP_BIT32(26)
-#define STM32F4_RCC_APB1ENR_CAN1_EN BSP_BIT32(25)
-#define STM32F4_RCC_APB1ENR_I2C3_EN BSP_BIT32(23)
-#define STM32F4_RCC_APB1ENR_I2C2_EN BSP_BIT32(22)
-#define STM32F4_RCC_APB1ENR_I2C1_EN BSP_BIT32(21)
-#define STM32F4_RCC_APB1ENR_UART5_EN BSP_BIT32(20)
-#define STM32F4_RCC_APB1ENR_UART4_EN BSP_BIT32(19)
-#define STM32F4_RCC_APB1ENR_USART3_EN BSP_BIT32(18)
-#define STM32F4_RCC_APB1ENR_USART2_EN BSP_BIT32(17)
-#define STM32F4_RCC_APB1ENR_SPI3_EN BSP_BIT32(15)
-#define STM32F4_RCC_APB1ENR_SPI2_EN BSP_BIT32(14)
-#define STM32F4_RCC_APB1ENR_WWDG_EN BSP_BIT32(11)
-#define STM32F4_RCC_APB1ENR_TIM14_EN BSP_BIT32(8)
-#define STM32F4_RCC_APB1ENR_TIM13_EN BSP_BIT32(7)
-#define STM32F4_RCC_APB1ENR_TIM12_EN BSP_BIT32(6)
-#define STM32F4_RCC_APB1ENR_TIM7_EN BSP_BIT32(5)
-#define STM32F4_RCC_APB1ENR_TIM6_EN BSP_BIT32(4)
-#define STM32F4_RCC_APB1ENR_TIM5_EN BSP_BIT32(3)
-#define STM32F4_RCC_APB1ENR_TIM4_EN BSP_BIT32(2)
-#define STM32F4_RCC_APB1ENR_TIM3_EN BSP_BIT32(1)
-#define STM32F4_RCC_APB1ENR_TIM2_EN BSP_BIT32(0)
- uint32_t apb2enr;
-#define STM32F4_RCC_APB2ENR_TIM11 BSP_BIT32(18)
-#define STM32F4_RCC_APB2ENR_TIM10_EN BSP_BIT32(17)
-#define STM32F4_RCC_APB2ENR_TIM9_EN BSP_BIT32(16)
-#define STM32F4_RCC_APB2ENR_SYSCFG_EN BSP_BIT32(14)
-#define STM32F4_RCC_APB2ENR_SPI1_EN BSP_BIT32(12)
-#define STM32F4_RCC_APB2ENR_SDIO_EN BSP_BIT32(11)
-#define STM32F4_RCC_APB2ENR_ADC3_EN BSP_BIT32(10)
-#define STM32F4_RCC_APB2ENR_ADC2_EN BSP_BIT32(9)
-#define STM32F4_RCC_APB2ENR_ADC1_EN BSP_BIT32(8)
-#define STM32F4_RCC_APB2ENR_USART6_EN BSP_BIT32(5)
-#define STM32F4_RCC_APB2ENR_USART1_EN BSP_BIT32(4)
-#define STM32F4_RCC_APB2ENR_TIM8_EN BSP_BIT32(1)
-#define STM32F4_RCC_APB2ENR_TIM1_EN BSP_BIT32(0)
+ uint32_t moder;
+ uint32_t otyper;
+ uint32_t ospeedr;
+ uint32_t pupdr;
+ uint32_t idr;
+ uint32_t odr;
+ uint32_t bsrr;
+ uint32_t lckr;
+ uint32_t afr [2];
+ uint32_t reserved_28 [246];
+} stm32f4_gpio;
+
+#define STM32F4_GPIO(i) ((volatile stm32f4_gpio *) (STM32F4_BASE + 0x40020000) + (i))
+
+typedef struct {
+ uint32_t cr;
+ uint32_t pllcfgr;
+ uint32_t cfgr;
+ uint32_t cir;
+ uint32_t ahbrstr [3];
+ uint32_t reserved_1c;
+ uint32_t apbrstr [2];
+ uint32_t reserved_28 [2];
+ uint32_t ahbenr [3];
+ uint32_t reserved_3c;
+ uint32_t apbenr [2];
+ uint32_t reserved_48 [2];
+ uint32_t ahblpenr [3];
+ uint32_t reserved_5c;
+ uint32_t apblpenr [2];
+ uint32_t reserved_68 [2];
+ uint32_t bdcr;
+ uint32_t csr;
+ uint32_t reserved_78 [2];
+ uint32_t sscgr;
+ uint32_t plli2scfgr;
} stm32f4_rcc;
-#define STM32F4_RCC (*(volatile stm32f4_rcc *) (STM32F4_BASE + 0x40023800))
+#define STM32F4_RCC ((volatile stm32f4_rcc *) (STM32F4_BASE + 0x40023800))
typedef struct {
uint32_t sr;
@@ -138,12 +135,12 @@ typedef struct {
#define STM32F4_USART_GTPR_PSC_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
} stm32f4_usart;
-#define STM32F4_USART_1 (*(volatile stm32f4_usart *) (STM32F4_BASE + 0x40011000))
-#define STM32F4_USART_2 (*(volatile stm32f4_usart *) (STM32F4_BASE + 0x40004400))
-#define STM32F4_USART_3 (*(volatile stm32f4_usart *) (STM32F4_BASE + 0x40004800))
-#define STM32F4_USART_4 (*(volatile stm32f4_usart *) (STM32F4_BASE + 0x40004c00))
-#define STM32F4_USART_5 (*(volatile stm32f4_usart *) (STM32F4_BASE + 0x40005000))
-#define STM32F4_USART_6 (*(volatile stm32f4_usart *) (STM32F4_BASE + 0x40011400))
+#define STM32F4_USART_1 ((volatile stm32f4_usart *) (STM32F4_BASE + 0x40011000))
+#define STM32F4_USART_2 ((volatile stm32f4_usart *) (STM32F4_BASE + 0x40004400))
+#define STM32F4_USART_3 ((volatile stm32f4_usart *) (STM32F4_BASE + 0x40004800))
+#define STM32F4_USART_4 ((volatile stm32f4_usart *) (STM32F4_BASE + 0x40004c00))
+#define STM32F4_USART_5 ((volatile stm32f4_usart *) (STM32F4_BASE + 0x40005000))
+#define STM32F4_USART_6 ((volatile stm32f4_usart *) (STM32F4_BASE + 0x40011400))
typedef struct {
uint32_t reserved_00 [268439808];
@@ -158,7 +155,9 @@ typedef struct {
stm32f4_usart usart_1;
uint32_t reserved_4001101c [249];
stm32f4_usart usart_6;
- uint32_t reserved_4001141c [18681];
+ uint32_t reserved_4001141c [15097];
+ stm32f4_gpio gpio [9];
+ uint32_t reserved_40022400 [1280];
stm32f4_rcc rcc;
} stm32f4;
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-10 03:50:12 +0000