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Diffstat (limited to 'c/src/lib/libbsp/arm/shared/include/arm-errata.h')
| -rw-r--r-- | c/src/lib/libbsp/arm/shared/include/arm-errata.h | 127 |
1 files changed, 127 insertions, 0 deletions
diff --git a/c/src/lib/libbsp/arm/shared/include/arm-errata.h b/c/src/lib/libbsp/arm/shared/include/arm-errata.h new file mode 100644 index 0000000000..6f26c1f708 --- /dev/null +++ b/c/src/lib/libbsp/arm/shared/include/arm-errata.h @@ -0,0 +1,127 @@ +/** + * @file arm-errata.h + * + * @ingroup arm_shared + * + * @brief Create #defines which state which erratas shall get applied + */ + +/* + * Copyright (c) 2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef ARM_ERRATA_H_ +#define ARM_ERRATA_H_ + +#include <bsp/arm-release-id.h> +#include <libcpu/arm-cp15.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#if defined( __ARM_ARCH_7A__ ) +static arm_release_id arm_errata_get_processor_release( + void +) +{ + const uint32_t MIDR = arm_cp15_get_id_code(); + const uint8_t REVISION = (MIDR & 0xF00000U) >> 20; + const uint8_t PATCH_LEVEL = (MIDR & 0xFU); + + return ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL( + REVISION, + PATCH_LEVEL + ); +} +#endif /* #if defined( __ARM_ARCH_7A__ ) */ + +#if defined( __ARM_ARCH_7A__ ) +static bool arm_errata_is_applicable_processor_errata_764369( + void +) +{ + const arm_release_id RELEASE = arm_errata_get_processor_release(); + bool is_applicable = false; + + /* Errata information for Cortex-A9 processors. + * Information taken from ARMs + * "Cortex-A series processors + * - Cortex-A9 + * - Software Developers Errata Notice + * - Revision r4 revisions + * - ARM Cortex-A9 processors r4 release Software Developers Errata Notice" + * The corresponding link is: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0360f/BABJFIBA.html + * Please see this document for more information on these erratas */ + + switch( RELEASE ) { + case ARM_RELEASE_ID_R4_P1: + case ARM_RELEASE_ID_R4_P4: + case ARM_RELEASE_ID_R3_P0: + case ARM_RELEASE_ID_R2_P10: + case ARM_RELEASE_ID_R2_P8: + case ARM_RELEASE_ID_R2_P6: + case ARM_RELEASE_ID_R2_P4: + case ARM_RELEASE_ID_R2_P3: + case ARM_RELEASE_ID_R2_P2: + case ARM_RELEASE_ID_R2_P0: + is_applicable = true; + default: + is_applicable = false; + break; + } + + return is_applicable; +} +#endif /* #if defined( __ARM_ARCH_7A__ ) */ + +#if defined( __ARM_ARCH_7A__ ) +static bool arm_errata_is_applicable_processor_errata_775420( + void +) +{ + const arm_release_id RELEASE = arm_errata_get_processor_release(); + bool is_applicable = false; + + /* Errata information for Cortex-A9 processors. + * Information taken from ARMs + * "Cortex-A series processors + * - Cortex-A9 + * - Software Developers Errata Notice + * - Revision r4 revisions + * - ARM Cortex-A9 processors r4 release Software Developers Errata Notice" + * The corresponding link is: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0360f/BABJFIBA.html + * Please see this document for more information on these erratas */ + + switch( RELEASE ) { + case ARM_RELEASE_ID_R2_P10: + case ARM_RELEASE_ID_R2_P8: + case ARM_RELEASE_ID_R2_P6: + case ARM_RELEASE_ID_R2_P4: + case ARM_RELEASE_ID_R2_P3: + case ARM_RELEASE_ID_R2_P2: + is_applicable = true; + default: + is_applicable = false; + break; + } + + return is_applicable; +} +#endif /* #if defined( __ARM_ARCH_7A__ ) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ARM_ERRATA_H_ */
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