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-rw-r--r--bsps/riscv/riscv/irq/irq.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/bsps/riscv/riscv/irq/irq.c b/bsps/riscv/riscv/irq/irq.c
index a369a81e62..ea33a3239c 100644
--- a/bsps/riscv/riscv/irq/irq.c
+++ b/bsps/riscv/riscv/irq/irq.c
@@ -84,7 +84,15 @@ void _RISCV_Interrupt_dispatch(uintptr_t mcause, Per_CPU_Control *cpu_self)
bsp_interrupt_handler_dispatch(
RISCV_INTERRUPT_VECTOR_EXTERNAL(interrupt_index)
);
+
plic_hart_regs->claim_complete = interrupt_index;
+
+ /*
+ * FIXME: It is not clear which fence is necessary here or if a fence is
+ * necessary at all. The goal is that the complete signal is somehow
+ * recognized by the PLIC before the next claim is issued.
+ */
+ __asm__ volatile ("fence o, i" : : : "memory");
}
} else if (mcause == (RISCV_INTERRUPT_SOFTWARE_MACHINE << 1)) {
#ifdef RTEMS_SMP