diff options
Diffstat (limited to 'bsps/powerpc/psim/start/bspstart.c')
-rw-r--r-- | bsps/powerpc/psim/start/bspstart.c | 113 |
1 files changed, 113 insertions, 0 deletions
diff --git a/bsps/powerpc/psim/start/bspstart.c b/bsps/powerpc/psim/start/bspstart.c new file mode 100644 index 0000000000..3a9809c022 --- /dev/null +++ b/bsps/powerpc/psim/start/bspstart.c @@ -0,0 +1,113 @@ +/* + * This set of routines starts the application. It includes application, + * board, and monitor specific initialization and configuration. + * The generic CPU dependent initialization has been performed + * before any of these are invoked. + * + * COPYRIGHT (c) 1989-2008. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#include <string.h> +#include <fcntl.h> +#include <bsp.h> +#include <bsp/irq.h> +#include <psim.h> +#include <bsp/bootcard.h> +#include <bsp/linker-symbols.h> +#include <rtems/bspIo.h> +#include <rtems/counter.h> +#include <rtems/powerpc/powerpc.h> + +#include <libcpu/cpuIdent.h> +#include <libcpu/bat.h> +#include <libcpu/spr.h> + +SPR_RW(SPRG1) + +/* On psim, each click of the decrementer register corresponds + * to 1 instruction. By setting this to 100, we are indicating + * that we are assuming it can execute 100 instructions per + * microsecond. This corresponds to sustaining 1 instruction + * per cycle at 100 Mhz. Whether this is a good guess or not + * is anyone's guess. + */ +extern int PSIM_INSTRUCTIONS_PER_MICROSECOND[]; + +/* + * PCI Bus Frequency + */ +unsigned int BSP_bus_frequency; + +/* + * Driver configuration parameters + */ +uint32_t bsp_clicks_per_usec; + +/* + * Memory on this board. + */ +uint32_t BSP_mem_size = (uint32_t)RamSize; + +/* + * Time base divisior (how many tick for 1 second). + */ +unsigned int BSP_time_base_divisor; + +extern unsigned long __rtems_end[]; + +/* + * bsp_start + * + * This routine does the bulk of the system initialization. + */ +void bsp_start( void ) +{ + /* + * Note we can not get CPU identification dynamically. + * PVR has to be set to PPC_PSIM (0xfffe) from the device + * file. + */ + + get_ppc_cpu_type(); + + /* + * initialize the device driver parameters + */ + BSP_bus_frequency = (unsigned int)PSIM_INSTRUCTIONS_PER_MICROSECOND; + bsp_clicks_per_usec = BSP_bus_frequency; + BSP_time_base_divisor = 1; + rtems_counter_initialize_converter(bsp_clicks_per_usec * 1000000); + + /* + * Initialize default raw exception handlers. + */ + ppc_exc_initialize_with_vector_base( + (uintptr_t) bsp_section_work_begin, + rtems_configuration_get_interrupt_stack_size(), + (void *) 0xfff00000 + ); + + /* + * Initalize RTEMS IRQ system + */ + BSP_rtems_irq_mng_init(0); + + /* + * Setup BATs and enable MMU + */ + /* Memory */ + setdbat(0, 0x0<<24, 0x0<<24, 2<<24, _PAGE_RW); + setibat(0, 0x0<<24, 0x0<<24, 2<<24, 0); + /* PCI */ + setdbat(1, 0x8<<24, 0x8<<24, 1<<24, IO_PAGE); + setdbat(2, 0xc<<24, 0xc<<24, 1<<24, IO_PAGE); + + _write_MSR(_read_MSR() | MSR_DR | MSR_IR); + __asm__ volatile("sync; isync"); + +} |