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-rw-r--r--bsps/bfin/TLL6527M/start/bsp_specs9
-rw-r--r--bsps/bfin/TLL6527M/start/bspstart.c152
-rw-r--r--bsps/bfin/TLL6527M/start/linkcmds176
3 files changed, 337 insertions, 0 deletions
diff --git a/bsps/bfin/TLL6527M/start/bsp_specs b/bsps/bfin/TLL6527M/start/bsp_specs
new file mode 100644
index 0000000000..87638cc027
--- /dev/null
+++ b/bsps/bfin/TLL6527M/start/bsp_specs
@@ -0,0 +1,9 @@
+%rename endfile old_endfile
+%rename startfile old_startfile
+
+*startfile:
+%{!qrtems: %(old_startfile)} \
+%{!nostdlib: %{qrtems: crti.o%s crtbegin.o%s}}
+
+*endfile:
+%{!qrtems: %(old_endfile)} %{qrtems: crtend.o%s crtn.o%s}
diff --git a/bsps/bfin/TLL6527M/start/bspstart.c b/bsps/bfin/TLL6527M/start/bspstart.c
new file mode 100644
index 0000000000..4c8302a7ba
--- /dev/null
+++ b/bsps/bfin/TLL6527M/start/bspstart.c
@@ -0,0 +1,152 @@
+/* bspstart.c for TLL6527M
+ *
+ * This routine does the bulk of the system initialization.
+ */
+
+/*
+ * COPYRIGHT (c) 2010 by ECE Northeastern University.
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license
+ */
+
+#include <bsp.h>
+#include <bsp/bootcard.h>
+#include <cplb.h>
+#include <bsp/interrupt.h>
+#include <libcpu/ebiuRegs.h>
+#include <rtems/sysinit.h>
+
+const unsigned int dcplbs_table[16][2] = {
+ { 0xFFA00000, (PAGE_SIZE_1MB | CPLB_D_PAGE_MGMT | CPLB_WT) },
+ { 0xFF900000, (PAGE_SIZE_1MB | CPLB_D_PAGE_MGMT | CPLB_WT) },/* L1 Data B */
+ { 0xFF800000, (PAGE_SIZE_1MB | CPLB_D_PAGE_MGMT | CPLB_WT) },/* L1 Data A */
+ { 0xFFB00000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) },
+
+ { 0x20300000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) },/* Async Memory Bank 3 */
+ { 0x20200000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) },/* Async Memory Bank 2 */
+ { 0x20100000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) },/* Async Memory Bank 1 */
+ { 0x20000000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) }, /* Async Memory Bank 0 */
+
+ { 0x02400000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) },
+ { 0x02000000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) },
+ { 0x00C00000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) },
+ { 0x00800000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) },
+ { 0x00400000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) },
+ { 0x00000000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) },
+
+ { 0xffffffff, 0xffffffff }/* end of section - termination */
+};
+
+
+const unsigned int _icplbs_table[16][2] = {
+ { 0xFFA00000, (PAGE_SIZE_1MB | CPLB_I_PAGE_MGMT | CPLB_I_PAGE_MGMT | 0x4) },
+ /* L1 Code */
+ { 0xEF000000, (PAGE_SIZE_1MB | CPLB_INOCACHE) }, /* AREA DE BOOT */
+ { 0xFFB00000, (PAGE_SIZE_1MB | CPLB_INOCACHE) },
+
+ { 0x20300000, (PAGE_SIZE_1MB | CPLB_INOCACHE) },/* Async Memory Bank 3 */
+ { 0x20200000, (PAGE_SIZE_1MB | CPLB_INOCACHE) },/* Async Bank 2 (Secnd) */
+ { 0x20100000, (PAGE_SIZE_1MB | CPLB_INOCACHE) },/* Async Bank 1 (Prim B) */
+ { 0x20000000, (PAGE_SIZE_1MB | CPLB_INOCACHE) },/* Async Bank 0 (Prim A) */
+
+ { 0x02400000, (PAGE_SIZE_4MB | CPLB_INOCACHE) },
+ { 0x02000000, (PAGE_SIZE_4MB | CPLB_INOCACHE) },
+ { 0x00C00000, (PAGE_SIZE_4MB | CPLB_INOCACHE) },
+ { 0x00800000, (PAGE_SIZE_4MB | CPLB_INOCACHE) },
+ { 0x00400000, (PAGE_SIZE_4MB | CPLB_INOCACHE) },
+ { 0x00000000, (PAGE_SIZE_4MB | CPLB_INOCACHE) },
+
+ { 0xffffffff, 0xffffffff }/* end of section - termination */
+};
+
+/*
+ * Init_PLL
+ *
+ * Routine to initialize the PLL. The TLL6527M uses a 25 Mhz XTAL.
+ */
+static void Init_PLL (void)
+{
+ unsigned short msel = 0;
+ unsigned short ssel = 0;
+
+ msel = (unsigned short)( (float)CCLK/(float)CLKIN );
+ ssel = (unsigned short)( (float)(CLKIN*msel)/(float)SCLK);
+
+ asm("cli r0;");
+
+ *((uint32_t*)SIC_IWR) = 0x1;
+
+ /* Configure PLL registers */
+ *((uint16_t*)PLL_DIV) = ssel;
+ msel = msel<<9;
+ *((uint16_t*)PLL_CTL) = msel;
+
+ /* Commands to set PLL values */
+ asm("idle;");
+ asm("sti r0;");
+}
+
+/*
+ * Init_EBIU
+ *
+ * Configure extern memory
+ */
+static void Init_EBIU (void)
+{
+ /* Check if SDRAM is already enabled */
+ if ( 0 != (*(uint16_t *)EBIU_SDSTAT & EBIU_SDSTAT_SDRS) ){
+ asm("ssync;");
+ /* RDIV = (100MHz*64ms)/8192-(6+3)=0x406 cycles */
+ *(uint16_t *)EBIU_SDRRC = 0x3F6; /* SHould have been 0x306*/
+ *(uint16_t *)EBIU_SDBCTL = EBIU_SDBCTL_EBCAW_10 | EBIU_SDBCTL_EBSZ_64M |
+ EBIU_SDBCTL_EBE;
+ *(uint32_t *)EBIU_SDGCTL = 0x8491998d;
+ asm("ssync;");
+ } else {
+ /* SDRAm is already programmed */
+ }
+}
+
+/*
+ * Init_Flags
+ *
+ * Enable LEDs port
+ */
+static void Init_Flags(void)
+{
+ *((uint16_t*)PORTH_FER) = 0x0;
+ *((uint16_t*)PORTH_MUX) = 0x0;
+ *((uint16_t*)PORTHIO_DIR) = 0x1<<15;
+ *((uint16_t*)PORTHIO_SET) = 0x1<<15;
+}
+
+RTEMS_SYSINIT_ITEM(
+ bfin_interrupt_init,
+ RTEMS_SYSINIT_BSP_PRE_DRIVERS,
+ RTEMS_SYSINIT_ORDER_MIDDLE
+);
+
+void bsp_start( void )
+{
+ int i;
+
+ /* BSP Hardware Initialization*/
+ Init_RTC(); /* Blackfin Real Time Clock initialization */
+ Init_PLL(); /* PLL initialization */
+ Init_EBIU(); /* EBIU initialization */
+ Init_Flags(); /* GPIO initialization */
+
+ /*
+ * Allocate the memory for the RTEMS Work Space. This can come from
+ * a variety of places: hard coded address, malloc'ed from outside
+ * RTEMS world (e.g. simulator or primitive memory manager), or (as
+ * typically done by stock BSPs) by subtracting the required amount
+ * of work space from the last physical address on the CPU board.
+ */
+ for (i=5;i<16;i++) {
+ set_vector((rtems_isr_entry)bfin_null_isr, i, 1);
+ }
+
+}
diff --git a/bsps/bfin/TLL6527M/start/linkcmds b/bsps/bfin/TLL6527M/start/linkcmds
new file mode 100644
index 0000000000..93d2a85d82
--- /dev/null
+++ b/bsps/bfin/TLL6527M/start/linkcmds
@@ -0,0 +1,176 @@
+OUTPUT_FORMAT("elf32-bfin", "elf32-bfin",
+ "elf32-bfin")
+
+OUTPUT_ARCH(bfin)
+ENTRY(__start)
+STARTUP(start.o)
+
+/*
+ * Declare some sizes.
+ */
+_RamBase = DEFINED(_RamBase) ? _RamBase : 0x0;
+_RamSize = DEFINED(_RamSize) ? _RamSize : 0x04000000;
+_HeapSize = DEFINED(_HeapSize) ? _HeapSize : 0x10000;
+_StackSize = DEFINED(_StackSize) ? _StackSize : 0x10000;
+
+MEMORY
+{
+ sdram(rwx) : ORIGIN = 0x00000100, LENGTH = 0x04000000
+
+ l1dataA(rwx) : ORIGIN = 0xff800000, LENGTH = 0x00004000
+ l1dataAC(rwx) : ORIGIN = 0xff804000, LENGTH = 0x00004000
+ l1dataB(rwx) : ORIGIN = 0xff900000, LENGTH = 0x00004000
+ l1dataBC(rwx) : ORIGIN = 0xff904000, LENGTH = 0x00004000
+
+ l1code(rwx) : ORIGIN = 0xffa00000, LENGTH = 0x0000C000
+ l1codeC(rwx) : ORIGIN = 0xffa10000, LENGTH = 0x00004000
+ scratchpad(rwx) : ORIGIN = 0xffb00000, LENGTH = 0x00001000
+}
+
+SECTIONS
+{
+
+ .init :
+ {
+ *(.l1code)
+ KEEP (*(.init))
+ } > sdram /*=0*/
+
+ .text :
+ {
+ CREATE_OBJECT_SYMBOLS
+ *(.text)
+ *(.rodata*)
+ *(.gnu.linkonce.r*)
+
+ /*
+ * Special FreeBSD sysctl sections.
+ */
+ . = ALIGN (16);
+ ___start_set_sysctl_set = .;
+ *(set_sysctl_*);
+ ___stop_set_sysctl_set = ABSOLUTE(.);
+ *(set_domain_*);
+ *(set_pseudo_*);
+
+ _etext = .;
+
+ ___CTOR_LIST__ = .;
+ LONG((___CTOR_END__ - ___CTOR_LIST__) / 4 - 2)
+ *(.ctors)
+ LONG(0)
+ ___CTOR_END__ = .;
+ ___DTOR_LIST__ = .;
+ LONG((___DTOR_END__ - ___DTOR_LIST__) / 4 - 2)
+ *(.dtors)
+ LONG(0)
+ ___DTOR_END__ = .;
+ } > sdram
+
+ .tdata : {
+ __TLS_Data_begin = .;
+ *(.tdata .tdata.* .gnu.linkonce.td.*)
+ __TLS_Data_end = .;
+ } > sdram
+
+ .tbss : {
+ __TLS_BSS_begin = .;
+ *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon)
+ __TLS_BSS_end = .;
+ } > sdram
+
+ __TLS_Data_size = __TLS_Data_end - __TLS_Data_begin;
+ __TLS_Data_begin = __TLS_Data_size != 0 ? __TLS_Data_begin : __TLS_BSS_begin;
+ __TLS_Data_end = __TLS_Data_size != 0 ? __TLS_Data_end : __TLS_BSS_begin;
+ __TLS_BSS_size = __TLS_BSS_end - __TLS_BSS_begin;
+ __TLS_Size = __TLS_BSS_end - __TLS_Data_begin;
+ __TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss));
+
+ .fini :
+ {
+ KEEP (*(.fini))
+ } > sdram /*=0*/
+
+ .data :
+ {
+ *(.data)
+ KEEP (*(SORT(.rtemsrwset.*)))
+ *(.jcr)
+ *(.gnu.linkonce.d*)
+ CONSTRUCTORS
+ _edata = .;
+ } > sdram
+
+ .eh_frame : { *(.eh_frame) } > sdram
+ .data1 : { *(.data1) } > sdram
+ .eh_frame : { *(.eh_frame) } > sdram
+ .gcc_except_table : { *(.gcc_except_table*) } > sdram
+
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata.*)
+ KEEP (*(SORT(.rtemsroset.*)))
+ *(.gnu.linkonce.r*)
+ } > sdram
+
+
+ .bss :
+ {
+ _bss_start = .;
+ _clear_start = .;
+ *(.bss)
+ *(.gnu.linkonce.b.*)
+ *(COMMON)
+ . = ALIGN (64);
+ _stack_init = .;
+ . += _StackSize;
+ _clear_end = .;
+ _WorkAreaBase = .;
+ _end = .;
+ __end = .;
+ } > sdram
+
+/* Debugging stuff follows */
+
+ /* Stabs debugging sections. */
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ /* DWARF debug sections.
+ Symbols in the DWARF debugging sections are relative to the beginning
+ of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+ /*.stack 0x80000 : { _stack = .; *(.stack) }*/
+ /* These must appear regardless of . */
+}
+
+__HeapSize = _HeapSize;
+__edata = _edata;
+__etext = _etext;
+
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-18 01:39:57 +0000