diff options
Diffstat (limited to 'bsps/arm/stm32h7/include/stm32h7xx_ll_system.h')
| -rw-r--r-- | bsps/arm/stm32h7/include/stm32h7xx_ll_system.h | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/bsps/arm/stm32h7/include/stm32h7xx_ll_system.h b/bsps/arm/stm32h7/include/stm32h7xx_ll_system.h index 77fc4ff5c4..450f8c293f 100644 --- a/bsps/arm/stm32h7/include/stm32h7xx_ll_system.h +++ b/bsps/arm/stm32h7/include/stm32h7xx_ll_system.h @@ -47,6 +47,7 @@ extern "C" { #if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU)
/** @defgroup SYSTEM_LL SYSTEM
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
@@ -55,9 +56,11 @@ extern "C" { /* Private constants ---------------------------------------------------------*/
/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
/** @defgroup SYSTEM_LL_EC_FLASH_BANK1_SECTORS SYSCFG Flash Bank1 sectors bits status
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define LL_SYSCFG_FLASH_B1_SECTOR0_STATUS_BIT 0x10000U
@@ -73,6 +76,7 @@ extern "C" { */
/** @defgroup SYSTEM_LL_EC_FLASH_BANK2_SECTORS SYSCFG Flash Bank2 sectors bits status
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define LL_SYSCFG_FLASH_B2_SECTOR0_STATUS_BIT 0x10000U
@@ -95,10 +99,12 @@ extern "C" { /* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_PMCR_I2C1_FMP /*!< Enable Fast Mode Plus for I2C1 */
@@ -114,6 +120,7 @@ extern "C" { */
/** @defgroup SYSTEM_LL_EC_ANALOG_SWITCH Analog Switch control
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define LL_SYSCFG_ANALOG_SWITCH_BOOSTEN SYSCFG_PMCR_BOOSTEN /*!< I/O analog switch voltage booster enable */
@@ -127,6 +134,7 @@ extern "C" { #if defined(SYSCFG_PMCR_EPIS_SEL)
/** @defgroup SYSTEM_LL_EC_EPIS Ethernet PHY Interface Selection
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define LL_SYSCFG_ETH_MII 0x00000000U /*!< ETH Media MII interface */
@@ -137,6 +145,7 @@ extern "C" { #endif /* SYSCFG_PMCR_EPIS_SEL */
/** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define LL_SYSCFG_EXTI_PORTA 0U /*!< EXTI PORT A */
@@ -155,6 +164,7 @@ extern "C" { */
/** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define LL_SYSCFG_EXTI_LINE0 ((0x000FUL << 16U) | 0U) /*!< EXTI_POSITION_0 | EXTICR[0] */
@@ -178,6 +188,7 @@ extern "C" { */
/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define LL_SYSCFG_TIMBREAK_AXISRAM_DBL_ECC SYSCFG_CFGR_AXISRAML /*!< Enables and locks the AXIRAM double ECC error signal
@@ -222,6 +233,7 @@ extern "C" { */
/** @defgroup SYSTEM_LL_EC_CS SYSCFG I/O compensation cell Code selection
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define LL_SYSCFG_CELL_CODE 0U
@@ -231,6 +243,7 @@ extern "C" { */
/** @defgroup SYSTEM_LL_IWDG1_CONTROL_MODES SYSCFG IWDG1 control modes
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define LL_SYSCFG_IWDG1_SW_CONTROL_MODE 0U
@@ -241,6 +254,7 @@ extern "C" { #if defined (DUAL_CORE)
/** @defgroup SYSTEM_LL_IWDG2_CONTROL_MODES SYSCFG IWDG2 control modes
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define LL_SYSCFG_IWDG2_SW_CONTROL_MODE 0U
@@ -251,6 +265,7 @@ extern "C" { #endif /* DUAL_CORE */
/** @defgroup SYSTEM_LL_DTCM_RAM_SIZE SYSCFG DTCM RAM size configuration
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define LL_SYSCFG_DTCM_RAM_SIZE_2KB 0U
@@ -262,6 +277,7 @@ extern "C" { */
#ifdef SYSCFG_PKGR_PKG
/** @defgroup SYSTEM_LL_PACKAGE SYSCFG device package
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define LL_SYSCFG_LQFP100_PACKAGE 0U
@@ -274,6 +290,7 @@ extern "C" { #endif /* SYSCFG_PKGR_PKG */
/** @defgroup SYSTEM_LL_SYSCFG_BOR SYSCFG Brownout Reset Threshold Level
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define LL_SYSCFG_BOR_OFF_RESET_LEVEL 0x00000000U
@@ -286,6 +303,7 @@ extern "C" { */
/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */
@@ -298,6 +316,7 @@ extern "C" { */
/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1LFZ1_DBG_TIM2 /*!< TIM2 counter stopped when core is halted */
@@ -318,6 +337,7 @@ extern "C" { */
/** @defgroup SYSTEM_LL_EC_APB1_GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define LL_DBGMCU_APB1_GRP2_FDCAN_STOP DBGMCU_APB1HFZ1_DBG_FDCAN /*!< FDCAN is frozen while the core is in debug mode */
@@ -326,6 +346,7 @@ extern "C" { */
/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2FZ1_DBG_TIM1 /*!< TIM1 counter stopped when core is halted */
@@ -339,6 +360,7 @@ extern "C" { */
/** @defgroup SYSTEM_LL_EC_APB3_GRP1_STOP_IP DBGMCU APB3 GRP1 STOP IP
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define LL_DBGMCU_APB3_GRP1_WWDG1_STOP DBGMCU_APB3FZ1_DBG_WWDG1 /*!< WWDG1 is frozen while the core is in debug mode */
@@ -347,6 +369,7 @@ extern "C" { */
/** @defgroup SYSTEM_LL_EC_APB4_GRP1_STOP_IP DBGMCU APB4 GRP1 STOP IP
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define LL_DBGMCU_APB4_GRP1_I2C4_STOP DBGMCU_APB4FZ1_DBG_I2C4 /*!< I2C4 is frozen while the core is in debug mode */
@@ -361,6 +384,7 @@ extern "C" { */
/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */
@@ -383,10 +407,12 @@ extern "C" { /* Exported functions --------------------------------------------------------*/
/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
@@ -1653,6 +1679,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_IOHSLV(void) */
/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
@@ -2144,6 +2171,7 @@ __STATIC_INLINE void LL_DBGMCU_APB4_GRP1_UnFreezePeriph(uint32_t Periphs) */
/** @defgroup SYSTEM_LL_EF_FLASH FLASH
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
@@ -2190,6 +2218,7 @@ __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void) #if defined(DUAL_CORE)
/** @defgroup SYSTEM_LL_EF_ART ART
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
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