diff options
Diffstat (limited to 'bsps/arm/stm32h7/include/stm32h7xx_ll_spi.h')
| -rw-r--r-- | bsps/arm/stm32h7/include/stm32h7xx_ll_spi.h | 57 |
1 files changed, 57 insertions, 0 deletions
diff --git a/bsps/arm/stm32h7/include/stm32h7xx_ll_spi.h b/bsps/arm/stm32h7/include/stm32h7xx_ll_spi.h index 2808474e53..437b27ef35 100644 --- a/bsps/arm/stm32h7/include/stm32h7xx_ll_spi.h +++ b/bsps/arm/stm32h7/include/stm32h7xx_ll_spi.h @@ -35,6 +35,7 @@ extern "C" { #if defined(SPI1) || defined(SPI2) || defined(SPI3) || defined(SPI4) || defined(SPI5) || defined(SPI6)
/** @defgroup SPI_LL SPI
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
@@ -45,6 +46,7 @@ extern "C" { /* Private macros ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)
/** @defgroup SPI_LL_Private_Macros SPI Private Macros
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
@@ -115,10 +117,12 @@ typedef struct /* Exported constants --------------------------------------------------------*/
/** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
+ * @ingroup RTEMSBSPsARMSTM32H7 * @brief Flags defines which can be used with LL_SPI_ReadReg function
* @{
*/
@@ -141,6 +145,7 @@ typedef struct */
/** @defgroup SPI_LL_EC_IT IT Defines
+ * @ingroup RTEMSBSPsARMSTM32H7 * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
* @{
*/
@@ -160,6 +165,7 @@ typedef struct */
/** @defgroup SPI_LL_EC_MODE Mode
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define LL_SPI_MODE_MASTER (SPI_CFG2_MASTER)
@@ -169,6 +175,7 @@ typedef struct */
/** @defgroup SPI_LL_EC_SS_LEVEL SS Level
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define LL_SPI_SS_LEVEL_HIGH (SPI_CR1_SSI)
@@ -178,6 +185,7 @@ typedef struct */
/** @defgroup SPI_LL_EC_SS_IDLENESS SS Idleness
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define LL_SPI_SS_IDLENESS_00CYCLE (0x00000000UL)
@@ -201,6 +209,7 @@ typedef struct */
/** @defgroup SPI_LL_EC_ID_IDLENESS Master Inter-Data Idleness
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define LL_SPI_ID_IDLENESS_00CYCLE (0x00000000UL)
@@ -224,6 +233,7 @@ typedef struct */
/** @defgroup SPI_LL_EC_TXCRCINIT_ALL TXCRC Init All
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN (0x00000000UL)
@@ -233,6 +243,7 @@ typedef struct */
/** @defgroup SPI_LL_EC_RXCRCINIT_ALL RXCRC Init All
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN (0x00000000UL)
@@ -242,6 +253,7 @@ typedef struct */
/** @defgroup SPI_LL_EC_UDR_CONFIG_REGISTER UDR Config Register
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define LL_SPI_UDR_CONFIG_REGISTER_PATTERN (0x00000000UL)
@@ -252,6 +264,7 @@ typedef struct */
/** @defgroup SPI_LL_EC_UDR_DETECT_BEGIN_DATA UDR Detect Begin Data
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define LL_SPI_UDR_DETECT_BEGIN_DATA_FRAME (0x00000000UL)
@@ -262,6 +275,7 @@ typedef struct */
/** @defgroup SPI_LL_EC_PROTOCOL Protocol
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define LL_SPI_PROTOCOL_MOTOROLA (0x00000000UL)
@@ -271,6 +285,7 @@ typedef struct */
/** @defgroup SPI_LL_EC_PHASE Phase
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define LL_SPI_PHASE_1EDGE (0x00000000UL)
@@ -280,6 +295,7 @@ typedef struct */
/** @defgroup SPI_LL_EC_POLARITY Polarity
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define LL_SPI_POLARITY_LOW (0x00000000UL)
@@ -289,6 +305,7 @@ typedef struct */
/** @defgroup SPI_LL_EC_NSS_POLARITY NSS Polarity
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define LL_SPI_NSS_POLARITY_LOW (0x00000000UL)
@@ -298,6 +315,7 @@ typedef struct */
/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define LL_SPI_BAUDRATEPRESCALER_DIV2 (0x00000000UL)
@@ -313,6 +331,7 @@ typedef struct */
/** @defgroup SPI_LL_EC_BIT_ORDER Bit Order
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define LL_SPI_LSB_FIRST (SPI_CFG2_LSBFRST)
@@ -322,6 +341,7 @@ typedef struct */
/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define LL_SPI_FULL_DUPLEX (0x00000000UL)
@@ -334,6 +354,7 @@ typedef struct */
/** @defgroup SPI_LL_EC_DATAWIDTH Data Width
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define LL_SPI_DATAWIDTH_4BIT (SPI_CFG1_DSIZE_0 | SPI_CFG1_DSIZE_1)
@@ -370,6 +391,7 @@ typedef struct */
/** @defgroup SPI_LL_EC_FIFO_TH FIFO Threshold
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define LL_SPI_FIFO_TH_01DATA (0x00000000UL)
@@ -395,6 +417,7 @@ typedef struct #if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)
/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define LL_SPI_CRCCALCULATION_DISABLE (0x00000000UL) /*!< CRC calculation disabled */
@@ -405,6 +428,7 @@ typedef struct #endif /* USE_FULL_LL_DRIVER */
/** @defgroup SPI_LL_EC_CRC CRC
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define LL_SPI_CRC_4BIT (SPI_CFG1_CRCSIZE_0 | SPI_CFG1_CRCSIZE_1)
@@ -441,6 +465,7 @@ typedef struct */
/** @defgroup SPI_LL_EC_NSS_MODE NSS Mode
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define LL_SPI_NSS_SOFT (SPI_CFG2_SSM)
@@ -451,6 +476,7 @@ typedef struct */
/** @defgroup SPI_LL_EC_RX_FIFO RxFIFO Packing LeVel
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define LL_SPI_RX_FIFO_0PACKET (0x00000000UL) /* 0 or multiple of 4 packet available is the RxFIFO */
@@ -467,10 +493,12 @@ typedef struct /* Exported macro ------------------------------------------------------------*/
/** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
@@ -502,10 +530,12 @@ typedef struct /* Exported functions --------------------------------------------------------*/
/** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
/** @defgroup SPI_LL_EF_Configuration Configuration
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
@@ -1648,6 +1678,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx) */
/** @defgroup SPI_LL_EF_FLAG_Management FLAG_Management
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
@@ -1935,6 +1966,7 @@ __STATIC_INLINE void LL_SPI_ClearFlag_SUSP(SPI_TypeDef *SPIx) */
/** @defgroup SPI_LL_EF_IT_Management IT_Management
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
@@ -2306,6 +2338,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TSER(SPI_TypeDef *SPIx) */
/** @defgroup SPI_LL_EF_DMA_Management DMA Management
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
@@ -2380,6 +2413,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx) */
/** @defgroup SPI_LL_EF_DATA_Management DATA_Management
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
@@ -2531,6 +2565,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx) #if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)
/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
@@ -2547,6 +2582,7 @@ void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct); */
/** @defgroup I2S_LL I2S
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
@@ -2557,6 +2593,7 @@ void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct); /* Exported types ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)
/** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
@@ -2610,10 +2647,12 @@ typedef struct /* Exported constants --------------------------------------------------------*/
/** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
/** @defgroup I2S_LL_EC_DATA_FORMAT Data Format
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define LL_I2S_DATAFORMAT_16B (0x00000000UL)
@@ -2626,6 +2665,7 @@ typedef struct */
/** @defgroup I2S_LL_EC_CHANNEL_LENGTH_TYPE Type of Channel Length
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define LL_I2S_SLAVE_VARIABLE_CH_LENGTH (0x00000000UL)
@@ -2635,6 +2675,7 @@ typedef struct */
/** @defgroup I2S_LL_EC_POLARITY Clock Polarity
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define LL_I2S_POLARITY_LOW (0x00000000UL)
@@ -2644,6 +2685,7 @@ typedef struct */
/** @defgroup I2S_LL_EC_STANDARD I2S Standard
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define LL_I2S_STANDARD_PHILIPS (0x00000000UL)
@@ -2656,6 +2698,7 @@ typedef struct */
/** @defgroup I2S_LL_EC_MODE Operation Mode
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define LL_I2S_MODE_SLAVE_TX (0x00000000UL)
@@ -2669,6 +2712,7 @@ typedef struct */
/** @defgroup I2S_LL_EC_PRESCALER_PARITY Prescaler Factor
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define LL_I2S_PRESCALER_PARITY_EVEN (0x00000000UL) /*!< Odd factor: Real divider value is = I2SDIV * 2 */
@@ -2678,6 +2722,7 @@ typedef struct */
/** @defgroup I2S_LL_EC_FIFO_TH FIFO Threshold Level
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define LL_I2S_FIFO_TH_01DATA (LL_SPI_FIFO_TH_01DATA)
@@ -2693,6 +2738,7 @@ typedef struct */
/** @defgroup I2S_LL_EC_BIT_ORDER Transmission Bit Order
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define LL_I2S_LSB_FIRST (LL_SPI_LSB_FIRST)
@@ -2704,6 +2750,7 @@ typedef struct #if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)
/** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define LL_I2S_MCLK_OUTPUT_DISABLE (0x00000000UL)
@@ -2713,6 +2760,7 @@ typedef struct */
/** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
@@ -2737,10 +2785,12 @@ typedef struct /* Exported macro ------------------------------------------------------------*/
/** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
/** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
@@ -2772,10 +2822,12 @@ typedef struct /* Exported functions --------------------------------------------------------*/
/** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
/** @defgroup I2S_LL_EF_Configuration Configuration
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
@@ -3274,6 +3326,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx) /** @defgroup I2S_LL_EF_FLAG_Management FLAG_Management
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
@@ -3370,6 +3423,7 @@ __STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx) */
/** @defgroup I2S_LL_EF_IT_Management IT_Management
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
@@ -3543,6 +3597,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_FRE(SPI_TypeDef *SPIx) */
/** @defgroup I2S_LL_EF_DMA_Management DMA_Management
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
@@ -3617,6 +3672,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx) */
/** @defgroup I2S_LL_EF_DATA_Management DATA_Management
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
@@ -3673,6 +3729,7 @@ __STATIC_INLINE void LL_I2S_TransmitData32(SPI_TypeDef *SPIx, uint32_t TxData) #if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)
/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
|