diff options
Diffstat (limited to 'bsps/arm/stm32h7/include/stm32h7xx_hal_flash_ex.h')
| -rw-r--r-- | bsps/arm/stm32h7/include/stm32h7xx_hal_flash_ex.h | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_flash_ex.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_flash_ex.h index 834c5d23fb..e411dbed62 100644 --- a/bsps/arm/stm32h7/include/stm32h7xx_hal_flash_ex.h +++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_flash_ex.h @@ -38,6 +38,7 @@ /* Exported types ------------------------------------------------------------*/
/** @defgroup FLASHEx_Exported_Types FLASH Exported Types
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
@@ -174,10 +175,12 @@ typedef struct /* Exported constants --------------------------------------------------------*/
/** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
/** @defgroup FLASHEx_Type_Erase FLASH Type Erase
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define FLASH_TYPEERASE_SECTORS 0x00U /*!< Sectors erase only */
@@ -188,6 +191,7 @@ typedef struct #if defined (FLASH_CR_PSIZE)
/** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define FLASH_VOLTAGE_RANGE_1 0x00000000U /*!< Flash program/erase by 8 bits */
@@ -200,6 +204,7 @@ typedef struct #endif /* FLASH_CR_PSIZE */
/** @defgroup FLASHEx_WRP_State FLASH WRP State
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define OB_WRPSTATE_DISABLE 0x00000000U /*!< Disable the write protection of the desired bank 1 sectors */
@@ -209,6 +214,7 @@ typedef struct */
/** @defgroup FLASHEx_Option_Type FLASH Option Type
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define OPTIONBYTE_WRP 0x01U /*!< WRP option byte configuration */
@@ -232,6 +238,7 @@ typedef struct */
/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define OB_RDP_LEVEL_0 0xAA00U
@@ -243,6 +250,7 @@ typedef struct */
/** @defgroup FLASHEx_Option_Bytes_WWatchdog FLASH Option Bytes WWatchdog
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define OB_WWDG_SW 0x10U /*!< Software WWDG selected */
@@ -253,6 +261,7 @@ typedef struct /** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define OB_IWDG_SW 0x20U /*!< Software IWDG selected */
@@ -262,6 +271,7 @@ typedef struct */
/** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define OB_STOP_NO_RST 0x40U /*!< No reset generated when entering in STOP */
@@ -271,6 +281,7 @@ typedef struct */
/** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define OB_STDBY_NO_RST 0x80U /*!< No reset generated when entering in STANDBY */
@@ -280,6 +291,7 @@ typedef struct */
/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_STOP FLASH IWDG Counter Freeze in STOP
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define OB_IWDG_STOP_FREEZE 0x00000000U /*!< Freeze IWDG counter in STOP mode */
@@ -289,6 +301,7 @@ typedef struct */
/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_SANDBY FLASH IWDG Counter Freeze in STANDBY
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define OB_IWDG_STDBY_FREEZE 0x00000000U /*!< Freeze IWDG counter in STANDBY mode */
@@ -298,6 +311,7 @@ typedef struct */
/** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define OB_BOR_LEVEL0 0x00000000U /*!< Reset level threshold is set to 1.6V */
@@ -311,6 +325,7 @@ typedef struct /** @defgroup FLASHEx_Boot_Address FLASH Boot Address
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define OB_BOOTADDR_ITCM_RAM 0x0000U /*!< Boot from ITCM RAM (0x00000000) */
@@ -325,6 +340,7 @@ typedef struct */
/** @defgroup FLASH_Latency FLASH Latency
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero Latency cycle */
@@ -348,6 +364,7 @@ typedef struct */
/** @defgroup FLASHEx_Banks FLASH Banks
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define FLASH_BANK_1 0x01U /*!< Bank 1 */
@@ -358,6 +375,7 @@ typedef struct */
/** @defgroup FLASHEx_OB_PCROP_RDP FLASHEx OB PCROP RDP
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define OB_PCROP_RDP_NOT_ERASE 0x00000000U /*!< PCROP area is not erased when the RDP level
@@ -370,6 +388,7 @@ typedef struct */
/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#if (FLASH_SECTOR_TOTAL == 128)
@@ -422,6 +441,7 @@ typedef struct */
/** @defgroup FLASHEx_OB_SECURITY FLASHEx OB SECURITY
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define OB_SECURITY_DISABLE 0x00000000U /*!< security enabled */
@@ -431,6 +451,7 @@ typedef struct */
/** @defgroup FLASHEx_OB_ST_RAM_SIZE FLASHEx OB ST RAM SIZE
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define OB_ST_RAM_SIZE_2KB 0x00000000U /*!< 2 Kbytes reserved to ST code */
@@ -443,6 +464,7 @@ typedef struct #if defined(DUAL_CORE)
/** @defgroup FLASHEx_OB_BCM7 FLASHEx OB BCM7
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define OB_BCM7_DISABLE 0x00000000U /*!< CM7 Boot disabled */
@@ -453,6 +475,7 @@ typedef struct */
/** @defgroup FLASHEx_OB_BCM4 FLASHEx OB BCM4
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define OB_BCM4_DISABLE 0x00000000U /*!< CM4 Boot disabled */
@@ -463,6 +486,7 @@ typedef struct #endif /* DUAL_CORE */
/** @defgroup FLASHEx_OB_IWDG1_SW FLASHEx OB IWDG1 SW
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define OB_IWDG1_SW FLASH_OPTSR_IWDG1_SW /*!< Hardware independent watchdog 1 */
@@ -473,6 +497,7 @@ typedef struct #if defined(DUAL_CORE)
/** @defgroup FLASHEx_OB_IWDG2_SW FLASHEx OB IWDG2 SW
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define OB_IWDG2_SW FLASH_OPTSR_IWDG2_SW /*!< Hardware independent watchdog 2*/
@@ -483,6 +508,7 @@ typedef struct #endif
/** @defgroup FLASHEx_OB_NRST_STOP_D1 FLASHEx OB NRST STOP D1
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define OB_STOP_RST_D1 0x00000000U /*!< Reset generated when entering the D1 to stop mode */
@@ -492,6 +518,7 @@ typedef struct */
/** @defgroup FLASHEx_OB_NRST_STDBY_D1 FLASHEx OB NRST STDBY D1
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define OB_STDBY_RST_D1 0x00000000U /*!< Reset generated when entering the D1 to standby mode */
@@ -502,6 +529,7 @@ typedef struct #if defined (DUAL_CORE)
/** @defgroup FLASHEx_OB_NRST_STOP_D2 FLASHEx OB NRST STOP D2
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define OB_STOP_RST_D2 0x00000000U /*!< Reset generated when entering the D2 to stop mode */
@@ -511,6 +539,7 @@ typedef struct */
/** @defgroup FLASHEx_OB_NRST_STDBY_D2 FLASHEx OB NRST STDBY D2
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define OB_STDBY_RST_D2 0x00000000U /*!< Reset generated when entering the D2 to standby mode */
@@ -521,6 +550,7 @@ typedef struct #endif /* DUAL_CORE */
/** @defgroup FLASHEx_OB_SWAP_BANK FLASHEx OB SWAP BANK
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define OB_SWAP_BANK_DISABLE 0x00000000U /*!< Bank swap disabled */
@@ -530,6 +560,7 @@ typedef struct */
/** @defgroup FLASHEx_OB_IOHSLV FLASHEx OB IOHSLV
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define OB_IOHSLV_DISABLE 0x00000000U /*!< IOHSLV disabled */
@@ -540,6 +571,7 @@ typedef struct #if defined (FLASH_OPTSR_VDDMMC_HSLV)
/** @defgroup FLASHEx_OB_VDDMMC_HSLV FLASHEx OB VDDMMC HSLV
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define OB_VDDMMC_HSLV_DISABLE 0x00000000U /*!< VDDMMC HSLV disabled */
@@ -550,6 +582,7 @@ typedef struct #endif /* FLASH_OPTSR_VDDMMC_HSLV */
/** @defgroup FLASHEx_OB_BOOT_OPTION FLASHEx OB BOOT OPTION
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define OB_BOOT_ADD0 0x01U /*!< Select Boot Address 0 */
@@ -560,6 +593,7 @@ typedef struct */
/** @defgroup FLASHEx_OB_USER_Type FLASHEx OB USER Type
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define OB_USER_IWDG1_SW 0x0001U /*!< Independent watchdog selection */
@@ -587,6 +621,7 @@ typedef struct */
/** @defgroup FLASHEx_OB_SECURE_RDP FLASHEx OB SECURE RDP
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define OB_SECURE_RDP_NOT_ERASE 0x00000000U /*!< Secure area is not erased when the RDP level
@@ -598,6 +633,7 @@ typedef struct */
/** @defgroup FLASHEx_CRC_Selection_Type FLASH CRC Selection Type
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define FLASH_CRC_ADDR 0x00000000U /*!< CRC selection type by address */
@@ -608,6 +644,7 @@ typedef struct */
/** @defgroup FLASHEx_CRC_Burst_Size FLASH CRC Burst Size
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define FLASH_CRC_BURST_SIZE_4 0x00000000U /*!< Every burst has a size of 4 Flash words (256-bit) */
@@ -619,6 +656,7 @@ typedef struct */
/** @defgroup FLASHEx_Programming_Delay FLASH Programming Delay
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define FLASH_PROGRAMMING_DELAY_0 0x00000000U /*!< programming delay set for Flash running at 70 MHz or below */
@@ -631,6 +669,7 @@ typedef struct #if defined (FLASH_OTPBL_LOCKBL)
/** @defgroup FLASHEx_OTP_Blocks FLASH OTP blocks
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
#define FLASH_OTP_BLOCK_0 0x00000001U /*!< OTP Block0 */
@@ -657,6 +696,7 @@ typedef struct /* Exported macro ------------------------------------------------------------*/
/** @defgroup FLASHEx_Exported_Macros FLASH Exported Macros
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
/**
@@ -741,10 +781,12 @@ HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_ /* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
/** @defgroup FLASHEx_IS_FLASH_Definitions FLASHEx Private macros to check input parameters
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
@@ -882,6 +924,7 @@ HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_ /* Private functions ---------------------------------------------------------*/
/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
+ * @ingroup RTEMSBSPsARMSTM32H7 * @{
*/
void FLASH_Erase_Sector(uint32_t Sector, uint32_t Banks, uint32_t VoltageRange);
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