diff options
author | Joel Sherrill <joel.sherrill@oarcorp.com> | 2012-06-11 13:37:29 -0500 |
---|---|---|
committer | Joel Sherrill <joel.sherrill@oarcorp.com> | 2012-06-11 13:37:29 -0500 |
commit | 2d7ae960bbdbc82f795814ee6c600e93200ddf4d (patch) | |
tree | ad12bf1ac7f551a70f004a897a7246cf0b9ea716 /cpukit/score/cpu/v850/cpu.c | |
parent | powerpc/cpu.h: Define CPU_SIMPLE_VECTORED_INTERRUPTS and remove _CPU_ISR_Init... (diff) | |
download | rtems-2d7ae960bbdbc82f795814ee6c600e93200ddf4d.tar.bz2 |
v850 port: Initial addition with BSP for simulator in GDB
Port
+ v850 does not have appear to have any optimized bit scan instructions
+ v850 does have single instructions for wap u16 and u32
+ Code path optimization preferences set
+ Add BSP variants for each GCC CPU model flag and a README
- v850e1 variant does not work (fails during BSP initialization)
BSP for GDB v850 Simulator
+ linkcmds matches defaults in GDB simulator with RTEMS mods
+ crt1.c added from v850 newlib port for __main()
+ BSP exits cleanly
+ printk and console I/O work
+ uses clock tick from IDLE task
+ Tests not requiring real clock ISR work
Documentation
+ CPU Supplment chapter for v850 added
Diffstat (limited to 'cpukit/score/cpu/v850/cpu.c')
-rw-r--r-- | cpukit/score/cpu/v850/cpu.c | 98 |
1 files changed, 98 insertions, 0 deletions
diff --git a/cpukit/score/cpu/v850/cpu.c b/cpukit/score/cpu/v850/cpu.c new file mode 100644 index 0000000000..6a7dd205af --- /dev/null +++ b/cpukit/score/cpu/v850/cpu.c @@ -0,0 +1,98 @@ +/** + * @file + * + * v850 CPU Dependent Source + */ + +/* + * COPYRIGHT (c) 1989-2012. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <rtems/system.h> +#include <rtems/score/isr.h> +#include <rtems/score/wkspace.h> + +#include <string.h> /* for memset */ + +/* + * v850 Specific Information: + * + * So far nothing known to be needed at this point during initialization. + */ +void _CPU_Initialize(void) +{ +} + +/* + * v850 Specific Information: + * + * This method returns 0 if interrupts are enabled and 1 if they are disabled. + * The v850 only has two interrupt levels (on and off). + */ +uint32_t _CPU_ISR_Get_level( void ) +{ + unsigned int psw; + + v850_get_psw( psw ); + + if ( (psw & V850_PSW_INTERRUPT_DISABLE_MASK) == V850_PSW_INTERRUPT_DISABLE ) + return 1; + + return 0; +} + +/* + * v850 Specific Information: + * + * This method initializes a v850 context control structure. + */ +void _CPU_Context_Initialize( + Context_Control *the_context, + uint32_t *stack_base, + uint32_t size, + uint32_t new_level, + void *entry_point, + bool is_fp +) +{ + uint32_t stack_high; /* highest "stack aligned" address */ + uint32_t psw; /* highest "stack aligned" address */ + + memset( the_context, 0, sizeof(Context_Control) ); + + /* + * On CPUs with stacks which grow down, we build the stack + * based on the stack_high address. + */ + stack_high = ((uint32_t)(stack_base) + size); + stack_high &= ~(CPU_STACK_ALIGNMENT - 1); + + v850_get_psw( psw ); + psw &= ~V850_PSW_INTERRUPT_DISABLE_MASK; + if ( new_level ) + psw |= V850_PSW_INTERRUPT_DISABLE; + else + psw |= V850_PSW_INTERRUPT_ENABLE; + + the_context->r31 = (uint32_t) entry_point; + the_context->r3_stack_pointer = stack_high; + the_context->psw = psw; + +#if 0 + printk( "the_context = %p\n", the_context ); + printk( "stack base = 0x%08x\n", stack_base ); + printk( "stack size = 0x%08x\n", size ); + printk( "sp = 0x%08x\n", the_context->r3_stack_pointer ); + printk( "psw = 0x%08x\n", the_context->psw ); +#endif +} + |