diff options
author | Padmarao Begari <padmarao.begari@microchip.com> | 2022-09-19 18:30:26 +0530 |
---|---|---|
committer | Joel Sherrill <joel@rtems.org> | 2022-09-20 12:00:51 -0500 |
commit | 6b0d3c987349d188b65e9fc8229daeba247928c5 (patch) | |
tree | 4f6f37aaab9be619b82612eb4f000a42549488ca /cpukit/score/cpu/riscv/include/rtems/score/cpu.h | |
parent | spec/build/bsps: Add dtb support (diff) | |
download | rtems-6b0d3c987349d188b65e9fc8229daeba247928c5.tar.bz2 |
bsps/riscv: Add Microchip PolarFire SoC BSP variant
The Microchip PolarFire SoC support is implemented as a
riscv BSP variant to boot with any individual hart(cpu core)
or SMP based on the boot HARTID configurable and support
components are 4 CPU Cores (U54), Interrupt controller (PLIC),
Timer (CLINT), UART.
Diffstat (limited to 'cpukit/score/cpu/riscv/include/rtems/score/cpu.h')
-rw-r--r-- | cpukit/score/cpu/riscv/include/rtems/score/cpu.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h index f0f3da05da..88f7e7960c 100644 --- a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h +++ b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h @@ -481,7 +481,7 @@ static inline uint32_t _CPU_SMP_Get_current_processor( void ) "=&r" ( mhartid ) ); - return (uint32_t) mhartid; + return (uint32_t) mhartid - RISCV_BOOT_HARTID; } void _CPU_SMP_Send_interrupt( uint32_t target_processor_index ); |