powerpc: Simplify context switch

PowerPC cores with the SPE (Signal Processing Extension) have 64-bit
general-purpose registers.  The SPE context switch code has been merged
with the standard context switch code.  The context switch may use cache
operations to increase the performance.  It will be ensured that the
context is 32-byte aligned (PPC_DEFAULT_CACHE_LINE_SIZE).  This
increases the overall memory size of the context area in the thread
control block slightly.  The general-purpose registers GPR2 and GPR13
are no longer part of the context.  The BSP must initialize these
registers during startup (usually initialized by the __eabi() function).

The new BSP option BSP_USE_DATA_CACHE_BLOCK_TOUCH can be used to enable
the dcbt instruction in the context switch.

The new BSP option BSP_USE_SYNC_IN_CONTEXT_SWITCH can be used to enable
sync and isync instructions in the context switch.  This should be not
necessary in most cases.

1 files changed, 34 insertions, 42 deletions

diff --git a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/vectors.h b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/vectors.h
index 8eda3a1aaa..1a071c27c3 100644
--- a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/vectors.h
+++ b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/vectors.h
@@ -142,23 +142,15 @@ extern "C" {
 /** @} */
 
 #ifndef __SPE__
-  #define PPC_EXC_GPR_TYPE unsigned
-  #define PPC_EXC_GPR_SIZE 4
-  #define PPC_EXC_GPR_OFFSET(gpr) ((gpr) * PPC_EXC_GPR_SIZE + 36)
+  #define PPC_EXC_GPR_OFFSET(gpr) ((gpr) * PPC_GPR_SIZE + 36)
   #define PPC_EXC_VECTOR_PROLOGUE_OFFSET PPC_EXC_GPR_OFFSET(4)
-  #define PPC_EXC_GPR_LOAD lwz
-  #define PPC_EXC_GPR_STORE stw
   #define PPC_EXC_MINIMAL_FRAME_SIZE 96
   #define PPC_EXC_FRAME_SIZE 176
 #else
-  #define PPC_EXC_GPR_TYPE uint64_t
-  #define PPC_EXC_GPR_SIZE 8
   #define PPC_EXC_SPEFSCR_OFFSET 36
   #define PPC_EXC_ACC_OFFSET 40
-  #define PPC_EXC_GPR_OFFSET(gpr) ((gpr) * PPC_EXC_GPR_SIZE + 48)
+  #define PPC_EXC_GPR_OFFSET(gpr) ((gpr) * PPC_GPR_SIZE + 48)
   #define PPC_EXC_VECTOR_PROLOGUE_OFFSET (PPC_EXC_GPR_OFFSET(4) + 4)
-  #define PPC_EXC_GPR_LOAD evldd
-  #define PPC_EXC_GPR_STORE evstdd
   #define PPC_EXC_MINIMAL_FRAME_SIZE 160
   #define PPC_EXC_FRAME_SIZE 320
 #endif
@@ -268,38 +260,38 @@ typedef struct {
     uint32_t EXC_SPEFSCR;
     uint64_t EXC_ACC;
   #endif
-  PPC_EXC_GPR_TYPE GPR0;
-  PPC_EXC_GPR_TYPE GPR1;
-  PPC_EXC_GPR_TYPE GPR2;
-  PPC_EXC_GPR_TYPE GPR3;
-  PPC_EXC_GPR_TYPE GPR4;
-  PPC_EXC_GPR_TYPE GPR5;
-  PPC_EXC_GPR_TYPE GPR6;
-  PPC_EXC_GPR_TYPE GPR7;
-  PPC_EXC_GPR_TYPE GPR8;
-  PPC_EXC_GPR_TYPE GPR9;
-  PPC_EXC_GPR_TYPE GPR10;
-  PPC_EXC_GPR_TYPE GPR11;
-  PPC_EXC_GPR_TYPE GPR12;
-  PPC_EXC_GPR_TYPE GPR13;
-  PPC_EXC_GPR_TYPE GPR14;
-  PPC_EXC_GPR_TYPE GPR15;
-  PPC_EXC_GPR_TYPE GPR16;
-  PPC_EXC_GPR_TYPE GPR17;
-  PPC_EXC_GPR_TYPE GPR18;
-  PPC_EXC_GPR_TYPE GPR19;
-  PPC_EXC_GPR_TYPE GPR20;
-  PPC_EXC_GPR_TYPE GPR21;
-  PPC_EXC_GPR_TYPE GPR22;
-  PPC_EXC_GPR_TYPE GPR23;
-  PPC_EXC_GPR_TYPE GPR24;
-  PPC_EXC_GPR_TYPE GPR25;
-  PPC_EXC_GPR_TYPE GPR26;
-  PPC_EXC_GPR_TYPE GPR27;
-  PPC_EXC_GPR_TYPE GPR28;
-  PPC_EXC_GPR_TYPE GPR29;
-  PPC_EXC_GPR_TYPE GPR30;
-  PPC_EXC_GPR_TYPE GPR31;
+  PPC_GPR_TYPE GPR0;
+  PPC_GPR_TYPE GPR1;
+  PPC_GPR_TYPE GPR2;
+  PPC_GPR_TYPE GPR3;
+  PPC_GPR_TYPE GPR4;
+  PPC_GPR_TYPE GPR5;
+  PPC_GPR_TYPE GPR6;
+  PPC_GPR_TYPE GPR7;
+  PPC_GPR_TYPE GPR8;
+  PPC_GPR_TYPE GPR9;
+  PPC_GPR_TYPE GPR10;
+  PPC_GPR_TYPE GPR11;
+  PPC_GPR_TYPE GPR12;
+  PPC_GPR_TYPE GPR13;
+  PPC_GPR_TYPE GPR14;
+  PPC_GPR_TYPE GPR15;
+  PPC_GPR_TYPE GPR16;
+  PPC_GPR_TYPE GPR17;
+  PPC_GPR_TYPE GPR18;
+  PPC_GPR_TYPE GPR19;
+  PPC_GPR_TYPE GPR20;
+  PPC_GPR_TYPE GPR21;
+  PPC_GPR_TYPE GPR22;
+  PPC_GPR_TYPE GPR23;
+  PPC_GPR_TYPE GPR24;
+  PPC_GPR_TYPE GPR25;
+  PPC_GPR_TYPE GPR26;
+  PPC_GPR_TYPE GPR27;
+  PPC_GPR_TYPE GPR28;
+  PPC_GPR_TYPE GPR29;
+  PPC_GPR_TYPE GPR30;
+  PPC_GPR_TYPE GPR31;
   unsigned EXC_MSR;
   unsigned EXC_DAR;
 } BSP_Exception_frame;