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| author | Joel Sherrill <joel.sherrill@oarcorp.com> | 2012-06-11 13:37:29 -0500 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@oarcorp.com> | 2012-06-11 13:37:29 -0500 |
| commit | 2d7ae960bbdbc82f795814ee6c600e93200ddf4d (patch) | |
| tree | ad12bf1ac7f551a70f004a897a7246cf0b9ea716 /c/src/lib/libbsp/v850/gdbv850sim/make/custom/v850sim.cfg | |
| parent | powerpc/cpu.h: Define CPU_SIMPLE_VECTORED_INTERRUPTS and remove _CPU_ISR_Init... (diff) | |
| download | rtems-2d7ae960bbdbc82f795814ee6c600e93200ddf4d.tar.bz2 | |
v850 port: Initial addition with BSP for simulator in GDB
Port
+ v850 does not have appear to have any optimized bit scan instructions
+ v850 does have single instructions for wap u16 and u32
+ Code path optimization preferences set
+ Add BSP variants for each GCC CPU model flag and a README
- v850e1 variant does not work (fails during BSP initialization)
BSP for GDB v850 Simulator
+ linkcmds matches defaults in GDB simulator with RTEMS mods
+ crt1.c added from v850 newlib port for __main()
+ BSP exits cleanly
+ printk and console I/O work
+ uses clock tick from IDLE task
+ Tests not requiring real clock ISR work
Documentation
+ CPU Supplment chapter for v850 added
Diffstat (limited to 'c/src/lib/libbsp/v850/gdbv850sim/make/custom/v850sim.cfg')
| -rw-r--r-- | c/src/lib/libbsp/v850/gdbv850sim/make/custom/v850sim.cfg | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/c/src/lib/libbsp/v850/gdbv850sim/make/custom/v850sim.cfg b/c/src/lib/libbsp/v850/gdbv850sim/make/custom/v850sim.cfg new file mode 100644 index 0000000000..9dcc918423 --- /dev/null +++ b/c/src/lib/libbsp/v850/gdbv850sim/make/custom/v850sim.cfg @@ -0,0 +1,8 @@ +# +# Base Config file for the v850 GDB Simulator as v850 +# + +# This is the same as not specifying a CPU model flag. +CPU_CFLAGS = -mv850 + +include $(RTEMS_ROOT)/make/custom/v850sim.inc |