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author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-04-23 09:53:31 +0200 |
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committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-04-23 15:18:44 +0200 |
commit | 031df3914990db0336a0d386fb53558b05de467e (patch) | |
tree | 4661e22f0cdb3f9d06879f0194b77c75f62bac79 /bsps/powerpc/mpc8260ads/net/README | |
parent | bsps: Move interrupt controller support to bsps (diff) | |
download | rtems-031df3914990db0336a0d386fb53558b05de467e.tar.bz2 |
bsps: Move legacy network drivers to bsps
This patch is a part of the BSP source reorganization.
Update #3285.
Diffstat (limited to 'bsps/powerpc/mpc8260ads/net/README')
-rw-r--r-- | bsps/powerpc/mpc8260ads/net/README | 55 |
1 files changed, 55 insertions, 0 deletions
diff --git a/bsps/powerpc/mpc8260ads/net/README b/bsps/powerpc/mpc8260ads/net/README new file mode 100644 index 0000000000..d5722557c3 --- /dev/null +++ b/bsps/powerpc/mpc8260ads/net/README @@ -0,0 +1,55 @@ +Networking with HDLC +==================== + +Author: Andy Dachs <a.dachs@sstl.co.uk> +Date: 31st August 2001 +Surrey Satellite Technology Limited + + +The network support in this BSP is not Ethernet support. The +"network" referred to here is a point to point HDLC communication link. +The ADS board does have a 10/100 ethernet port and it would be nice to +get support for that added. + +My requirement is for a WAN so I need the ability to send IP frames over +HDLC. Ultimately this will end up as frame relay support but in the meantime +I'm simply wrapping up the IP packet inside an HDLC frame. There is no +addressing mechanism or mac address attached to the start of the frame. + +This is what is physically transmitted: +<FLAG><IP Frame><CRC><FLAG> + + +The physical link consists of four lines, +TX DATA : Data transmitted +TX CLOCK: Clock for transmitted data. Data source provides clock. +RX DATA : Received data +RX CLOCK: Clock for received data. Data sink accepts clock. + +To connect two entities you require a NULL modem arrangement, i.e. TX data +and Tx clock from one end go into RX data and Rx clock on the other end. + +The MPC8260ADS side of the link is implemented using SCC3 in HDLC mode. The +TX clock is generated by BRG4. The RX clock in input to the board on the CLK5 +input. I built a LVTTL to RS422 converter. + +The other end of the link is a Windows NT PC with WANic400 synchronous +communication card. We bought the card from ImageStream +(http://www.imagestream.com/WANic400.html). You also need the NT +drivers and a cable. There are other distributors but I found these +guys helpful - and they also do Linux drivers. + +The NT WANic driver has a number of modes, one of which is ethernet emulation. +This mode is what is needed to transport IP packets in HDLC frames. + +In libnetworking/net you will find a file called if_hdlcsubr.c containing +the hdlc_input and hdlc_output routines required by network.c. This file was +created by taking out the addressing mechanisms from if_ethersubr.c in the +same directory. There are probably neater ways to do this <any +contributions welcome here>. + + + + + + |