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author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-04-19 06:35:52 +0200 |
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committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-04-20 09:57:01 +0200 |
commit | 7632906fc290b652416ab59eb5fb49356c064ed6 (patch) | |
tree | ac036b1f95637e044e10138ceea8d2b56d80ec97 /bsps/m68k/mcf5329/clock/clock.c | |
parent | bsps: Move bspsmpgetcurrentprocessor.c to bsps (diff) | |
download | rtems-7632906fc290b652416ab59eb5fb49356c064ed6.tar.bz2 |
bsps: Move clock drivers to bsps
This patch is a part of the BSP source reorganization.
Update #3285.
Diffstat (limited to 'bsps/m68k/mcf5329/clock/clock.c')
-rw-r--r-- | bsps/m68k/mcf5329/clock/clock.c | 105 |
1 files changed, 105 insertions, 0 deletions
diff --git a/bsps/m68k/mcf5329/clock/clock.c b/bsps/m68k/mcf5329/clock/clock.c new file mode 100644 index 0000000000..5638238921 --- /dev/null +++ b/bsps/m68k/mcf5329/clock/clock.c @@ -0,0 +1,105 @@ +/* + * Use the last periodic interval timer (PIT2) as the system clock. + */ + +#include <rtems.h> +#include <rtems/timecounter.h> +#include <bsp.h> + +/* + * Use INTC1 base + */ +#define CLOCK_VECTOR (128+46) + +static rtems_timecounter_simple mcf5329_tc; + +static uint32_t mcf5329_tc_get(rtems_timecounter_simple *tc) +{ + return MCF_PIT3_PCNTR; +} + +static bool mcf5329_tc_is_pending(rtems_timecounter_simple *tc) +{ + return (MCF_PIT3_PCSR & MCF_PIT_PCSR_PIF) != 0; +} + +static uint32_t mcf5329_tc_get_timecount(struct timecounter *tc) +{ + return rtems_timecounter_simple_downcounter_get( + tc, + mcf5329_tc_get, + mcf5329_tc_is_pending + ); +} + +static void mcf5329_tc_at_tick(rtems_timecounter_simple *tc) +{ + MCF_PIT3_PCSR |= MCF_PIT_PCSR_PIF; +} + +static void mcf5329_tc_tick(void) +{ + rtems_timecounter_simple_downcounter_tick( + &mcf5329_tc, + mcf5329_tc_get, + mcf5329_tc_at_tick + ); +} + +/* + * Attach clock interrupt handler + */ +#define Clock_driver_support_install_isr( _new ) \ + set_vector(_new, CLOCK_VECTOR, 1) + +/* + * Turn off the clock + */ +#define Clock_driver_support_shutdown_hardware() \ + do { \ + MCF_PIT3_PCSR &= ~MCF_PIT_PCSR_EN; \ + } while (0) + +/* + * Set up the clock hardware + * + * We need to have 1 interrupt every rtems_configuration_get_microseconds_per_tick() + */ +static void Clock_driver_support_initialize_hardware(void) +{ + int level; + uint32_t pmr; + uint32_t preScaleCode = 0; + uint32_t clk = bsp_get_BUS_clock_speed(); + uint32_t tps = 1000000 / rtems_configuration_get_microseconds_per_tick(); + + while (preScaleCode < 15) { + pmr = (clk >> preScaleCode) / tps; + if (pmr < (1 << 15)) + break; + preScaleCode++; + } + MCF_INTC1_ICR46 = MCF_INTC_ICR_IL(PIT3_IRQ_LEVEL); + + rtems_interrupt_disable(level); + MCF_INTC1_IMRH &= ~MCF_INTC_IMRH_INT_MASK46; + MCF_PIT3_PCSR &= ~MCF_PIT_PCSR_EN; + rtems_interrupt_enable(level); + + MCF_PIT3_PCSR = MCF_PIT_PCSR_PRE(preScaleCode) | + MCF_PIT_PCSR_OVW | MCF_PIT_PCSR_PIE | MCF_PIT_PCSR_RLD; + MCF_PIT3_PMR = pmr; + MCF_PIT3_PCSR = MCF_PIT_PCSR_PRE(preScaleCode) | + MCF_PIT_PCSR_PIE | MCF_PIT_PCSR_RLD | MCF_PIT_PCSR_EN; + + rtems_timecounter_simple_install( + &mcf5329_tc, + clk >> preScaleCode, + pmr, + mcf5329_tc_get_timecount + ); +} + +#define Clock_driver_timecounter_tick() mcf5329_tc_tick() + +#include "../../../shared/dev/clock/clockimpl.h" |