diff options
| author | shashvatjain <shashvatjain2002@gmail.com> | 2018-11-08 06:17:49 +0530 |
|---|---|---|
| committer | Gedare Bloom <gedare@rtems.org> | 2018-11-09 12:51:08 -0500 |
| commit | b3c624d8886db6e791babe5e0d4f8b28992e000a (patch) | |
| tree | a6b9e8b739a5b794b4e51bcd8bcf99e92de87583 /bsps/arm/altera-cyclone-v/include/bsp/irq.h | |
| parent | Include missing <rtems/score/thread.h> (diff) | |
| download | rtems-b3c624d8886db6e791babe5e0d4f8b28992e000a.tar.bz2 | |
arm/altera cyclone v: Update Doxygen (GCI 2018)
Diffstat (limited to 'bsps/arm/altera-cyclone-v/include/bsp/irq.h')
| -rw-r--r-- | bsps/arm/altera-cyclone-v/include/bsp/irq.h | 22 |
1 files changed, 21 insertions, 1 deletions
diff --git a/bsps/arm/altera-cyclone-v/include/bsp/irq.h b/bsps/arm/altera-cyclone-v/include/bsp/irq.h index c136500415..ad0e4dfd61 100644 --- a/bsps/arm/altera-cyclone-v/include/bsp/irq.h +++ b/bsps/arm/altera-cyclone-v/include/bsp/irq.h @@ -1,3 +1,11 @@ +/** + * @file + * + * @ingroup altera-cyclone-v_interrupt + * + * @brief Interrupt definitions. + */ + /* * Copyright (c) 2013 embedded brains GmbH. All rights reserved. * @@ -28,6 +36,18 @@ extern "C" { #endif /* __cplusplus */ +/** + * @defgroup altera-cyclone-v_interrupt Interrupt Support + * + * @ingroup arm_altera-cyclone-v + * + * @ingroup bsp_interrupt + * + * @brief Interrupt Support for Altera Cyclone V + * + * @{ + */ + /* Use interrupt IDs as defined in alt_interrupt_common.h */ #define BSP_INTERRUPT_VECTOR_MIN ALT_INT_INTERRUPT_SGI0 #define BSP_INTERRUPT_VECTOR_MAX ALT_INT_INTERRUPT_RAM_ECC_UNCORRECTED_IRQ @@ -38,4 +58,4 @@ extern "C" { #endif /* ASM */ -#endif /* LIBBSP_ARM_ALTERA_CYCLONE_V_IRQ_H */
\ No newline at end of file +#endif /* LIBBSP_ARM_ALTERA_CYCLONE_V_IRQ_H */ |