1 files changed, 73 insertions, 2 deletions

diff --git a/rtemslwip/zynqmp/xparameters_ps.h b/rtemslwip/zynqmp/xparameters_ps.h
index 427ae77..0defb9d 100644
--- a/rtemslwip/zynqmp/xparameters_ps.h
+++ b/rtemslwip/zynqmp/xparameters_ps.h
@@ -36,8 +36,6 @@
 #define XPAR_XEMACPS_3_INTR   XPS_GEM3_INT_ID
 #define XPAR_XEMACPS_3_WAKE_INTR  XPS_GEM3_WAKE_INT_ID
 
-#define XPS_SYS_CTRL_BASEADDR 0xFF180000U
-
 #define XPS_GEM0_INT_ID     ( 57U + 32U )
 #define XPS_GEM0_WAKE_INT_ID    ( 58U + 32U )
 #define XPS_GEM1_INT_ID     ( 59U + 32U )
@@ -65,4 +63,77 @@
 #define XPAR_PSU_ETHERNET_3_INTERRUPT_ID   0x403FU
 #define XPAR_PSU_ETHERNET_3_WAKE_INTERRUPT_ID 0x403FU
 
+/* Platform specific definitions */
+#define PLATFORM_ZYNQMP
+
+/* Definitions for driver EMACPS */
+#define XPAR_XEMACPS_NUM_INSTANCES 4
+
+/* Definitions for peripheral PSU_ETHERNET_0 */
+#define XPAR_PSU_ETHERNET_0_DEVICE_ID 0
+#define XPAR_PSU_ETHERNET_0_BASEADDR 0xFF0B0000
+#define XPAR_PSU_ETHERNET_0_ENET_CLK_FREQ_HZ 124998749
+#define XPAR_PSU_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0 12
+#define XPAR_PSU_ETHERNET_0_ENET_SLCR_1000MBPS_DIV1 1
+#define XPAR_PSU_ETHERNET_0_ENET_SLCR_100MBPS_DIV0 60
+#define XPAR_PSU_ETHERNET_0_ENET_SLCR_100MBPS_DIV1 1
+#define XPAR_PSU_ETHERNET_0_ENET_SLCR_10MBPS_DIV0 60
+#define XPAR_PSU_ETHERNET_0_ENET_SLCR_10MBPS_DIV1 10
+#define XPAR_PSU_ETHERNET_0_IS_CACHE_COHERENT 0
+#define XPAR_PSU_ETHERNET_0_REF_CLK GEM0_REF
+#define XPAR_XEMACPS_0_IS_CACHE_COHERENT 0
+#define XPAR_XEMACPS_0_ENET_CLK_FREQ_HZ 124998749
+#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV1 1
+#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 1
+#define XPAR_XEMACPS_0_DEVICE_ID XPAR_PSU_ETHERNET_0_DEVICE_ID
+#define XPAR_XEMACPS_0_BASEADDR 0xFF0B0000
+
+/* Definitions for peripheral PSU_ETHERNET_1 */
+#define XPAR_PSU_ETHERNET_1_DEVICE_ID 1
+#define XPAR_PSU_ETHERNET_1_BASEADDR 0xFF0C0000
+#define XPAR_PSU_ETHERNET_1_ENET_CLK_FREQ_HZ 124998749
+#define XPAR_PSU_ETHERNET_1_ENET_SLCR_1000MBPS_DIV0 12
+#define XPAR_PSU_ETHERNET_1_ENET_SLCR_1000MBPS_DIV1 1
+#define XPAR_PSU_ETHERNET_1_ENET_SLCR_100MBPS_DIV0 60
+#define XPAR_PSU_ETHERNET_1_ENET_SLCR_100MBPS_DIV1 1
+#define XPAR_PSU_ETHERNET_1_ENET_SLCR_10MBPS_DIV0 60
+#define XPAR_PSU_ETHERNET_1_ENET_SLCR_10MBPS_DIV1 10
+#define XPAR_PSU_ETHERNET_1_IS_CACHE_COHERENT 0
+#define XPAR_PSU_ETHERNET_1_REF_CLK GEM1_REF
+#define XPAR_XEMACPS_1_IS_CACHE_COHERENT 0
+#define XPAR_XEMACPS_1_DEVICE_ID XPAR_PSU_ETHERNET_1_DEVICE_ID
+#define XPAR_XEMACPS_1_BASEADDR 0xFF0C0000
+
+/* Definitions for peripheral PSU_ETHERNET_2 */
+#define XPAR_PSU_ETHERNET_2_DEVICE_ID 1
+#define XPAR_PSU_ETHERNET_2_BASEADDR 0xFF0D0000
+#define XPAR_PSU_ETHERNET_2_ENET_CLK_FREQ_HZ 124998749
+#define XPAR_PSU_ETHERNET_2_ENET_SLCR_1000MBPS_DIV0 12
+#define XPAR_PSU_ETHERNET_2_ENET_SLCR_1000MBPS_DIV1 1
+#define XPAR_PSU_ETHERNET_2_ENET_SLCR_100MBPS_DIV0 60
+#define XPAR_PSU_ETHERNET_2_ENET_SLCR_100MBPS_DIV1 1
+#define XPAR_PSU_ETHERNET_2_ENET_SLCR_10MBPS_DIV0 60
+#define XPAR_PSU_ETHERNET_2_ENET_SLCR_10MBPS_DIV1 10
+#define XPAR_PSU_ETHERNET_2_IS_CACHE_COHERENT 0
+#define XPAR_PSU_ETHERNET_2_REF_CLK GEM2_REF
+#define XPAR_XEMACPS_2_DEVICE_ID XPAR_PSU_ETHERNET_2_DEVICE_ID
+#define XPAR_XEMACPS_2_BASEADDR 0xFF0D0000
+
+/* Definitions for peripheral PSU_ETHERNET_3 */
+#define XPAR_PSU_ETHERNET_3_DEVICE_ID 0
+#define XPAR_PSU_ETHERNET_3_BASEADDR 0xFF0E0000
+#define XPAR_PSU_ETHERNET_3_ENET_CLK_FREQ_HZ 124998749
+#define XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV0 12
+#define XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV1 1
+#define XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV0 60
+#define XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV1 1
+#define XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV0 60
+#define XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV1 10
+#define XPAR_PSU_ETHERNET_3_IS_CACHE_COHERENT 0
+#define XPAR_PSU_ETHERNET_3_REF_CLK GEM3_REF
+#define XPAR_XEMACPS_3_DEVICE_ID XPAR_PSU_ETHERNET_3_DEVICE_ID
+#define XPAR_XEMACPS_3_BASEADDR 0xFF0E0000
+
+#define XPAR_SCUGIC_0_DIST_BASEADDR 0xF9010000U
+
 #endif