diff options
Diffstat (limited to 'freebsd/sys/pci/if_rlreg.h')
| -rw-r--r-- | freebsd/sys/pci/if_rlreg.h | 29 |
1 files changed, 16 insertions, 13 deletions
diff --git a/freebsd/sys/pci/if_rlreg.h b/freebsd/sys/pci/if_rlreg.h index be89c4f5..b0de60f4 100644 --- a/freebsd/sys/pci/if_rlreg.h +++ b/freebsd/sys/pci/if_rlreg.h @@ -145,6 +145,7 @@ #define RL_PMCH 0x006F /* 8 bits */ #define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */ #define RL_INTRMOD 0x00E2 /* 16 bits */ +#define RL_MISC 0x00F0 /* * TX config register bits @@ -163,7 +164,6 @@ #define RL_LOOPTEST_ON_CPLUS 0x00060000 /* Known revision codes. */ - #define RL_HWREV_8169 0x00000000 #define RL_HWREV_8169S 0x00800000 #define RL_HWREV_8110S 0x04000000 @@ -189,8 +189,13 @@ #define RL_HWREV_8105E 0x40800000 #define RL_HWREV_8105E_SPIN1 0x40C00000 #define RL_HWREV_8402 0x44000000 +#define RL_HWREV_8106E 0x44800000 #define RL_HWREV_8168F 0x48000000 #define RL_HWREV_8411 0x48800000 +#define RL_HWREV_8168G 0x4C000000 +#define RL_HWREV_8168EP 0x50000000 +#define RL_HWREV_8168GU 0x50800000 +#define RL_HWREV_8411B 0x5C800000 #define RL_HWREV_8139 0x60000000 #define RL_HWREV_8139A 0x70000000 #define RL_HWREV_8139AG 0x70800000 @@ -282,8 +287,10 @@ #define RL_RXCFG_RX_RUNT 0x00000010 #define RL_RXCFG_RX_ERRPKT 0x00000020 #define RL_RXCFG_WRAP 0x00000080 +#define RL_RXCFG_EARLYOFFV2 0x00000800 #define RL_RXCFG_MAXDMA 0x00000700 #define RL_RXCFG_BUFSZ 0x00001800 +#define RL_RXCFG_EARLYOFF 0x00003800 #define RL_RXCFG_FIFOTHRESH 0x0000E000 #define RL_RXCFG_EARLYTHRESH 0x07000000 @@ -324,8 +331,8 @@ #define RL_RXSTAT_INDIV 0x00004000 #define RL_RXSTAT_MULTI 0x00008000 #define RL_RXSTAT_LENMASK 0xFFFF0000 +#define RL_RXSTAT_UNFINISHED 0x0000FFF0 /* DMA still in progress */ -#define RL_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */ /* * Command register. */ @@ -356,6 +363,7 @@ #define RL_PARA7C 0x7C #define RL_PARA7C_DEF 0xcb38de43 #define RL_PARA7C_RETUNE 0xfb38de03 + /* * EEPROM control register */ @@ -468,11 +476,9 @@ */ /* RL_DUMPSTATS_LO register */ - #define RL_DUMPSTATS_START 0x00000008 /* Transmit start register */ - #define RL_TXSTART_SWI 0x01 /* generate TX interrupt */ #define RL_TXSTART_START 0x40 /* start normal queue transmit */ #define RL_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */ @@ -491,7 +497,6 @@ #define RL_BUSWIDTH_64BITS 0x08 /* C+ mode command register */ - #define RL_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */ #define RL_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */ #define RL_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */ @@ -509,7 +514,6 @@ #define RL_CPLUSCMD_BIST_ENB 0x8000 /* 8168C/CP */ /* C+ early transmit threshold */ - #define RL_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */ /* Timer interrupt register */ @@ -523,7 +527,6 @@ /* * Gigabit PHY access register (8169 only) */ - #define RL_PHYAR_PHYDATA 0x0000FFFF #define RL_PHYAR_PHYREG 0x001F0000 #define RL_PHYAR_BUSY 0x80000000 @@ -554,7 +557,6 @@ * For reception, there's just one large buffer where the chip stores * all received packets. */ - #define RL_RX_BUF_SZ RL_RXBUF_64 #define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13)) #define RL_TX_LIST_CNT 4 @@ -637,11 +639,10 @@ struct rl_hwrev { /* * RX/TX descriptor definition. When large send mode is enabled, the - * lower 11 bits of the TX rl_cmd word are used to hold the MSS, and + * lower 11 bits of the TX rl_cmdstat word are used to hold the MSS, and * the checksum offload bits are disabled. The structure layout is * the same for RX and TX descriptors */ - struct rl_desc { uint32_t rl_cmdstat; uint32_t rl_vlanctl; @@ -674,7 +675,6 @@ struct rl_desc { * Error bits are valid only on the last descriptor of a frame * (i.e. RL_TDESC_CMD_EOF == 1) */ - #define RL_TDESC_STAT_COLCNT 0x000F0000 /* collision count */ #define RL_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */ #define RL_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */ @@ -686,7 +686,6 @@ struct rl_desc { /* * RX descriptor cmd/vlan definitions */ - #define RL_RDESC_CMD_EOR 0x40000000 #define RL_RDESC_CMD_OWN 0x80000000 #define RL_RDESC_CMD_BUFLEN 0x00001FFF @@ -777,7 +776,7 @@ struct rl_stats { #define RL_TX_DESC_CNT RL_8169_TX_DESC_CNT #define RL_RX_DESC_CNT RL_8169_RX_DESC_CNT #define RL_RX_JUMBO_DESC_CNT RL_RX_DESC_CNT -#define RL_NTXSEGS 32 +#define RL_NTXSEGS 35 #define RL_RING_ALIGN 256 #define RL_DUMP_ALIGN 64 @@ -877,6 +876,7 @@ struct rl_softc { bus_dma_tag_t rl_parent_tag; uint8_t rl_type; const struct rl_hwrev *rl_hwrev; + uint32_t rl_macrev; int rl_eecmd_read; int rl_eewidth; int rl_expcap; @@ -929,6 +929,9 @@ struct rl_softc { #define RL_FLAG_WAIT_TXPOLL 0x00004000 #define RL_FLAG_CMDSTOP_WAIT_TXQ 0x00008000 #define RL_FLAG_WOL_MANLINK 0x00010000 +#define RL_FLAG_EARLYOFF 0x00020000 +#define RL_FLAG_EARLYOFFV2 0x00040000 +#define RL_FLAG_RXDV_GATED 0x00080000 #define RL_FLAG_PCIE 0x40000000 #define RL_FLAG_LINK 0x80000000 }; |