diff options
Diffstat (limited to 'freebsd/sys/dev/bge/if_bgereg.h')
| -rw-r--r-- | freebsd/sys/dev/bge/if_bgereg.h | 25 |
1 files changed, 24 insertions, 1 deletions
diff --git a/freebsd/sys/dev/bge/if_bgereg.h b/freebsd/sys/dev/bge/if_bgereg.h index 09ced543..acac8b28 100644 --- a/freebsd/sys/dev/bge/if_bgereg.h +++ b/freebsd/sys/dev/bge/if_bgereg.h @@ -331,6 +331,7 @@ #define BGE_CHIPID_BCM5717_B0 0x05717100 #define BGE_CHIPID_BCM5719_A0 0x05719000 #define BGE_CHIPID_BCM5720_A0 0x05720000 +#define BGE_CHIPID_BCM5762_A0 0x05762000 #define BGE_CHIPID_BCM57765_A0 0x57785000 #define BGE_CHIPID_BCM57765_B0 0x57785100 @@ -357,6 +358,7 @@ #define BGE_ASICREV_BCM5719 0x5719 #define BGE_ASICREV_BCM5720 0x5720 #define BGE_ASICREV_BCM5761 0x5761 +#define BGE_ASICREV_BCM5762 0x5762 #define BGE_ASICREV_BCM5784 0x5784 #define BGE_ASICREV_BCM5785 0x5785 #define BGE_ASICREV_BCM57765 0x57785 @@ -378,6 +380,7 @@ #define BGE_CHIPREV_5717_AX 0x57170 #define BGE_CHIPREV_5717_BX 0x57171 #define BGE_CHIPREV_5761_AX 0x57611 +#define BGE_CHIPREV_57765_AX 0x577850 #define BGE_CHIPREV_5784_AX 0x57841 /* PCI DMA Read/Write Control register */ @@ -1289,6 +1292,7 @@ #define BGE_CPMU_MUTEX_REQ 0x365C #define BGE_CPMU_MUTEX_GNT 0x3660 #define BGE_CPMU_PHY_STRAP 0x3664 +#define BGE_CPMU_PADRNG_CTL 0x3668 /* Central Power Management Unit (CPMU) register */ #define BGE_CPMU_CTRL_LINK_IDLE_MODE 0x00000200 @@ -1328,6 +1332,9 @@ /* CPMU GPHY Strap register */ #define BGE_CPMU_PHY_STRAP_IS_SERDES 0x00000020 +/* CPMU Padring Control register */ +#define BGE_CPMU_PADRNG_CTL_RDIV2 0x00040000 + /* * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) */ @@ -1539,6 +1546,8 @@ */ #define BGE_RDMA_MODE 0x4800 #define BGE_RDMA_STATUS 0x4804 +#define BGE_RDMA_RSRVCTRL_REG2 0x4890 +#define BGE_RDMA_LSO_CRPTEN_CTRL_REG2 0x48A0 #define BGE_RDMA_RSRVCTRL 0x4900 #define BGE_RDMA_LSO_CRPTEN_CTRL 0x4910 @@ -1586,6 +1595,8 @@ #define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 0x00020000 #define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K 0x00030000 #define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K 0x000C0000 +#define BGE_RDMA_TX_LENGTH_WA_5719 0x02000000 +#define BGE_RDMA_TX_LENGTH_WA_5720 0x00200000 /* BD Read DMA Mode register */ #define BGE_RDMA_BD_MODE 0x4A00 @@ -1603,6 +1614,9 @@ #define BGE_RDMA_NON_LSO_MODE_RESET 0x00000001 #define BGE_RDMA_NON_LSO_MODE_ENABLE 0x00000002 +#define BGE_RDMA_LENGTH 0x4BE0 +#define BGE_NUM_RDMA_CHANNELS 4 + /* * Write DMA control registers */ @@ -2444,6 +2458,8 @@ struct bge_status_block { #define BCOM_DEVICEID_BCM5721 0x1659 #define BCOM_DEVICEID_BCM5722 0x165A #define BCOM_DEVICEID_BCM5723 0x165B +#define BCOM_DEVICEID_BCM5725 0x1643 +#define BCOM_DEVICEID_BCM5727 0x16F3 #define BCOM_DEVICEID_BCM5750 0x1676 #define BCOM_DEVICEID_BCM5750M 0x167C #define BCOM_DEVICEID_BCM5751 0x1677 @@ -2463,6 +2479,7 @@ struct bge_status_block { #define BCOM_DEVICEID_BCM5761E 0x1680 #define BCOM_DEVICEID_BCM5761S 0x1688 #define BCOM_DEVICEID_BCM5761SE 0x1689 +#define BCOM_DEVICEID_BCM5762 0x1687 #define BCOM_DEVICEID_BCM5764 0x1684 #define BCOM_DEVICEID_BCM5780 0x166A #define BCOM_DEVICEID_BCM5780S 0x166B @@ -2485,11 +2502,16 @@ struct bge_status_block { #define BCOM_DEVICEID_BCM57760 0x1690 #define BCOM_DEVICEID_BCM57761 0x16B0 #define BCOM_DEVICEID_BCM57762 0x1682 +#define BCOM_DEVICEID_BCM57764 0x1642 #define BCOM_DEVICEID_BCM57765 0x16B4 #define BCOM_DEVICEID_BCM57766 0x1686 +#define BCOM_DEVICEID_BCM57767 0x1683 #define BCOM_DEVICEID_BCM57780 0x1692 #define BCOM_DEVICEID_BCM57781 0x16B1 +#define BCOM_DEVICEID_BCM57782 0x16B7 #define BCOM_DEVICEID_BCM57785 0x16B5 +#define BCOM_DEVICEID_BCM57786 0x16B3 +#define BCOM_DEVICEID_BCM57787 0x1641 #define BCOM_DEVICEID_BCM57788 0x1691 #define BCOM_DEVICEID_BCM57790 0x1694 #define BCOM_DEVICEID_BCM57791 0x16B2 @@ -2829,7 +2851,7 @@ struct bge_gib { */ #define BGE_NSEG_JUMBO 4 -#define BGE_NSEG_NEW 32 +#define BGE_NSEG_NEW 35 #define BGE_TSOSEG_SZ 4096 /* Maximum DMA address for controllers that have 40bit DMA address bug. */ @@ -2982,6 +3004,7 @@ struct bge_softc { #define BGE_FLAG_SHORT_DMA_BUG 0x08000000 #define BGE_FLAG_4K_RDMA_BUG 0x10000000 #define BGE_FLAG_MBOX_REORDER 0x20000000 +#define BGE_FLAG_RDMA_BUG 0x40000000 uint32_t bge_mfw_flags; /* Management F/W flags */ #define BGE_MFW_ON_RXCPU 0x00000001 #define BGE_MFW_ON_APE 0x00000002 |