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| author | Kevin Kirspel <kevin-kirspel@idexx.com> | 2017-01-30 11:58:24 -0500 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2017-02-14 09:37:12 +0100 |
| commit | 5382f639805a28e9596e3e68a8877aa7c0dde52a (patch) | |
| tree | 863290d7edb00d7c30c0eb8778c87e9ffe20c87e | |
| parent | Add ordered Nexus devices (diff) | |
| download | rtems-libbsd-5382f639805a28e9596e3e68a8877aa7c0dde52a.tar.bz2 | |
Add support for LPC32XX cache
| -rwxr-xr-x[-rw-r--r--] | rtemsbsd/include/machine/rtems-bsd-cache.h | 7 |
1 files changed, 2 insertions, 5 deletions
diff --git a/rtemsbsd/include/machine/rtems-bsd-cache.h b/rtemsbsd/include/machine/rtems-bsd-cache.h index b8c4ce7e..bd496f9d 100644..100755 --- a/rtemsbsd/include/machine/rtems-bsd-cache.h +++ b/rtemsbsd/include/machine/rtems-bsd-cache.h @@ -42,15 +42,12 @@ #include <bsp.h> -#if defined(LIBBSP_ARM_LPC24XX_BSP_H) +#if defined(LIBBSP_ARM_LPC24XX_BSP_H) || (defined(LIBBSP_ARM_LPC32XX_BSP_H) && defined(LPC32XX_DISABLE_MMU)) /* No cache */ #elif defined(LIBBSP_ARM_ALTERA_CYCLONE_V_BSP_H) || \ - defined(LIBBSP_ARM_XILINX_ZYNQ_BSP_H) + defined(LIBBSP_ARM_XILINX_ZYNQ_BSP_H) || (defined(LIBBSP_ARM_LPC32XX_BSP_H) && !defined(LPC32XX_DISABLE_MMU)) /* With cache, no coherency support in hardware */ #define CPU_DATA_CACHE_ALIGNMENT 32 -#elif defined(LIBBSP_ARM_LPC32XX_BSP_H) - /* With cache, no coherency support in hardware */ - #include <libcpu/cache.h> #elif defined(__GEN83xx_BSP_h) /* With cache, coherency support in hardware */ #endif |