diff options
| author | Christian Mauderer <christian.mauderer@embedded-brains.de> | 2023-08-11 07:37:35 +0200 |
|---|---|---|
| committer | Christian Mauderer <christian.mauderer@embedded-brains.de> | 2023-08-21 09:17:02 +0200 |
| commit | 3393edcb4b863ad41931107fe6dcaf16d560956e (patch) | |
| tree | 438a4f7aa1da81bd0021878b24dcc9f7d0c0d971 | |
| parent | imx: Enable GPIO driver for imxrt too (diff) | |
| download | rtems-libbsd-3393edcb4b863ad41931107fe6dcaf16d560956e.tar.bz2 | |
bsp/imxrt: Enable cache handling
The BSP needs the CPU_DATA_CACHE_ALIGNMENT set to enable correct cache
handling in libbsd. Otherwise for example USB doesn't work reliable.
| -rwxr-xr-x | rtemsbsd/include/machine/rtems-bsd-cache.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/rtemsbsd/include/machine/rtems-bsd-cache.h b/rtemsbsd/include/machine/rtems-bsd-cache.h index 73b55e25..e292b216 100755 --- a/rtemsbsd/include/machine/rtems-bsd-cache.h +++ b/rtemsbsd/include/machine/rtems-bsd-cache.h @@ -45,7 +45,7 @@ #if defined(LIBBSP_ARM_LPC24XX_BSP_H) || (defined(LIBBSP_ARM_LPC32XX_BSP_H) && defined(LPC32XX_DISABLE_MMU)) /* No cache */ #elif defined(LIBBSP_ARM_ALTERA_CYCLONE_V_BSP_H) || \ - defined(LIBBSP_ARM_XILINX_ZYNQ_BSP_H) || (defined(LIBBSP_ARM_LPC32XX_BSP_H) && !defined(LPC32XX_DISABLE_MMU)) || defined(LIBBSP_ARM_IMX_BSP_H) + defined(LIBBSP_ARM_XILINX_ZYNQ_BSP_H) || (defined(LIBBSP_ARM_LPC32XX_BSP_H) && !defined(LPC32XX_DISABLE_MMU)) || defined(LIBBSP_ARM_IMX_BSP_H) || defined(LIBBSP_ARM_IMXRT_BSP_H) /* With cache, no coherency support in hardware */ #define CPU_DATA_CACHE_ALIGNMENT 32 #elif defined(__GEN83xx_BSP_h) |