summaryrefslogtreecommitdiffstats
path: root/spec/dev/grlib/if/grethgbit.yml
diff options
context:
space:
mode:
Diffstat (limited to 'spec/dev/grlib/if/grethgbit.yml')
-rw-r--r--spec/dev/grlib/if/grethgbit.yml88
1 files changed, 44 insertions, 44 deletions
diff --git a/spec/dev/grlib/if/grethgbit.yml b/spec/dev/grlib/if/grethgbit.yml
index 2989e85d..2313fa44 100644
--- a/spec/dev/grlib/if/grethgbit.yml
+++ b/spec/dev/grlib/if/grethgbit.yml
@@ -66,121 +66,121 @@ register-block-size: 48
registers:
- bits:
- default:
- - access: [r]
+ - properties: [r]
brief: null
description: null
name: 'EA'
start: 31
width: 1
- - access: [r]
+ - properties: [r]
brief: null
description: null
name: 'BS'
start: 28
width: 3
- - access: [r]
+ - properties: [r]
brief: null
description: null
name: 'GA'
start: 27
width: 1
- - access: [r]
+ - properties: [r]
brief: null
description: null
name: 'MA'
start: 26
width: 1
- - access: [r]
+ - properties: [r]
brief: null
description: null
name: 'MC'
start: 25
width: 1
- - access: [r, w]
+ - properties: [r, w]
brief: null
description: null
name: 'ED'
start: 14
width: 1
- - access: [r, w]
+ - properties: [r, w]
brief: null
description: null
name: 'RD'
start: 13
width: 1
- - access: [r, w]
+ - properties: [r, w]
brief: null
description: null
name: 'DD'
start: 12
width: 1
- - access: [r, w]
+ - properties: [r, w]
brief: null
description: null
name: 'ME'
start: 11
width: 1
- - access: [r, w]
+ - properties: [r, w]
brief: null
description: null
name: 'PI'
start: 10
width: 1
- - access: [r, w]
+ - properties: [r, w]
brief: null
description: null
name: 'BM'
start: 9
width: 1
- - access: [r, w]
+ - properties: [r, w]
brief: null
description: null
name: 'GB'
start: 8
width: 1
- - access: [r, w]
+ - properties: [r, w]
brief: null
description: null
name: 'SP'
start: 7
width: 1
- - access: [r, w1c]
+ - properties: [r, w1c]
brief: null
description: null
name: 'RS'
start: 6
width: 1
- - access: [r, w]
+ - properties: [r, w]
brief: null
description: null
name: 'PM'
start: 5
width: 1
- - access: [r, w]
+ - properties: [r, w]
brief: null
description: null
name: 'FD'
start: 4
width: 1
- - access: [r, w]
+ - properties: [r, w]
brief: null
description: null
name: 'RI'
start: 3
width: 1
- - access: [r, w]
+ - properties: [r, w]
brief: null
description: null
name: 'TI'
start: 2
width: 1
- - access: [r, w]
+ - properties: [r, w]
brief: null
description: null
name: 'RE'
start: 1
width: 1
- - access: [r, w]
+ - properties: [r, w]
brief: null
description: null
name: 'TE'
@@ -194,55 +194,55 @@ registers:
width: 32
- bits:
- default:
- - access: [r, w1c]
+ - properties: [r, w1c]
brief: null
description: null
name: 'PS'
start: 8
width: 1
- - access: [r, w1c]
+ - properties: [r, w1c]
brief: null
description: null
name: 'IA'
start: 7
width: 1
- - access: [r, w1c]
+ - properties: [r, w1c]
brief: null
description: null
name: 'TS'
start: 6
width: 1
- - access: [r, w1c]
+ - properties: [r, w1c]
brief: null
description: null
name: 'TA'
start: 5
width: 1
- - access: [r, w1c]
+ - properties: [r, w1c]
brief: null
description: null
name: 'RA'
start: 4
width: 1
- - access: [r, w1c]
+ - properties: [r, w1c]
brief: null
description: null
name: 'TI'
start: 3
width: 1
- - access: [r, w1c]
+ - properties: [r, w1c]
brief: null
description: null
name: 'RI'
start: 2
width: 1
- - access: [r, w1c]
+ - properties: [r, w1c]
brief: null
description: null
name: 'TE'
start: 1
width: 1
- - access: [r, w1c]
+ - properties: [r, w1c]
brief: null
description: null
name: 'RE'
@@ -256,7 +256,7 @@ registers:
width: 32
- bits:
- default:
- - access: [r, w]
+ - properties: [r, w]
brief: null
description: null
name: 'MSB'
@@ -270,7 +270,7 @@ registers:
width: 32
- bits:
- default:
- - access: [r, w]
+ - properties: [r, w]
brief: null
description: null
name: 'LSB'
@@ -284,43 +284,43 @@ registers:
width: 32
- bits:
- default:
- - access: [r, w]
+ - properties: [r, w]
brief: null
description: null
name: 'DATA'
start: 16
width: 16
- - access: [r, w]
+ - properties: [r, w]
brief: null
description: null
name: 'PHYADDR'
start: 11
width: 5
- - access: [r, w]
+ - properties: [r, w]
brief: null
description: null
name: 'REGADDR'
start: 6
width: 5
- - access: [r]
+ - properties: [r]
brief: null
description: null
name: 'BU'
start: 3
width: 1
- - access: [r]
+ - properties: [r]
brief: null
description: null
name: 'LF'
start: 2
width: 1
- - access: [r, w]
+ - properties: [r, w]
brief: null
description: null
name: 'RD'
start: 1
width: 1
- - access: [r, w]
+ - properties: [r, w]
brief: null
description: null
name: 'WR'
@@ -334,13 +334,13 @@ registers:
width: 32
- bits:
- default:
- - access: [r, w]
+ - properties: [r, w]
brief: null
description: null
name: 'BASEADDR'
start: 10
width: 22
- - access: [r, w]
+ - properties: [r, w]
brief: null
description: null
name: 'DESCPNT'
@@ -354,13 +354,13 @@ registers:
width: 32
- bits:
- default:
- - access: [r, w]
+ - properties: [r, w]
brief: null
description: null
name: 'BASEADDR'
start: 10
width: 22
- - access: [r, w]
+ - properties: [r, w]
brief: null
description: null
name: 'DESCPNT'
@@ -374,7 +374,7 @@ registers:
width: 32
- bits:
- default:
- - access: [r, w]
+ - properties: [r, w]
brief: null
description: null
name: 'MSB'
@@ -388,7 +388,7 @@ registers:
width: 32
- bits:
- default:
- - access: [r, w]
+ - properties: [r, w]
brief: null
description: null
name: 'LSB'