diff options
| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2021-07-29 09:46:13 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2021-08-02 07:23:41 +0200 |
| commit | 353a102466453147dee9078ef7438316e1849267 (patch) | |
| tree | ab25e7f4e2f3b6a7a90dfac2778fee753cbe4185 | |
| parent | spec: Specify kernel input/output support (diff) | |
| download | rtems-central-353a102466453147dee9078ef7438316e1849267.tar.bz2 | |
spec: Specify some cache manager directives
54 files changed, 1120 insertions, 0 deletions
diff --git a/spec/rtems/cache/if/aligned-malloc.yml b/spec/rtems/cache/if/aligned-malloc.yml index be0b0a9a..0f9b373b 100644 --- a/spec/rtems/cache/if/aligned-malloc.yml +++ b/spec/rtems/cache/if/aligned-malloc.yml @@ -20,6 +20,12 @@ links: uid: header - role: interface-ingroup uid: group +- role: constraint + uid: /constraint/directive-ctx-devinit +- role: constraint + uid: /constraint/directive-ctx-task +- role: constraint + uid: /constraint/object-allocator name: rtems_cache_aligned_malloc notes: null params: diff --git a/spec/rtems/cache/if/coherent-add-area.yml b/spec/rtems/cache/if/coherent-add-area.yml index 614f1a88..e5b9cbcb 100644 --- a/spec/rtems/cache/if/coherent-add-area.yml +++ b/spec/rtems/cache/if/coherent-add-area.yml @@ -21,6 +21,12 @@ links: uid: header - role: interface-ingroup uid: group +- role: constraint + uid: /constraint/directive-ctx-devinit +- role: constraint + uid: /constraint/directive-ctx-task +- role: constraint + uid: /constraint/object-allocator name: rtems_cache_coherent_add_area notes: null params: diff --git a/spec/rtems/cache/if/coherent-allocate.yml b/spec/rtems/cache/if/coherent-allocate.yml index 303738a5..4da8f4b2 100644 --- a/spec/rtems/cache/if/coherent-allocate.yml +++ b/spec/rtems/cache/if/coherent-allocate.yml @@ -22,6 +22,12 @@ links: uid: header - role: interface-ingroup uid: group +- role: constraint + uid: /constraint/directive-ctx-devinit +- role: constraint + uid: /constraint/directive-ctx-task +- role: constraint + uid: /constraint/object-allocator name: rtems_cache_coherent_allocate notes: null params: diff --git a/spec/rtems/cache/if/coherent-free.yml b/spec/rtems/cache/if/coherent-free.yml index dbc01469..c337990e 100644 --- a/spec/rtems/cache/if/coherent-free.yml +++ b/spec/rtems/cache/if/coherent-free.yml @@ -20,6 +20,12 @@ links: uid: header - role: interface-ingroup uid: group +- role: constraint + uid: /constraint/directive-ctx-devinit +- role: constraint + uid: /constraint/directive-ctx-task +- role: constraint + uid: /constraint/object-allocator name: rtems_cache_coherent_free notes: null params: diff --git a/spec/rtems/cache/if/disable-data.yml b/spec/rtems/cache/if/disable-data.yml index 6fb44cfb..2d4a3d5c 100644 --- a/spec/rtems/cache/if/disable-data.yml +++ b/spec/rtems/cache/if/disable-data.yml @@ -19,6 +19,10 @@ links: uid: header - role: interface-ingroup uid: group +- role: constraint + uid: /constraint/directive-ctx-any +- role: constraint + uid: /constraint/directive-no-preempt name: rtems_cache_disable_data notes: null params: [] diff --git a/spec/rtems/cache/if/disable-instruction.yml b/spec/rtems/cache/if/disable-instruction.yml index 4ef329de..654fdf32 100644 --- a/spec/rtems/cache/if/disable-instruction.yml +++ b/spec/rtems/cache/if/disable-instruction.yml @@ -19,6 +19,10 @@ links: uid: header - role: interface-ingroup uid: group +- role: constraint + uid: /constraint/directive-ctx-any +- role: constraint + uid: /constraint/directive-no-preempt name: rtems_cache_disable_instruction notes: null params: [] diff --git a/spec/rtems/cache/if/enable-data.yml b/spec/rtems/cache/if/enable-data.yml index 3f50f7a5..42fd9539 100644 --- a/spec/rtems/cache/if/enable-data.yml +++ b/spec/rtems/cache/if/enable-data.yml @@ -19,6 +19,10 @@ links: uid: header - role: interface-ingroup uid: group +- role: constraint + uid: /constraint/directive-ctx-any +- role: constraint + uid: /constraint/directive-no-preempt name: rtems_cache_enable_data notes: null params: [] diff --git a/spec/rtems/cache/if/enable-instruction.yml b/spec/rtems/cache/if/enable-instruction.yml index 31b5e297..d5ed2487 100644 --- a/spec/rtems/cache/if/enable-instruction.yml +++ b/spec/rtems/cache/if/enable-instruction.yml @@ -19,6 +19,10 @@ links: uid: header - role: interface-ingroup uid: group +- role: constraint + uid: /constraint/directive-ctx-any +- role: constraint + uid: /constraint/directive-no-preempt name: rtems_cache_enable_instruction notes: null params: [] diff --git a/spec/rtems/cache/if/flush-entire-data.yml b/spec/rtems/cache/if/flush-entire-data.yml index 659fa947..707af381 100644 --- a/spec/rtems/cache/if/flush-entire-data.yml +++ b/spec/rtems/cache/if/flush-entire-data.yml @@ -19,6 +19,10 @@ links: uid: header - role: interface-ingroup uid: group +- role: constraint + uid: /constraint/directive-ctx-any +- role: constraint + uid: /constraint/directive-no-preempt name: rtems_cache_flush_entire_data notes: null params: [] diff --git a/spec/rtems/cache/if/flush-multiple-data-lines.yml b/spec/rtems/cache/if/flush-multiple-data-lines.yml index fc153fc8..a110924c 100644 --- a/spec/rtems/cache/if/flush-multiple-data-lines.yml +++ b/spec/rtems/cache/if/flush-multiple-data-lines.yml @@ -21,6 +21,10 @@ links: uid: header - role: interface-ingroup uid: group +- role: constraint + uid: /constraint/directive-ctx-any +- role: constraint + uid: /constraint/directive-no-preempt name: rtems_cache_flush_multiple_data_lines notes: null params: diff --git a/spec/rtems/cache/if/freeze-data.yml b/spec/rtems/cache/if/freeze-data.yml index 9cec123d..99d8e7f7 100644 --- a/spec/rtems/cache/if/freeze-data.yml +++ b/spec/rtems/cache/if/freeze-data.yml @@ -19,6 +19,10 @@ links: uid: header - role: interface-ingroup uid: group +- role: constraint + uid: /constraint/directive-ctx-any +- role: constraint + uid: /constraint/directive-no-preempt name: rtems_cache_freeze_data notes: null params: [] diff --git a/spec/rtems/cache/if/freeze-instruction.yml b/spec/rtems/cache/if/freeze-instruction.yml index a3e494b4..f2d578de 100644 --- a/spec/rtems/cache/if/freeze-instruction.yml +++ b/spec/rtems/cache/if/freeze-instruction.yml @@ -19,6 +19,10 @@ links: uid: header - role: interface-ingroup uid: group +- role: constraint + uid: /constraint/directive-ctx-any +- role: constraint + uid: /constraint/directive-no-preempt name: rtems_cache_freeze_instruction notes: null params: [] diff --git a/spec/rtems/cache/if/get-data-line-size.yml b/spec/rtems/cache/if/get-data-line-size.yml index b0d2b1c2..0fda20d3 100644 --- a/spec/rtems/cache/if/get-data-line-size.yml +++ b/spec/rtems/cache/if/get-data-line-size.yml @@ -19,6 +19,10 @@ links: uid: header - role: interface-ingroup uid: group +- role: constraint + uid: /constraint/directive-ctx-any +- role: constraint + uid: /constraint/directive-no-preempt name: rtems_cache_get_data_line_size notes: null params: [] diff --git a/spec/rtems/cache/if/get-data-size.yml b/spec/rtems/cache/if/get-data-size.yml index f64b1318..1a430292 100644 --- a/spec/rtems/cache/if/get-data-size.yml +++ b/spec/rtems/cache/if/get-data-size.yml @@ -20,6 +20,10 @@ links: uid: header - role: interface-ingroup uid: group +- role: constraint + uid: /constraint/directive-ctx-any +- role: constraint + uid: /constraint/directive-no-preempt name: rtems_cache_get_data_cache_size notes: null params: diff --git a/spec/rtems/cache/if/get-instruction-line-size.yml b/spec/rtems/cache/if/get-instruction-line-size.yml index 0d0d28b9..ee883e04 100644 --- a/spec/rtems/cache/if/get-instruction-line-size.yml +++ b/spec/rtems/cache/if/get-instruction-line-size.yml @@ -19,6 +19,10 @@ links: uid: header - role: interface-ingroup uid: group +- role: constraint + uid: /constraint/directive-ctx-any +- role: constraint + uid: /constraint/directive-no-preempt name: rtems_cache_get_instruction_line_size notes: null params: [] diff --git a/spec/rtems/cache/if/get-instruction-size.yml b/spec/rtems/cache/if/get-instruction-size.yml index cc4620f2..3a317833 100644 --- a/spec/rtems/cache/if/get-instruction-size.yml +++ b/spec/rtems/cache/if/get-instruction-size.yml @@ -20,6 +20,10 @@ links: uid: header - role: interface-ingroup uid: group +- role: constraint + uid: /constraint/directive-ctx-any +- role: constraint + uid: /constraint/directive-no-preempt name: rtems_cache_get_instruction_cache_size notes: null params: diff --git a/spec/rtems/cache/if/get-maximal-line-size.yml b/spec/rtems/cache/if/get-maximal-line-size.yml index f164dbe0..e231695c 100644 --- a/spec/rtems/cache/if/get-maximal-line-size.yml +++ b/spec/rtems/cache/if/get-maximal-line-size.yml @@ -19,6 +19,10 @@ links: uid: header - role: interface-ingroup uid: group +- role: constraint + uid: /constraint/directive-ctx-any +- role: constraint + uid: /constraint/directive-no-preempt name: rtems_cache_get_maximal_line_size notes: null params: [] diff --git a/spec/rtems/cache/if/instruction-sync-after-code-change.yml b/spec/rtems/cache/if/instruction-sync-after-code-change.yml index 1a2c0953..a209173d 100644 --- a/spec/rtems/cache/if/instruction-sync-after-code-change.yml +++ b/spec/rtems/cache/if/instruction-sync-after-code-change.yml @@ -21,6 +21,10 @@ links: uid: header - role: interface-ingroup uid: group +- role: constraint + uid: /constraint/directive-ctx-any +- role: constraint + uid: /constraint/directive-no-preempt name: rtems_cache_instruction_sync_after_code_change notes: null params: diff --git a/spec/rtems/cache/if/invalidate-entire-data.yml b/spec/rtems/cache/if/invalidate-entire-data.yml index ac71cf38..770ca394 100644 --- a/spec/rtems/cache/if/invalidate-entire-data.yml +++ b/spec/rtems/cache/if/invalidate-entire-data.yml @@ -19,6 +19,10 @@ links: uid: header - role: interface-ingroup uid: group +- role: constraint + uid: /constraint/directive-ctx-any +- role: constraint + uid: /constraint/directive-no-preempt name: rtems_cache_invalidate_entire_data notes: null params: [] diff --git a/spec/rtems/cache/if/invalidate-entire-instruction.yml b/spec/rtems/cache/if/invalidate-entire-instruction.yml index 3f33495d..8dedbb0e 100644 --- a/spec/rtems/cache/if/invalidate-entire-instruction.yml +++ b/spec/rtems/cache/if/invalidate-entire-instruction.yml @@ -19,6 +19,10 @@ links: uid: header - role: interface-ingroup uid: group +- role: constraint + uid: /constraint/directive-ctx-any +- role: constraint + uid: /constraint/directive-no-preempt name: rtems_cache_invalidate_entire_instruction notes: null params: [] diff --git a/spec/rtems/cache/if/invalidate-multiple-data-lines.yml b/spec/rtems/cache/if/invalidate-multiple-data-lines.yml index 18877f27..b69336ee 100644 --- a/spec/rtems/cache/if/invalidate-multiple-data-lines.yml +++ b/spec/rtems/cache/if/invalidate-multiple-data-lines.yml @@ -21,6 +21,10 @@ links: uid: header - role: interface-ingroup uid: group +- role: constraint + uid: /constraint/directive-ctx-any +- role: constraint + uid: /constraint/directive-no-preempt name: rtems_cache_invalidate_multiple_data_lines notes: null params: diff --git a/spec/rtems/cache/if/invalidate-multiple-instruction-lines.yml b/spec/rtems/cache/if/invalidate-multiple-instruction-lines.yml index 499c2d53..6f95de28 100644 --- a/spec/rtems/cache/if/invalidate-multiple-instruction-lines.yml +++ b/spec/rtems/cache/if/invalidate-multiple-instruction-lines.yml @@ -21,6 +21,10 @@ links: uid: header - role: interface-ingroup uid: group +- role: constraint + uid: /constraint/directive-ctx-any +- role: constraint + uid: /constraint/directive-no-preempt name: rtems_cache_invalidate_multiple_instruction_lines notes: null params: diff --git a/spec/rtems/cache/if/unfreeze-data.yml b/spec/rtems/cache/if/unfreeze-data.yml index 2949a8f5..461993cd 100644 --- a/spec/rtems/cache/if/unfreeze-data.yml +++ b/spec/rtems/cache/if/unfreeze-data.yml @@ -19,6 +19,10 @@ links: uid: header - role: interface-ingroup uid: group +- role: constraint + uid: /constraint/directive-ctx-any +- role: constraint + uid: /constraint/directive-no-preempt name: rtems_cache_unfreeze_data notes: null params: [] diff --git a/spec/rtems/cache/if/unfreeze-instruction.yml b/spec/rtems/cache/if/unfreeze-instruction.yml index 99d97057..b49586ba 100644 --- a/spec/rtems/cache/if/unfreeze-instruction.yml +++ b/spec/rtems/cache/if/unfreeze-instruction.yml @@ -19,6 +19,10 @@ links: uid: header - role: interface-ingroup uid: group +- role: constraint + uid: /constraint/directive-ctx-any +- role: constraint + uid: /constraint/directive-no-preempt name: rtems_cache_unfreeze_instruction notes: null params: [] diff --git a/spec/rtems/cache/req/disable-data.yml b/spec/rtems/cache/req/disable-data.yml new file mode 100644 index 00000000..0998e621 --- /dev/null +++ b/spec/rtems/cache/req/disable-data.yml @@ -0,0 +1,16 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 +copyrights: +- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de) +enabled-by: true +links: +- role: interface-function + uid: ../if/disable-data +functional-type: function +rationale: null +references: [] +requirement-type: functional +text: | + Where the ${/glossary/target:/term} has a data cache, where the data cache + can be disabled, when the ${../if/disable-data:/name} directive is called, + the data cache shall be disabled. +type: requirement diff --git a/spec/rtems/cache/req/disable-instruction.yml b/spec/rtems/cache/req/disable-instruction.yml new file mode 100644 index 00000000..a03bfe04 --- /dev/null +++ b/spec/rtems/cache/req/disable-instruction.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 +copyrights: +- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de) +enabled-by: true +links: +- role: interface-function + uid: ../if/disable-instruction +functional-type: function +rationale: null +references: [] +requirement-type: functional +text: | + Where the ${/glossary/target:/term} has an instruction cache, where the + instruction cache can be disabled, when the + ${../if/disable-instruction:/name} directive is called, the instruction cache + shall be disabled. +type: requirement diff --git a/spec/rtems/cache/req/enable-data.yml b/spec/rtems/cache/req/enable-data.yml new file mode 100644 index 00000000..3eb37775 --- /dev/null +++ b/spec/rtems/cache/req/enable-data.yml @@ -0,0 +1,16 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 +copyrights: +- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de) +enabled-by: true +links: +- role: interface-function + uid: ../if/enable-data +functional-type: function +rationale: null +references: [] +requirement-type: functional +text: | + Where the ${/glossary/target:/term} has a data cache, where the data cache + can be enabled, when the ${../if/enable-data:/name} directive is called, + the data cache shall be enabled. +type: requirement diff --git a/spec/rtems/cache/req/enable-instruction.yml b/spec/rtems/cache/req/enable-instruction.yml new file mode 100644 index 00000000..ef2df530 --- /dev/null +++ b/spec/rtems/cache/req/enable-instruction.yml @@ -0,0 +1,16 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 +copyrights: +- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de) +enabled-by: true +links: +- role: interface-function + uid: ../if/enable-instruction +functional-type: function +rationale: null +references: [] +requirement-type: functional +text: | + Where the ${/glossary/target:/term} has an instruction cache, where the + instruction cache can be enabled, when the ${../if/enable-instruction:/name} + directive is called, the instruction cache shall be enabled. +type: requirement diff --git a/spec/rtems/cache/req/flush-entire-data.yml b/spec/rtems/cache/req/flush-entire-data.yml new file mode 100644 index 00000000..1889dfad --- /dev/null +++ b/spec/rtems/cache/req/flush-entire-data.yml @@ -0,0 +1,16 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 +copyrights: +- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de) +enabled-by: true +links: +- role: interface-function + uid: ../if/flush-entire-data +functional-type: function +rationale: null +references: [] +requirement-type: functional +text: | + Where the ${/glossary/target:/term} has a data cache, where the data cache + can be flushed, when the ${../if/flush-entire-data:/name} directive is + called, the data cache shall be flushed. +type: requirement diff --git a/spec/rtems/cache/req/flush-multiple-data-lines.yml b/spec/rtems/cache/req/flush-multiple-data-lines.yml new file mode 100644 index 00000000..af900638 --- /dev/null +++ b/spec/rtems/cache/req/flush-multiple-data-lines.yml @@ -0,0 +1,19 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 +copyrights: +- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de) +enabled-by: true +links: +- role: interface-function + uid: ../if/flush-multiple-data-lines +functional-type: function +rationale: null +references: [] +requirement-type: functional +text: | + Where the ${/glossary/target:/term} has a data cache, where data cache lines + can be flushed, where the data cache is not coherent with all bus masters, + when the ${../if/flush-multiple-data-lines:/name} directive is called, the + data cache lines covering the memory area specified by + ${../if/flush-multiple-data-lines:/params[0]/name} and + ${../if/flush-multiple-data-lines:/params[1]/name} shall be flushed. +type: requirement diff --git a/spec/rtems/cache/req/freeze-data.yml b/spec/rtems/cache/req/freeze-data.yml new file mode 100644 index 00000000..daf04780 --- /dev/null +++ b/spec/rtems/cache/req/freeze-data.yml @@ -0,0 +1,16 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 +copyrights: +- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de) +enabled-by: true +links: +- role: interface-function + uid: ../if/freeze-data +functional-type: function +rationale: null +references: [] +requirement-type: functional +text: | + Where the ${/glossary/target:/term} has a data cache, where the data cache + can be frozen, when the ${../if/freeze-data:/name} directive is called, the + data cache shall be frozen. +type: requirement diff --git a/spec/rtems/cache/req/freeze-instruction.yml b/spec/rtems/cache/req/freeze-instruction.yml new file mode 100644 index 00000000..2aa7d214 --- /dev/null +++ b/spec/rtems/cache/req/freeze-instruction.yml @@ -0,0 +1,16 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 +copyrights: +- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de) +enabled-by: true +links: +- role: interface-function + uid: ../if/freeze-instruction +functional-type: function +rationale: null +references: [] +requirement-type: functional +text: | + Where the ${/glossary/target:/term} has an instruction cache, where the + instruction cache can be frozen, when the ${../if/freeze-instruction:/name} + directive is called, the instruction cache shall be frozen. +type: requirement diff --git a/spec/rtems/cache/req/get-data-line-size-no-cache.yml b/spec/rtems/cache/req/get-data-line-size-no-cache.yml new file mode 100644 index 00000000..7b0a4ab9 --- /dev/null +++ b/spec/rtems/cache/req/get-data-line-size-no-cache.yml @@ -0,0 +1,15 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 +copyrights: +- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de) +enabled-by: true +links: +- role: interface-function + uid: ../if/get-data-line-size +functional-type: function +rationale: null +references: [] +requirement-type: functional +text: | + Where the ${/glossary/target:/term} has no data cache, the + ${../if/get-data-line-size:/name} directive shall return zero. +type: requirement diff --git a/spec/rtems/cache/req/get-data-line-size.yml b/spec/rtems/cache/req/get-data-line-size.yml new file mode 100644 index 00000000..b701a7da --- /dev/null +++ b/spec/rtems/cache/req/get-data-line-size.yml @@ -0,0 +1,16 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 +copyrights: +- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de) +enabled-by: true +links: +- role: interface-function + uid: ../if/get-data-line-size +functional-type: function +rationale: null +references: [] +requirement-type: functional +text: | + Where the ${/glossary/target:/term} has a data cache, the + ${../if/get-data-line-size:/name} directive shall return the size of the data + cache line. +type: requirement diff --git a/spec/rtems/cache/req/get-data-size-level-zero.yml b/spec/rtems/cache/req/get-data-size-level-zero.yml new file mode 100644 index 00000000..18bfbe7a --- /dev/null +++ b/spec/rtems/cache/req/get-data-size-level-zero.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 +copyrights: +- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de) +enabled-by: true +links: +- role: interface-function + uid: ../if/get-data-size +functional-type: function +rationale: null +references: [] +requirement-type: functional +text: | + Where the ${/glossary/target:/term} has a data cache, while the + ${../if/get-data-size:/params[0]/name} parameter is equal to zero, the + ${../if/get-data-size:/name} directive shall return the size of the entire + data cache. +type: requirement diff --git a/spec/rtems/cache/req/get-data-size-no-cache.yml b/spec/rtems/cache/req/get-data-size-no-cache.yml new file mode 100644 index 00000000..29faf959 --- /dev/null +++ b/spec/rtems/cache/req/get-data-size-no-cache.yml @@ -0,0 +1,15 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 +copyrights: +- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de) +enabled-by: true +links: +- role: interface-function + uid: ../if/get-data-size +functional-type: function +rationale: null +references: [] +requirement-type: functional +text: | + Where the ${/glossary/target:/term} has no data cache, the + ${../if/get-data-size:/name} directive shall return zero. +type: requirement diff --git a/spec/rtems/cache/req/get-data-size-no-level.yml b/spec/rtems/cache/req/get-data-size-no-level.yml new file mode 100644 index 00000000..e8c9cc14 --- /dev/null +++ b/spec/rtems/cache/req/get-data-size-no-level.yml @@ -0,0 +1,18 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 +copyrights: +- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de) +enabled-by: true +links: +- role: interface-function + uid: ../if/get-data-size +functional-type: function +rationale: null +references: [] +requirement-type: functional +text: | + Where the ${/glossary/target:/term} has a data cache, while the + ${../if/get-data-size:/params[0]/name} parameter is greater than zero, while + the ${../if/get-data-size:/params[0]/name} parameter is not associated with a + data cache level, the ${../if/get-data-size:/name} directive shall return + zero. +type: requirement diff --git a/spec/rtems/cache/req/get-data-size.yml b/spec/rtems/cache/req/get-data-size.yml new file mode 100644 index 00000000..0a3f8f8d --- /dev/null +++ b/spec/rtems/cache/req/get-data-size.yml @@ -0,0 +1,19 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 +copyrights: +- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de) +enabled-by: true +links: +- role: interface-function + uid: ../if/get-data-size +functional-type: function +rationale: null +references: [] +requirement-type: functional +text: | + Where the ${/glossary/target:/term} has a data cache, while the + ${../if/get-data-size:/params[0]/name} parameter is greater than zero, while + the ${../if/get-data-size:/params[0]/name} parameter is associated with a + data cache level, the ${../if/get-data-size:/name} directive shall return the + size of the data cache of the level specified by + ${../if/get-data-size:/params[0]/name}. +type: requirement diff --git a/spec/rtems/cache/req/get-instruction-line-size-no-cache.yml b/spec/rtems/cache/req/get-instruction-line-size-no-cache.yml new file mode 100644 index 00000000..85fbd3ae --- /dev/null +++ b/spec/rtems/cache/req/get-instruction-line-size-no-cache.yml @@ -0,0 +1,15 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 +copyrights: +- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de) +enabled-by: true +links: +- role: interface-function + uid: ../if/get-instruction-line-size +functional-type: function +rationale: null +references: [] +requirement-type: functional +text: | + Where the ${/glossary/target:/term} has no instruction cache, the + ${../if/get-instruction-line-size:/name} directive shall return zero. +type: requirement diff --git a/spec/rtems/cache/req/get-instruction-line-size.yml b/spec/rtems/cache/req/get-instruction-line-size.yml new file mode 100644 index 00000000..efb7b876 --- /dev/null +++ b/spec/rtems/cache/req/get-instruction-line-size.yml @@ -0,0 +1,16 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 +copyrights: +- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de) +enabled-by: true +links: +- role: interface-function + uid: ../if/get-instruction-line-size +functional-type: function +rationale: null +references: [] +requirement-type: functional +text: | + Where the ${/glossary/target:/term} has an instruction cache, the + ${../if/get-instruction-line-size:/name} directive shall return the size of + the instruction cache line. +type: requirement diff --git a/spec/rtems/cache/req/get-instruction-size-level-zero.yml b/spec/rtems/cache/req/get-instruction-size-level-zero.yml new file mode 100644 index 00000000..99c4bea9 --- /dev/null +++ b/spec/rtems/cache/req/get-instruction-size-level-zero.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 +copyrights: +- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de) +enabled-by: true +links: +- role: interface-function + uid: ../if/get-instruction-size +functional-type: function +rationale: null +references: [] +requirement-type: functional +text: | + Where the ${/glossary/target:/term} has an instruction cache, while the + ${../if/get-instruction-size:/params[0]/name} parameter is equal to zero, the + ${../if/get-instruction-size:/name} directive shall return the size of the + entire instruction cache. +type: requirement diff --git a/spec/rtems/cache/req/get-instruction-size-no-cache.yml b/spec/rtems/cache/req/get-instruction-size-no-cache.yml new file mode 100644 index 00000000..490fa169 --- /dev/null +++ b/spec/rtems/cache/req/get-instruction-size-no-cache.yml @@ -0,0 +1,15 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 +copyrights: +- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de) +enabled-by: true +links: +- role: interface-function + uid: ../if/get-instruction-size +functional-type: function +rationale: null +references: [] +requirement-type: functional +text: | + Where the ${/glossary/target:/term} has no instruction cache, the + ${../if/get-instruction-size:/name} directive shall return zero. +type: requirement diff --git a/spec/rtems/cache/req/get-instruction-size-no-level.yml b/spec/rtems/cache/req/get-instruction-size-no-level.yml new file mode 100644 index 00000000..8daa7a5e --- /dev/null +++ b/spec/rtems/cache/req/get-instruction-size-no-level.yml @@ -0,0 +1,18 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 +copyrights: +- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de) +enabled-by: true +links: +- role: interface-function + uid: ../if/get-instruction-size +functional-type: function +rationale: null +references: [] +requirement-type: functional +text: | + Where the ${/glossary/target:/term} has an instruction cache, while the + ${../if/get-instruction-size:/params[0]/name} parameter is greater than zero, + while the ${../if/get-instruction-size:/params[0]/name} parameter is not + associated with an instruction cache level, the + ${../if/get-instruction-size:/name} directive shall return zero. +type: requirement diff --git a/spec/rtems/cache/req/get-instruction-size.yml b/spec/rtems/cache/req/get-instruction-size.yml new file mode 100644 index 00000000..940d736d --- /dev/null +++ b/spec/rtems/cache/req/get-instruction-size.yml @@ -0,0 +1,20 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 +copyrights: +- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de) +enabled-by: true +links: +- role: interface-function + uid: ../if/get-instruction-size +functional-type: function +rationale: null +references: [] +requirement-type: functional +text: | + Where the ${/glossary/target:/term} has an instruction cache, while the + ${../if/get-instruction-size:/params[0]/name} parameter is greater than zero, + while the ${../if/get-instruction-size:/params[0]/name} parameter is + associated with an instruction cache level, the + ${../if/get-instruction-size:/name} directive shall return the size of the + instruction cache of the level specified by + ${../if/get-instruction-size:/params[0]/name}. +type: requirement diff --git a/spec/rtems/cache/req/get-maximal-line-size-no-cache.yml b/spec/rtems/cache/req/get-maximal-line-size-no-cache.yml new file mode 100644 index 00000000..615572c9 --- /dev/null +++ b/spec/rtems/cache/req/get-maximal-line-size-no-cache.yml @@ -0,0 +1,15 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 +copyrights: +- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de) +enabled-by: true +links: +- role: interface-function + uid: ../if/get-maximal-line-size +functional-type: function +rationale: null +references: [] +requirement-type: functional +text: | + Where the ${/glossary/target:/term} has no data cache and no instruction + cache, the ${../if/get-maximal-line-size:/name} directive shall return zero. +type: requirement diff --git a/spec/rtems/cache/req/get-maximal-line-size.yml b/spec/rtems/cache/req/get-maximal-line-size.yml new file mode 100644 index 00000000..ef70cf07 --- /dev/null +++ b/spec/rtems/cache/req/get-maximal-line-size.yml @@ -0,0 +1,16 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 +copyrights: +- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de) +enabled-by: true +links: +- role: interface-function + uid: ../if/get-maximal-line-size +functional-type: function +rationale: null +references: [] +requirement-type: functional +text: | + Where the ${/glossary/target:/term} has a data cache or an instruction cache, + the ${../if/get-maximal-line-size:/name} directive shall return the maximal + cache line size of all caches. +type: requirement diff --git a/spec/rtems/cache/req/instruction-sync-after-code-change.yml b/spec/rtems/cache/req/instruction-sync-after-code-change.yml new file mode 100644 index 00000000..01db7562 --- /dev/null +++ b/spec/rtems/cache/req/instruction-sync-after-code-change.yml @@ -0,0 +1,20 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 +copyrights: +- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de) +enabled-by: true +links: +- role: interface-function + uid: ../if/instruction-sync-after-code-change +functional-type: function +rationale: null +references: [] +requirement-type: functional +text: | + Where the ${/glossary/target:/term} has an instruction cache, where the + instruction cache needs to be synchronized after code changes, when the + ${../if/instruction-sync-after-code-change:/name} directive is called, the + instruction cache shall be synchronized so that the code in the memory area + specified by ${../if/instruction-sync-after-code-change:/params[0]/name} and + ${../if/instruction-sync-after-code-change:/params[1]/name} will be fetched + when it needs to be executed. +type: requirement diff --git a/spec/rtems/cache/req/invalidate-entire-data.yml b/spec/rtems/cache/req/invalidate-entire-data.yml new file mode 100644 index 00000000..7820b537 --- /dev/null +++ b/spec/rtems/cache/req/invalidate-entire-data.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 +copyrights: +- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de) +enabled-by: true +links: +- role: interface-function + uid: ../if/invalidate-entire-data +functional-type: function +rationale: null +references: [] +requirement-type: functional +text: | + Where the ${/glossary/target:/term} has a data cache, where the data cache + can be flushed and invalidated, when the + ${../if/invalidate-entire-data:/name} directive is called, the data cache + shall be flushed and invalidated. +type: requirement diff --git a/spec/rtems/cache/req/invalidate-entire-instruction.yml b/spec/rtems/cache/req/invalidate-entire-instruction.yml new file mode 100644 index 00000000..341a43f4 --- /dev/null +++ b/spec/rtems/cache/req/invalidate-entire-instruction.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 +copyrights: +- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de) +enabled-by: true +links: +- role: interface-function + uid: ../if/invalidate-entire-instruction +functional-type: function +rationale: null +references: [] +requirement-type: functional +text: | + Where the ${/glossary/target:/term} has an instruction cache, where the + instruction cache can be invalidated, when the + ${../if/invalidate-entire-instruction:/name} directive is called, the + instruction cache shall be invalidated. +type: requirement diff --git a/spec/rtems/cache/req/invalidate-multiple-data-lines.yml b/spec/rtems/cache/req/invalidate-multiple-data-lines.yml new file mode 100644 index 00000000..e9140b27 --- /dev/null +++ b/spec/rtems/cache/req/invalidate-multiple-data-lines.yml @@ -0,0 +1,19 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 +copyrights: +- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de) +enabled-by: true +links: +- role: interface-function + uid: ../if/invalidate-multiple-data-lines +functional-type: function +rationale: null +references: [] +requirement-type: functional +text: | + Where the ${/glossary/target:/term} has a data cache, where data cache lines + can be invalidated, where the data cache is not coherent with all bus + masters, when the ${../if/invalidate-multiple-data-lines:/name} directive is + called, the data cache lines covering the memory area specified by + ${../if/invalidate-multiple-data-lines:/params[0]/name} and + ${../if/invalidate-multiple-data-lines:/params[1]/name} shall be invalidated. +type: requirement diff --git a/spec/rtems/cache/req/invalidate-multiple-instruction-lines.yml b/spec/rtems/cache/req/invalidate-multiple-instruction-lines.yml new file mode 100644 index 00000000..3cb5af2a --- /dev/null +++ b/spec/rtems/cache/req/invalidate-multiple-instruction-lines.yml @@ -0,0 +1,21 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 +copyrights: +- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de) +enabled-by: true +links: +- role: interface-function + uid: ../if/invalidate-multiple-instruction-lines +functional-type: function +rationale: null +references: [] +requirement-type: functional +text: | + Where the ${/glossary/target:/term} has an instruction cache, where + instruction cache lines can be invalidated, where the instruction cache is + not coherent with all bus masters, when the + ${../if/invalidate-multiple-instruction-lines:/name} directive is called, the + instruction cache lines covering the memory area specified by + ${../if/invalidate-multiple-instruction-lines:/params[0]/name} and + ${../if/invalidate-multiple-instruction-lines:/params[1]/name} shall be + invalidated. +type: requirement diff --git a/spec/rtems/cache/req/unfreeze-data.yml b/spec/rtems/cache/req/unfreeze-data.yml new file mode 100644 index 00000000..6d41df0e --- /dev/null +++ b/spec/rtems/cache/req/unfreeze-data.yml @@ -0,0 +1,16 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 +copyrights: +- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de) +enabled-by: true +links: +- role: interface-function + uid: ../if/unfreeze-data +functional-type: function +rationale: null +references: [] +requirement-type: functional +text: | + Where the ${/glossary/target:/term} has a data cache, where the data cache + can be frozen, when the ${../if/unfreeze-data:/name} directive is called, the + data cache shall be not frozen. +type: requirement diff --git a/spec/rtems/cache/req/unfreeze-instruction.yml b/spec/rtems/cache/req/unfreeze-instruction.yml new file mode 100644 index 00000000..38f03fe9 --- /dev/null +++ b/spec/rtems/cache/req/unfreeze-instruction.yml @@ -0,0 +1,16 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 +copyrights: +- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de) +enabled-by: true +links: +- role: interface-function + uid: ../if/unfreeze-instruction +functional-type: function +rationale: null +references: [] +requirement-type: functional +text: | + Where the ${/glossary/target:/term} has an instruction cache, where the + instruction cache can be frozen, when the ${../if/unfreeze-instruction:/name} + directive is called, the instruction cache shall be not frozen. +type: requirement diff --git a/spec/rtems/cache/val/cache.yml b/spec/rtems/cache/val/cache.yml new file mode 100644 index 00000000..dc499a58 --- /dev/null +++ b/spec/rtems/cache/val/cache.yml @@ -0,0 +1,526 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +copyrights: +- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de) +enabled-by: true +links: [] +test-actions: +- action-brief: | + Call the ${../if/disable-data:/name} and ${../if/enable-data:/name} + directives. + action-code: | + rtems_cache_disable_data(); + rtems_cache_enable_data(); + checks: [] + links: + - role: validation + uid: ../req/disable-data + - role: validation + uid: ../req/enable-data +- action-brief: | + Call the ${../if/disable-data:/name} and ${../if/enable-data:/name} + directives with maskable interrupts disabled. + action-code: | + rtems_interrupt_level level; + + rtems_interrupt_local_disable(level); + rtems_cache_disable_data(); + rtems_cache_enable_data(); + rtems_interrupt_local_enable(level); + checks: [] + links: + - role: validation + uid: ../req/disable-data + - role: validation + uid: ../req/enable-data +- action-brief: | + Call the ${../if/disable-instruction:/name} and + ${../if/enable-instruction:/name} directives. + action-code: | + rtems_cache_disable_instruction(); + rtems_cache_enable_instruction(); + checks: [] + links: + - role: validation + uid: ../req/disable-instruction + - role: validation + uid: ../req/enable-instruction +- action-brief: | + Call the ${../if/disable-instruction:/name} and + ${../if/enable-instruction:/name} directives with maskable interrupts + disabled. + action-code: | + rtems_interrupt_level level; + + rtems_interrupt_local_disable(level); + rtems_cache_disable_instruction(); + rtems_cache_enable_instruction(); + rtems_interrupt_local_enable(level); + checks: [] + links: + - role: validation + uid: ../req/disable-instruction + - role: validation + uid: ../req/enable-instruction +- action-brief: | + Call the ${../if/freeze-data:/name} and ${../if/unfreeze-data:/name} + directives. + action-code: | + rtems_cache_freeze_data(); + rtems_cache_unfreeze_data(); + checks: [] + links: + - role: validation + uid: ../req/freeze-data + - role: validation + uid: ../req/unfreeze-data +- action-brief: | + Call the ${../if/freeze-data:/name} and ${../if/unfreeze-data:/name} + directives with maskable interrupts disabled. + action-code: | + rtems_interrupt_level level; + + rtems_interrupt_local_disable(level); + rtems_cache_freeze_data(); + rtems_cache_unfreeze_data(); + rtems_interrupt_local_enable(level); + checks: [] + links: + - role: validation + uid: ../req/freeze-data + - role: validation + uid: ../req/unfreeze-data +- action-brief: | + Call the ${../if/freeze-instruction:/name} and + ${../if/unfreeze-instruction:/name} directives. + action-code: | + rtems_cache_freeze_instruction(); + rtems_cache_unfreeze_instruction(); + checks: [] + links: + - role: validation + uid: ../req/freeze-instruction + - role: validation + uid: ../req/unfreeze-instruction +- action-brief: | + Call the ${../if/freeze-instruction:/name} and + ${../if/unfreeze-instruction:/name} directives with maskable interrupts + disabled. + action-code: | + rtems_interrupt_level level; + + rtems_interrupt_local_disable(level); + rtems_cache_freeze_instruction(); + rtems_cache_unfreeze_instruction(); + rtems_interrupt_local_enable(level); + checks: [] + links: + - role: validation + uid: ../req/freeze-instruction + - role: validation + uid: ../req/unfreeze-instruction +- action-brief: | + Call the ${../if/invalidate-entire-data:/name} directive with maskable + interrupts disabled. + action-code: | + rtems_interrupt_level level; + + rtems_interrupt_local_disable(level); + rtems_cache_invalidate_entire_data(); + rtems_interrupt_local_enable(level); + checks: [] + links: + - role: validation + uid: ../req/invalidate-entire-data +- action-brief: | + Call the ${../if/invalidate-entire-instruction:/name} directive. + action-code: | + rtems_cache_invalidate_entire_instruction(); + checks: [] + links: + - role: validation + uid: ../req/invalidate-entire-instruction +- action-brief: | + Call the ${../if/invalidate-entire-instruction:/name} directive with + maskable interrupts disabled. + action-code: | + rtems_interrupt_level level; + + rtems_interrupt_local_disable(level); + rtems_cache_invalidate_entire_instruction(); + rtems_interrupt_local_enable(level); + checks: [] + links: + - role: validation + uid: ../req/invalidate-entire-instruction +- action-brief: | + Call the ${../if/flush-entire-data:/name} directive. + action-code: | + rtems_cache_flush_entire_data(); + checks: [] + links: + - role: validation + uid: ../req/flush-entire-data +- action-brief: | + Call the ${../if/flush-entire-data:/name} directive with maskable + interrupts disabled. + action-code: | + rtems_interrupt_level level; + + rtems_interrupt_local_disable(level); + rtems_cache_flush_entire_data(); + rtems_interrupt_local_enable(level); + checks: [] + links: + - role: validation + uid: ../req/flush-entire-data +- action-brief: | + Call the ${../if/flush-multiple-data-lines:/name} directive with a sample + set of memory areas. + action-code: | + CallFlushMultipleDataLines(); + checks: [] + links: + - role: validation + uid: ../req/flush-multiple-data-lines +- action-brief: | + Call the ${../if/flush-multiple-data-lines:/name} directive with a sample + set of memory areas with maskable interrupts disabled. + action-code: | + rtems_interrupt_level level; + + rtems_interrupt_local_disable(level); + CallFlushMultipleDataLines(); + rtems_interrupt_local_enable(level); + checks: [] + links: + - role: validation + uid: ../req/flush-multiple-data-lines +- action-brief: | + Call the ${../if/invalidate-multiple-data-lines:/name} directive with a sample + set of memory areas. + action-code: | + CallInvalidateMultipleDataLines(); + checks: [] + links: + - role: validation + uid: ../req/invalidate-multiple-data-lines +- action-brief: | + Call the ${../if/invalidate-multiple-data-lines:/name} directive with a sample + set of memory areas with maskable interrupts disabled. + action-code: | + rtems_interrupt_level level; + + rtems_interrupt_local_disable(level); + CallInvalidateMultipleDataLines(); + rtems_interrupt_local_enable(level); + checks: [] + links: + - role: validation + uid: ../req/invalidate-multiple-data-lines +- action-brief: | + Call the ${../if/invalidate-multiple-instruction-lines:/name} directive + with a sample set of memory areas. + action-code: | + CallInvalidateMultipleInstructionLines(); + checks: [] + links: + - role: validation + uid: ../req/invalidate-multiple-instruction-lines +- action-brief: | + Call the ${../if/invalidate-multiple-instruction-lines:/name} directive + with a sample set of memory areas with maskable interrupts disabled. + action-code: | + rtems_interrupt_level level; + + rtems_interrupt_local_disable(level); + CallInvalidateMultipleInstructionLines(); + rtems_interrupt_local_enable(level); + checks: [] + links: + - role: validation + uid: ../req/invalidate-multiple-instruction-lines +- action-brief: | + Call the ${../if/instruction-sync-after-code-change:/name} directive + with a sample set of memory areas. + action-code: | + CallInstructionSyncAfterCodeChange(); + checks: [] + links: + - role: validation + uid: ../req/instruction-sync-after-code-change +- action-brief: | + Call the ${../if/instruction-sync-after-code-change:/name} directive + with a sample set of memory areas with maskable interrupts disabled. + action-code: | + rtems_interrupt_level level; + + rtems_interrupt_local_disable(level); + CallInstructionSyncAfterCodeChange(); + rtems_interrupt_local_enable(level); + checks: [] + links: + - role: validation + uid: ../req/instruction-sync-after-code-change +- action-brief: | + Call the ${../if/get-data-line-size:/name}, + ${../if/get-instruction-line-size:/name}, and the + ${../if/get-maximal-line-size:/name} directives. + action-code: | + size_t data_line_size; + size_t instruction_line_size; + size_t maximal_line_size; + + data_line_size = rtems_cache_get_data_line_size(); + instruction_line_size = rtems_cache_get_instruction_line_size(); + maximal_line_size = rtems_cache_get_maximal_line_size(); + checks: + - brief: | + Check that the maximal cache line size is greater than or equal to the + data cache line size. + code: | + T_step_ge_sz( ${step}, maximal_line_size, data_line_size ); + links: + - role: validation + uid: ../req/get-maximal-line-size + - brief: | + Check that the maximal cache line size is greater than or equal to the + instruction cache line size. + code: | + T_step_ge_sz( ${step}, maximal_line_size, instruction_line_size ); + links: + - role: validation + uid: ../req/get-maximal-line-size + links: + - role: validation + uid: ../req/get-data-line-size + - role: validation + uid: ../req/get-instruction-line-size +- action-brief: | + Call the ${../if/get-data-line-size:/name}, + ${../if/get-instruction-line-size:/name}, and the + ${../if/get-maximal-line-size:/name} directives with maskable interrupts + disabled. + action-code: | + size_t data_line_size; + size_t instruction_line_size; + size_t maximal_line_size; + rtems_interrupt_level level; + + rtems_interrupt_local_disable(level); + data_line_size = rtems_cache_get_data_line_size(); + instruction_line_size = rtems_cache_get_instruction_line_size(); + maximal_line_size = rtems_cache_get_maximal_line_size(); + rtems_interrupt_local_enable(level); + checks: + - brief: | + Check that the maximal cache line size is greater than or equal to the + data cache line size. + code: | + T_step_ge_sz( ${step}, maximal_line_size, data_line_size ); + links: + - role: validation + uid: ../req/get-maximal-line-size + - brief: | + Check that the maximal cache line size is greater than or equal to the + instruction cache line size. + code: | + T_step_ge_sz( ${step}, maximal_line_size, instruction_line_size ); + links: + - role: validation + uid: ../req/get-maximal-line-size + links: + - role: validation + uid: ../req/get-data-line-size + - role: validation + uid: ../req/get-instruction-line-size +- action-brief: | + Call the ${../if/get-data-size:/name} directive with increasing level + starting with zero until it returns zero. + action-code: | + CallGetDataSize(); + checks: [] + links: + - role: validation + uid: ../req/get-data-size + - role: validation + uid: ../req/get-data-size-level-zero + - role: validation + uid: ../req/get-data-size-no-cache + - role: validation + uid: ../req/get-data-size-no-level +- action-brief: | + Call the ${../if/get-data-size:/name} directive with increasing level + starting with zero until it returns zero with maskable interrupts disabled. + action-code: | + rtems_interrupt_level level; + + rtems_interrupt_local_disable(level); + CallGetDataSize(); + rtems_interrupt_local_enable(level); + checks: [] + links: + - role: validation + uid: ../req/get-data-size +- action-brief: | + Call the ${../if/get-instruction-size:/name} directive with increasing + level starting with zero until it returns zero. + action-code: | + CallGetInstructionSize(); + checks: [] + links: + - role: validation + uid: ../req/get-instruction-size + - role: validation + uid: ../req/get-instruction-size-level-zero + - role: validation + uid: ../req/get-instruction-size-no-cache + - role: validation + uid: ../req/get-instruction-size-no-level +- action-brief: | + Call the ${../if/get-instruction-size:/name} directive with increasing + level starting with zero until it returns zero with maskable interrupts + disabled. + action-code: | + rtems_interrupt_level level; + + rtems_interrupt_local_disable(level); + CallGetInstructionSize(); + rtems_interrupt_local_enable(level); + checks: [] + links: + - role: validation + uid: ../req/get-instruction-size +test-brief: | + Tests some ${../if/group:/name} directives. +test-context: [] +test-context-support: null +test-description: null +test-header: null +test-includes: +- rtems.h +test-local-includes: [] +test-setup: null +test-stop: null +test-support: | + static void CallFlushMultipleDataLines( void ) + { + uint8_t buf[256]; + uintptr_t data; + uintptr_t n; + uintptr_t i; + + rtems_cache_flush_multiple_data_lines( NULL, 0 ); + data = RTEMS_ALIGN_UP( (uintptr_t) &buf[ 1 ], 128 ); + + for ( n = 16; n <= 128 ; n *= 2 ) { + for ( i = 0; i < 3; ++i ) { + uintptr_t j; + + for ( j = 0; j < 3; ++j ) { + rtems_cache_flush_multiple_data_lines( + (const void *) ( data + 1 - i ), + n + 1 - j + ); + } + } + } + } + + static void CallInvalidateMultipleDataLines( void ) + { + uint8_t buf[256]; + uintptr_t data; + uintptr_t n; + uintptr_t i; + + rtems_cache_invalidate_multiple_data_lines( NULL, 0 ); + data = RTEMS_ALIGN_UP( (uintptr_t) &buf[ 1 ], 128 ); + + for ( n = 16; n <= 128 ; n *= 2 ) { + for ( i = 0; i < 3; ++i ) { + uintptr_t j; + + for ( j = 0; j < 3; ++j ) { + rtems_cache_invalidate_multiple_data_lines( + (const void *) ( data + 1 - i ), + n + 1 - j + ); + } + } + } + } + + static void CallInvalidateMultipleInstructionLines( void ) + { + uintptr_t data; + uintptr_t n; + uintptr_t i; + + rtems_cache_invalidate_multiple_instruction_lines( NULL, 0 ); + data = (uintptr_t) rtems_cache_invalidate_multiple_instruction_lines; + + for ( n = 16; n <= 128 ; n *= 2 ) { + for ( i = 0; i < 3; ++i ) { + uintptr_t j; + + for ( j = 0; j < 3; ++j ) { + rtems_cache_invalidate_multiple_instruction_lines( + (const void *) ( data + 1 - i ), + n + 1 - j + ); + } + } + } + } + + static void CallInstructionSyncAfterCodeChange( void ) + { + uintptr_t data; + uintptr_t n; + uintptr_t i; + + rtems_cache_instruction_sync_after_code_change( NULL, 0 ); + data = (uintptr_t) rtems_cache_instruction_sync_after_code_change; + + for ( n = 16; n <= 128 ; n *= 2 ) { + for ( i = 0; i < 3; ++i ) { + uintptr_t j; + + for ( j = 0; j < 3; ++j ) { + rtems_cache_instruction_sync_after_code_change( + (const void *) ( data + 1 - i ), + n + 1 - j + ); + } + } + } + } + + static void CallGetDataSize( void ) + { + uint32_t level; + size_t n; + + level = 0; + + do { + n = rtems_cache_get_data_cache_size( level ); + ++level; + } while (n != 0 ); + } + + static void CallGetInstructionSize( void ) + { + uint32_t level; + size_t n; + + level = 0; + + do { + n = rtems_cache_get_instruction_cache_size( level ); + ++level; + } while (n != 0 ); + } +test-target: testsuites/validation/tc-cache.c +test-teardown: null +type: test-case |