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When trying to compile RTEMS for the Stellaris LM3S6965 board, I had an
issue of pppd.exe's .rodata section being too big to fit in the board's
memory image (region 'ROM_INT' overflowed).
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This reverts commit d9ff8b3e687a0ec56cac6463ba01ba7775eccd41.
It is not that simple:
https://sourceware.org/ml/binutils/2014-06/msg00062.html
On Fri, Jun 06, 2014 at 01:31:48PM +0200, Sebastian Huber wrote:
> On 2014-06-06 13:23, Sebastian Huber wrote:
> >Ok, so this "cmplwi cr0, rX, ppc_exc_lock_std@sdarel" is illegal,
> >since
> >ppc_exc_lock_std@sdarel is signed and the immediate is unsigned
> >16-bit? The
> >assembler doesn't issue a warning about this.
> >
> >Exists there a way to rescue this cmplwi hack without relaxing the
> >overflow
> >checks?
>
> Hm, sorry, it was surprisingly simple. This works:
>
> "cmplwi cr0, rX, ppc_exc_lock_std@sdarel@l"
>
> I was not aware that you can add several @ in a row.
That is the wrong thing to use here. sdarel@l translates to a VLE
reloc which applies to a split 16-bit field in VLE insns.
You want
cmpwi cr0, rX, ppc_exc_lock_std@sdarel
to properly compare a 16-bit signed number from sym@sdarel.
Note that the assembler does error if you write something like
cmplwi 3,-30000
or
cmpwi 3,40000
so what the linker is now doing is extending this behaviour to link
time.
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See also
https://sourceware.org/ml/binutils/2014-06/msg00059.html
On Fri, Jun 06, 2014 at 11:01:10AM +0200, Sebastian Huber wrote:
> I performed a git bisect and found this:
>
> 93d1b056cb396d6468781fe0e40dd769891bed32 is the first bad commit
> commit 93d1b056cb396d6468781fe0e40dd769891bed32
> Author: Alan Modra <amodra@gmail.com>
> Date: Tue May 20 11:42:42 2014 +0930
>
> Rewrite ppc32 backend .sdata and .sdata2 handling
Hmm, I'm surprised that your git bisect found this patch. Was
_SDA_BASE_ set differently before this?
> 0x00000000000dfc00 _SDA_BASE_
> 0x00000000000d7f78 ppc_exc_lock_std
> 4b8: 28 05 00 00 cmplwi r5,0
> 4ba: R_PPC_SDAREL16 ppc_exc_lock_std
ppc_exc_lock_std@sdarel will be calculating 0xd7f78 - 0xdfc00
which is 0xf...fff8378, and that falls foul of
commit 86c9573369616e7437481b6e5533aef3a435cdcf
Author: Alan Modra <amodra@gmail.com>
Date: Sat Mar 8 13:05:06 2014 +1030
Better overflow checking for powerpc32 relocations
cmplwi has an *unsigned* 16-bit field, and we now check the overflow
properly.
I wonder how many more of these we'll hit, and whether the uproar will
be enough that I'll be forced to relax the checks?
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The nanoseconds extension returned wrong values on secondary processors
since some of the global timer registeres are banked. Use global
variables instead.
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Do not touch the L1 caches since they have been initialized by the start
hooks.
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Use arm_a9mpcore_start_hook_0(). The L2 cache is now disabled.
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Use value for standard U-Boot.
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Define ARM_CP15_TEXT_SECTION to BSP_START_TEXT_SECTION so that the
start code is in the right section.
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Allow users of this header file to optionally place the inline functions
into a non-standard section.
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Delete superfluous/incorrect interrupt disable/enable.
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Invalidate entire branch predictor array.
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Enable SCU only on the boot processor.
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Add arm_a9mpcore_start_enable_smp_in_auxiliary_control().
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Add arm_a9mpcore_start_on_secondary_processor(). Rely on error checks
in _SMP_Start_multitasking_on_secondary_processor().
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The GRETH doesn't support IP fragments.
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Guest systems in paravirtualization environments run usually in user
mode. Thus it is not possible to directly access the PSR and TBR
registers. Use functions instead of inline assembler to access these
registers if RTEMS_PARAVIRT is defined.
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The last optimization missed was incorrect in regards to
PSR write instruction delay must be 3 instructions.
New optimizations:
* align to 32-byte cache line.
* rearrange code into three "blocks" of 4 instructions that
is executed by syscall 2 and 3. This is to optimize for
16/32 byte cache lines.
* use delay-slot instruction in trap table to reduce by one
instruction.
* use the fact that "wr %PSR" implements XOR to reduce by
one instruction.
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The following BSPs do not have tick support so the tests fail:
arm1136jfs
arm1136js
arm7tdmi
arm920
armcortexa9 (does not run any more)
avrtest
h8sim
h8sxsim
m32csim
m32rsim
moxiesim
simsh1
simsh2
simsh4
v850e1sim
v850e2sim
v850e2v3sim
v850esim
v850essim
v850sim
This list was provided by Joel in the following post:
http://www.rtems.org/pipermail/rtems-devel/2014-April/006526.html
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Network mbufs and clusters now are cached. Thus the nocache heap can get reduced to 1 MByte.
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Switch to the standard ARM startup code. This requires adding the
standard interrupt code. The interrupt code does nothing at this
point in time. I do not know if the ARM simulator in GDB supports
interrupts.
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The syscall functions overlapped with RTEMS, for example _write, _read, etc.
Change these to be internal to the BSP and avoid any clash with names in
RTEMS. Add support for SWI_Write0.
Change the console driver to use SWI_Write0. This outputs the character
to the host's stdout. Writing to file name 0 is not captured and managed
by GDB's simulation code while the SWI_Write0 is. The managed stdout
data is encapulated in the MI protocol while writes to file handle 0 are
dropped by GDB when in MI mode.
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The exit SPARC system call doesn't have a function entry
point like the others do. This is probably why people use
TA 0x0 instruction directly for shutting down the system.
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The Zynq BSPs can be used with varations of hardware such as memory size.
This option lets you set a length.
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This value can be found the xparameters.h file generated by the
Xilinx tools.
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