Age | Commit message (Collapse) | Author |
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Reimplemented the baud-rate algorithm from scratch to cope with
GRCAN, GRCANFD and OC_CAN devices.
Update #4323.
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When the DMA table has been allocated dynamically, the IOCTL_SET_PACKETSIZE
will trigger an issue where pDev->rx and pDev->tx are not updated with
the new DMA tables base address. Instead the old pointers are used.
There is no point in reallocting the DMA tables because there is no
configuration option to it. Therefore the DMA tables allocation is
moved to a separate function never called from SET_PACKETSIZE.
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This is enables the updated codec for GR740 and is backwards compatible
with all other versions of the IP.
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Update #4336.
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Closes #4320
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Updates #4320
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Updates #4320
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This enables several testsuites that were initially disabled during
development.
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CID 1437650: Unchecked return value from library in rtems_shell_help().
Closes #4291
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CID 1255518: Unchecked return value from library in pwdgrp_init().
Closes #4282
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CID 1063856: Unchecked return value from library in
rtems_shell_main_chmod().
Closes #4281
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CID 1049146: Unchecked return value from library in get_clock().
CID 1049147: Unchecked return value from library in get_random_fd().
Closes #4280
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CID 1255318: Unchecked return value in display_line().
Updates #4257
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CID 1437613: Unused value in grcan_set_filter().
This fix was recommended by Daniel Hellstrom (daniel@gaisler.com).
Closes #4301
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CID 1399773: Unsigned compared against 0 in brm_write().
Closes #4295
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CID 1399768: Unsigned compared against 0 in satcan_ioctl().
Closes #4294
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CID 1437630: Unchecked return value from library in gr_cpci_gr740_init1().
Closes #4290
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CID 1399785: Unchecked return value from library in gr_tmtc_1553_init1().
Closes #4289
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CID 1399783: Unchecked return value from library in gr701_init1().
Closes #4288
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CID 1399780: Unchecked return value from library in gr_rasta_adcdac_init1().
Closes #4287
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CID 1399771: Unchecked return value from library in gr_rasta_tmtc_init1().
Closes #4286
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CID 1399767: Unchecked return value error from library in gr_cpci_leon4_n2x_init1().
Closes #4285
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CID 1399723: Missing break in switch in pci_read_addressable().
Closes #4279
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CID 1399763: Unchecked return value from library in gr_rasta_io_init1().
Closes #4284
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CID 1399760: Unchecked return value from library in gr_rasta_spw_router_init1().
Closes #4283
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CID 1399726: Missing break in switch in task_usage().
CID 1399728: Missing break in switch in task_usage().
CID 1399742: Missing break in switch in task_usage().
Closes #4278
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CID 1399761: Missing break in switch in process_dma().
CID 1399765: Missing break in switch in process_dma().
CID 1399766: Missing break in switch in process_dma().
CID 1399777: Missing break in switch in process_dma().
Closes #4277
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CID 1399781: Unchecked return value in grspw_device_init().
Closes #4259
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The current ZynqMP BSPs don't have _qemu in their name as do all other
RTEMS BSPs that are specifically made to run on QEMU. This fixes the
naming for those ZynqMP BSP variants for easier identification.
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Add the stub necessary to boot on AArch64 under EL2 and drop to EL1 for
normal operation.
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Run with stack alignment faults enabled under RTEMS_DEBUG to catch any
stack misalignments early. This makes it easier to track them down
should they ever occur.
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AArch64 on hardware is often started at EL2 instead of EL1 from either
u-boot or a first stage bootloader. This allows RTEMS to drop from EL2
execution to EL1 to operate as normal.
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According to commentary on GCC bug
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99143, the alignment
behavior of linker sections on which RTEMS has relied was never
guaranteed to be consistent across platforms and any alignment
requirements for linker sections needs to be enforced explicitly.
This adds those explicit alignment requirements.
Closes #4255.
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ZynqMP hardware appears to have an odd hard-wired SGI implementation in
which the SGIs are permanently set as enabled or disabled. Allow the
TM27 IRQs to be overridden as necessary.
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Remove usage of SUBALIGN() in aarch64 linkcmds which works around a
difference in behavior on AArch64 platforms. This is no longer necessary
since alignment is now enforced explicitly.
Closes #4178.
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The Per_CPU_Control::isr_dispatch_disable is a 32-bit integer.
Close #4206.
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Make sure that a user-provided stack size is the minimum size allocated
for the stack.
Make sure we meet the stack alignment requirement also for CPU ports
with CPU_STACK_ALIGNMENT > CPU_HEAP_ALIGNMENT.
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Ensure that CONFIGURE_MAXIMUM_THREAD_LOCAL_STORAGE_SIZE meets the task
storage alignment requirement.
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