diff options
| author | Jarielle Catbagan <jcatbagan93@gmail.com> | 2015-07-16 04:26:44 -0700 |
|---|---|---|
| committer | Ed Sutter <edsutterjr@gmail.com> | 2015-07-18 09:13:25 -0400 |
| commit | 8a80d54c3f7ffd73ab86b1ac482e2040f0d63135 (patch) | |
| tree | 72e6a89820c8f87944146a4fcd8d66bcdd403208 | |
| parent | BBB: cpuio.c/rom_reset.S: Configure the MPU, Core, DDR, and Per PLLs and init... (diff) | |
| download | umon-8a80d54c3f7ffd73ab86b1ac482e2040f0d63135.tar.bz2 | |
BBB: rom_reset.S: Initialize the SP at the top of SRAM prior to invoking pll_init and ddr_init
| -rw-r--r-- | ports/beagleboneblack/rom_reset.S | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/ports/beagleboneblack/rom_reset.S b/ports/beagleboneblack/rom_reset.S index e44e816..98701a4 100644 --- a/ports/beagleboneblack/rom_reset.S +++ b/ports/beagleboneblack/rom_reset.S @@ -171,8 +171,13 @@ warmstart: bic r0, r0, #0x1f /* clear all mode bits */ orr r0, r0, #0x13 /* set System mode bits */ msr CPSR_c, r0 /* move back to CPSR */ - /* Reset the stack pointer for the SVC mode (our current mode) */ - ldr sp, =(MonStack + MONSTACKSIZE - 4) + + /* Initialize the SP at the top of SRAM outside of the uMon code + * space so that the following two C functions can be invoked + * properly to take care of PLL and DDR3 initialization. + */ + movw sp, #0x5e00 + movt sp, #0x4030 /* Initialize the MPU, Core, DDR, and Per PLLs. Furthermore, * initialize the external DDR3 memory as well. @@ -181,6 +186,9 @@ dev_init: bl pll_init bl ddr_init + /* Reset the stack pointer for the SVC mode (our current mode) */ + ldr sp, =(MonStack + MONSTACKSIZE - 4) + /* * Restore argument which was saved to r11 and jump to * the C function start(). |