Silence warnings when compiled with LLVM

10 files changed, 94 insertions, 98 deletions

diff --git a/elf.c b/elf.c
index 6736dcc..2a73ce3 100644
--- a/elf.c
+++ b/elf.c
@@ -51,7 +51,7 @@ read_elf_header (FILE * fp)
   efile.fp = fp;
 
   if ((ehdr.e_ident[EI_MAG0] != 0x7f) ||
-      strncmp (&ehdr.e_ident[EI_MAG1], "ELF", 3) != 0)
+      strncmp ((char *) &ehdr.e_ident[EI_MAG1], "ELF", 3) != 0)
     {
       return (-1);
     }
diff --git a/erc32.c b/erc32.c
index ff95dc6..190941e 100644
--- a/erc32.c
+++ b/erc32.c
@@ -253,9 +253,8 @@ static uint32	gpt_counter_read (void);
 static void	gpt_scaler_set (uint32 val);
 static void	gpt_reload_set (uint32 val);
 static void	timer_ctrl (uint32 val);
-static unsigned char *
-		get_mem_ptr (uint32 addr, uint32 size);
-static void	store_bytes (unsigned char *mem, uint32 waddr,
+static char	*get_mem_ptr (uint32 addr, uint32 size);
+static void	store_bytes (char *mem, uint32 waddr,
 			uint32 *data, int sz, int32 *ws);
 
 /* One-time init */
@@ -1467,7 +1466,7 @@ timer_ctrl(val)
    wait-states.  */
 
 static void
-store_bytes (unsigned char *mem, uint32 waddr, uint32 *data, int32 sz,
+store_bytes (char *mem, uint32 waddr, uint32 *data, int32 sz,
 	     int32 *ws)
 {
     switch (sz) {
@@ -1624,7 +1623,7 @@ memory_write (uint32 addr, uint32 *data, int32 sz, int32 *ws)
     return 1;
 }
 
-static unsigned char  *
+static char  *
 get_mem_ptr(addr, size)
     uint32          addr;
     uint32          size;
@@ -1661,7 +1660,7 @@ sis_memory_read(addr, data, length)
 {
     char           *mem;
     int            ws;
-    int            w4;
+    unsigned int   w4;
 
     if (length == 4) {
 	memory_read (addr, &w4, &ws);
diff --git a/func.c b/func.c
index d5eb83f..437837c 100644
--- a/func.c
+++ b/func.c
@@ -61,8 +61,8 @@ int		port = 1234;
 int		sim_run = 0;
 
 /* RAM and ROM for all systems */
-unsigned char romb[ROM_SIZE];
-unsigned char ramb[RAM_SIZE];
+char romb[ROM_SIZE];
+char ramb[RAM_SIZE];
 const struct memsys *ms = &erc32sys;
 int		cputype = 0;		/* 0 = erc32, 2 = leon2,3 = leon3, 5 = riscv */
 int             sis_gdb_break;
@@ -146,8 +146,8 @@ int
 exec_cmd(const char *cmd)
 {
     char           *cmd1, *cmd2;
-    int32           stat;
-    uint32          len, i, clen, j;
+    int32           stat, i;
+    uint32          len, clen, j;
     char           *cmdsave, *cmdsave2 = NULL;
 
     stat = OK;
@@ -691,7 +691,7 @@ init_signals()
 
 void print_insn_sis(uint32 addr)
 {
-    unsigned char           i[4];
+    char           i[4];
 
     ms->sis_memory_read (addr, i, 4);
     arch->disas(addr );
@@ -705,7 +705,7 @@ disp_mem(addr, len)
 
     uint32          i;
     union {
-	    unsigned char u8[4];
+	    char u8[4];
 	    uint32 u32;
     } data;
     uint32          mem[4], j;
@@ -890,10 +890,7 @@ check_bpt(sregs)
 }
 
 int
-check_wpr(sregs, address, mask)
-    struct pstate  *sregs;
-    int32          address;
-    unsigned char  mask;
+check_wpr( struct pstate *sregs, int32 address, unsigned char mask)
 {
     int32           i, msk;
 
@@ -909,10 +906,7 @@ check_wpr(sregs, address, mask)
 }
 
 int
-check_wpw(sregs, address, mask)
-    struct pstate  *sregs;
-    int32          address;
-    unsigned char  mask;
+check_wpw( struct pstate *sregs, int32 address, unsigned char mask)
 {
     int32           i, msk;
 
@@ -1062,7 +1056,7 @@ sim_timeout(int32 arg)
 
 /* simulate one core time-wise */
 
-static int
+static void
 run_sim_core(sregs, ntime, deb, dis)
     struct pstate  *sregs;
     uint64 ntime;
diff --git a/interf.c b/interf.c
index e79a6cb..d1e368b 100644
--- a/interf.c
+++ b/interf.c
@@ -81,7 +81,7 @@ sim_create_inferior()
 }
 
 int
-sim_write (uint32 mem, const unsigned char *buf, int length)
+sim_write (uint32 mem, const char *buf, int length)
 {
     int i, len;
 
@@ -92,7 +92,7 @@ sim_write (uint32 mem, const unsigned char *buf, int length)
 }
 
 int
-sim_read (uint32 mem, unsigned char *buf, int length)
+sim_read (uint32 mem, char *buf, int length)
 {
     int i, len;
 
diff --git a/leon2.c b/leon2.c
index d2d1b65..a2f7ebf 100644
--- a/leon2.c
+++ b/leon2.c
@@ -156,8 +156,8 @@ static void gpt_init (void);
 static void gpt_reset (void);
 static void gpt_scaler_set (uint32 val);
 static void timer_ctrl (uint32 val, int i);
-static unsigned char *get_mem_ptr (uint32 addr, uint32 size);
-static void store_bytes (unsigned char *mem, uint32 waddr,
+static char *get_mem_ptr (uint32 addr, uint32 size);
+static void store_bytes (char *mem, uint32 waddr,
 			 uint32 * data, int sz, int32 * ws);
 
 /* One-time init. */
@@ -791,7 +791,7 @@ timer_ctrl (uint32 val, int i)
    2 (one word), or 3 (two words); WS should return the number of wait-states. */
 
 static void
-store_bytes (unsigned char *mem, uint32 waddr, uint32 * data, int32 sz,
+store_bytes (char *mem, uint32 waddr, uint32 * data, int32 sz,
 	     int32 * ws)
 {
   switch (sz)
@@ -916,7 +916,7 @@ memory_write (uint32 addr, uint32 * data, int32 sz, int32 * ws)
   return 1;
 }
 
-static unsigned char *
+static char *
 get_mem_ptr (uint32 addr, uint32 size)
 {
   if ((addr + size) < ROM_END)
@@ -932,7 +932,7 @@ get_mem_ptr (uint32 addr, uint32 size)
 }
 
 static int
-sis_memory_write (uint32 addr, const unsigned char *data, uint32 length)
+sis_memory_write (uint32 addr, const char *data, uint32 length)
 {
   char *mem;
 
@@ -948,7 +948,7 @@ sis_memory_read (uint32 addr, char *data, uint32 length)
 {
   char *mem;
   int ws;
-  int w4;
+  unsigned int w4;
 
   if (length == 4)
     {
diff --git a/leon3.c b/leon3.c
index b770cb4..f2b0127 100644
--- a/leon3.c
+++ b/leon3.c
@@ -167,8 +167,8 @@ static void gpt_init (void);
 static void gpt_reset (void);
 static void gpt_scaler_set (uint32 val);
 static void timer_ctrl (uint32 val, int i);
-static unsigned char *get_mem_ptr (uint32 addr, uint32 size);
-static void store_bytes (unsigned char *mem, uint32 waddr,
+static char *get_mem_ptr (uint32 addr, uint32 size);
+static void store_bytes (char *mem, uint32 waddr,
 			 uint32 * data, int sz, int32 * ws);
 static void gpt_add_intr (int i);
 
@@ -620,7 +620,7 @@ port_init (void)
 {
   f1in = stdin;
   f1out = stdout;
-  if (uart_dev1[0] != 0)
+  if (uart_dev1[0] != 0) {
     if ((fd1 = open (uart_dev1, O_RDWR | O_NONBLOCK)) < 0)
       {
 	printf ("Warning, couldn't open output device %s\n", uart_dev1);
@@ -633,6 +633,7 @@ port_init (void)
 	setbuf (f1out, NULL);
 	f1open = 1;
       }
+  }
   if (f1in)
     ifd1 = fileno (f1in);
   if (ifd1 == 0)
@@ -942,7 +943,7 @@ static void
 gpt_scaler_set (uint32 val)
 {
   /* Mask for 16-bit scaler. */
-  if (gpt_scaler != val & 0x0ffff)
+  if (gpt_scaler != (val & 0x0ffff))
     {
       gpt_scaler = val & 0x0ffff;
       remove_event (gpt_intr, -1);
@@ -975,7 +976,7 @@ timer_ctrl (uint32 val, int i)
    2 (one word), or 3 (two words); WS should return the number of wait-states. */
 
 static void
-store_bytes (unsigned char *mem, uint32 waddr, uint32 * data, int32 sz,
+store_bytes (char *mem, uint32 waddr, uint32 * data, int32 sz,
 	     int32 * ws)
 {
   if (sz == 2)
@@ -1112,7 +1113,7 @@ memory_write (uint32 addr, uint32 * data, int32 sz, int32 * ws)
   return 1;
 }
 
-static unsigned char *
+static char *
 get_mem_ptr (uint32 addr, uint32 size)
 {
   if ((addr + size) < ROM_END)
@@ -1128,7 +1129,7 @@ get_mem_ptr (uint32 addr, uint32 size)
 }
 
 static int
-sis_memory_write (uint32 addr, const unsigned char *data, uint32 length)
+sis_memory_write (uint32 addr, const char *data, uint32 length)
 {
   char *mem;
   int32 ws;
diff --git a/remote.c b/remote.c
index f7d0d7b..7cc7344 100644
--- a/remote.c
+++ b/remote.c
@@ -147,12 +147,12 @@ check_pkg (unsigned char *buf, int len)
 }
 
 static void
-int2hex (unsigned char *hexbuf, unsigned char *intbuf, int len)
+int2hex (char *hexbuf, char *intbuf, int len)
 {
   int i;
   for (i = 0; i < len; i++)
     {
-      hexbuf[i * 2] = hexchars[intbuf[i] >> 4];
+      hexbuf[i * 2] = hexchars[(intbuf[i] >> 4) & 0x0f];
       hexbuf[i * 2 + 1] = hexchars[intbuf[i] & 0x0f];
     }
   hexbuf[len * 2] = 0;
@@ -182,11 +182,11 @@ sim_stat ()
 int
 gdb_remote_exec (char *buf)
 {
-  unsigned char membuf[1024];
+  char membuf[1024];
   unsigned int i, j, len, addr;
   int cont = 1;
-  unsigned char *cptr, *mptr;
-  unsigned char *txbuf = &sendbuf[1];
+  char *cptr, *mptr;
+  char *txbuf = &sendbuf[1];
 
   switch (buf[0])
     {
@@ -373,8 +373,10 @@ gdb_remote_exec (char *buf)
 	{
 	  cptr = &buf[6];
 	  mptr = membuf;
-	  while (*cptr != '#')
-	    *mptr++ = (hex (*cptr++) << 4) | hex (*cptr++);
+	  while (*cptr != '#') {
+	    *mptr = hex (*cptr++) << 4;
+	    *mptr++ |= hex (*cptr++);
+	  }
 	  *mptr = 0;
 	  exec_cmd (membuf);
 	  strcpy (txbuf, "OK");
@@ -394,7 +396,7 @@ gdb_remote_exec (char *buf)
 void
 gdb_remote (int port)
 {
-  char buffer[2048];
+  unsigned char buffer[2048];
   int cont = 1;
   int res, len = 0;
   char ack = '+';
@@ -411,7 +413,7 @@ gdb_remote (int port)
   printf ("gdb: listening on port %d ", port);
   while (cont)
     {
-      if (cont = create_socket (port))
+      if ((cont = create_socket (port)))
 	{
 	  send (new_socket, &ack, 1, 0);
 	  printf ("connected\n");
@@ -465,7 +467,7 @@ gdb_remote (int port)
 	      else
 		{
 		  strcpy (sendbuf, "$");
-		  cont = gdb_remote_exec (&buffer[res]);
+		  cont = gdb_remote_exec ((char *) &buffer[res]);
 		  if (sis_verbose)
 		    printf ("tx: %s\n", sendbuf);
 		  send (new_socket, sendbuf, strlen (sendbuf), 0);
diff --git a/riscv.c b/riscv.c
index 326fc3b..8b2e734 100644
--- a/riscv.c
+++ b/riscv.c
@@ -136,8 +136,8 @@ riscv_dispatch_instruction (sregs)
      struct pstate *sregs;
 {
 
-  uint32 op1, op2, op3, rd, rs1, rs2, npc, btrue, inst;
-  int32 sop1, sop2, *wdata, result, offset;
+  uint32 op1, op2, op3, rd, rs1, rs2, npc, btrue, inst, *wdata;
+  int32 sop1, sop2, result, offset;
   int32 pc, data, address, ws, mexc, fcc;
   unsigned char op, funct3, funct5, rs1p, rs2p, funct2, frs1, frs2, frd;
   int64 sop64a, sop64b;
@@ -179,7 +179,7 @@ riscv_dispatch_instruction (sregs)
 		  sregs->wpaddress = address;
 		  break;
 		}
-	      mexc = ms->memory_read (address, &data, &ws);
+	      mexc = ms->memory_read (address, &op1, &ws);
 	      sregs->hold += ws;
 	      if (mexc)
 		{
@@ -188,7 +188,7 @@ riscv_dispatch_instruction (sregs)
 		}
 	      else
 		{
-		  sregs->g[rs2p] = data;
+		  sregs->g[rs2p] = op1;
 		}
 	      break;
 	    case CSW:		/* sw rs2', offset[6:2](rs1') */
@@ -213,7 +213,7 @@ riscv_dispatch_instruction (sregs)
 		  sregs->wpaddress = address;
 		  break;
 		}
-	      mexc = ms->memory_read (address, &data, &ws);
+	      mexc = ms->memory_read (address, &op1, &ws);
 	      sregs->hold += ws;
 	      if (mexc)
 		{
@@ -222,7 +222,7 @@ riscv_dispatch_instruction (sregs)
 		}
 	      else
 		{
-		  sregs->fsi[rs2p << 1] = data;
+		  sregs->fsi[rs2p << 1] = op1;
 #ifdef FPU_D_ENABLED
 		  sregs->fsi[(rs2p << 1) + 1] = -1;
 #endif
@@ -238,9 +238,9 @@ riscv_dispatch_instruction (sregs)
 		  sregs->wpaddress = address;
 		  break;
 		}
-	      mexc = ms->memory_read (address, &data, &ws);
+	      mexc = ms->memory_read (address, &op1, &ws);
 	      sregs->hold += ws;
-	      mexc |= ms->memory_read (address + 4, &result, &ws);
+	      mexc |= ms->memory_read (address + 4, &op2, &ws);
 	      sregs->hold += ws;
 	      if (mexc)
 		{
@@ -249,8 +249,8 @@ riscv_dispatch_instruction (sregs)
 		}
 	      else
 		{
-		  sregs->fsi[rs2p << 1] = data;
-		  sregs->fsi[(rs2p << 1) + 1] = result;
+		  sregs->fsi[rs2p << 1] = op1;
+		  sregs->fsi[(rs2p << 1) + 1] = op2;
 		}
 	      break;
 #endif
@@ -432,7 +432,7 @@ riscv_dispatch_instruction (sregs)
 		  sregs->wpaddress = address;
 		  break;
 		}
-	      mexc = ms->memory_read (address, &data, &ws);
+	      mexc = ms->memory_read (address, &op1, &ws);
 	      sregs->hold += ws;
 	      if (mexc)
 		{
@@ -441,7 +441,7 @@ riscv_dispatch_instruction (sregs)
 		}
 	      else
 		{
-		  sregs->g[rs1] = data;
+		  sregs->g[rs1] = op1;
 		}
 	      break;
 #ifdef FPU_D_ENABLED
@@ -453,10 +453,10 @@ riscv_dispatch_instruction (sregs)
 		  sregs->wpaddress = address;
 		  break;
 		}
-	      mexc = ms->memory_read (address, &data, &ws);
+	      mexc = ms->memory_read (address, &op1, &ws);
 	      sregs->hold += ws;
 	      if (!mexc)
-		mexc = ms->memory_read (address + 4, &result, &ws);
+		mexc = ms->memory_read (address + 4, &op2, &ws);
 	      sregs->hold += ws;
 	      if (mexc)
 		{
@@ -465,8 +465,8 @@ riscv_dispatch_instruction (sregs)
 		}
 	      else
 		{
-		  sregs->fsi[rs1 << 1] = data;
-		  sregs->fsi[(rs1 << 1) + 1] = result;
+		  sregs->fsi[rs1 << 1] = op1;
+		  sregs->fsi[(rs1 << 1) + 1] = op2;
 		}
 	      break;
 #endif
@@ -478,7 +478,7 @@ riscv_dispatch_instruction (sregs)
 		  sregs->wpaddress = address;
 		  break;
 		}
-	      mexc = ms->memory_read (address, &data, &ws);
+	      mexc = ms->memory_read (address, &op1, &ws);
 	      sregs->hold += ws;
 	      if (mexc)
 		{
@@ -487,7 +487,7 @@ riscv_dispatch_instruction (sregs)
 		}
 	      else
 		{
-		  sregs->fsi[rs1 << 1] = data;
+		  sregs->fsi[rs1 << 1] = op1;
 		}
 	      break;
 	    case 4:
@@ -1022,7 +1022,7 @@ riscv_dispatch_instruction (sregs)
 		  sregs->wpaddress = address;
 		  break;
 		}
-	      mexc = ms->memory_read (address, &data, &ws);
+	      mexc = ms->memory_read (address, &op1, &ws);
 	      sregs->hold += ws;
 	      if (mexc)
 		{
@@ -1031,7 +1031,7 @@ riscv_dispatch_instruction (sregs)
 		}
 	      else
 		{
-		  sregs->g[rd] = data;
+		  sregs->g[rd] = op1;
 		}
 	      break;
 	    case LB:
@@ -1040,7 +1040,7 @@ riscv_dispatch_instruction (sregs)
 		  sregs->trap = TRAP_ILLEG;
 		  break;
 		}
-	      mexc = ms->memory_read (address, &data, &ws);
+	      mexc = ms->memory_read (address, (uint32 *) &data, &ws);
 	      sregs->hold += ws;
 	      if (mexc)
 		{
@@ -1052,7 +1052,7 @@ riscv_dispatch_instruction (sregs)
 	      sregs->g[rd] = data;
 	      break;
 	    case LBU:
-	      mexc = ms->memory_read (address, &data, &ws);
+	      mexc = ms->memory_read (address, &op1, &ws);
 	      sregs->hold += ws;
 	      if (mexc)
 		{
@@ -1060,7 +1060,7 @@ riscv_dispatch_instruction (sregs)
 		  sregs->wpaddress = address;
 		  break;
 		}
-	      sregs->g[rd] = data & 0x0ff;
+	      sregs->g[rd] = op1 & 0x0ff;
 	      break;
 	    case LH:
 	      if (address & 0x1)
@@ -1069,7 +1069,7 @@ riscv_dispatch_instruction (sregs)
 		  sregs->wpaddress = address;
 		  break;
 		}
-	      mexc = ms->memory_read (address, &data, &ws);
+	      mexc = ms->memory_read (address, (uint32 *) &data, &ws);
 	      sregs->hold += ws;
 	      if (mexc)
 		{
@@ -1087,7 +1087,7 @@ riscv_dispatch_instruction (sregs)
 		  sregs->wpaddress = address;
 		  break;
 		}
-	      mexc = ms->memory_read (address, &data, &ws);
+	      mexc = ms->memory_read (address, &op1, &ws);
 	      sregs->hold += ws;
 	      if (mexc)
 		{
@@ -1095,8 +1095,8 @@ riscv_dispatch_instruction (sregs)
 		  sregs->wpaddress = address;
 		  break;
 		}
-	      data &= 0x0ffff;
-	      sregs->g[rd] = data;
+	      op1 &= 0x0ffff;
+	      sregs->g[rd] = op1;
 	      break;
 
 	    default:
@@ -1126,7 +1126,7 @@ riscv_dispatch_instruction (sregs)
 		  sregs->wpaddress = address;
 		  break;
 		}
-	      mexc = ms->memory_read (address, &data, &ws);
+	      mexc = ms->memory_read (address, &op1, &ws);
 	      sregs->hold += ws;
 	      if (mexc)
 		{
@@ -1135,7 +1135,7 @@ riscv_dispatch_instruction (sregs)
 		}
 	      else
 		{
-		  sregs->g[rd] = data;
+		  sregs->g[rd] = op1;
 		  sregs->lrqa = address;
 		  sregs->lrq = 1;
 #ifdef DEBUG
@@ -1191,7 +1191,7 @@ riscv_dispatch_instruction (sregs)
 		  sregs->wpaddress = address;
 		  break;
 		}
-	      mexc = ms->memory_read (address, &data, &ws);
+	      mexc = ms->memory_read (address, (uint32 *) &data, &ws);
 	      sregs->hold += ws;
 	      if (mexc)
 		{
@@ -1357,7 +1357,7 @@ riscv_dispatch_instruction (sregs)
 		  sregs->wpaddress = address;
 		  break;
 		}
-	      mexc = ms->memory_read (address, &data, &ws);
+	      mexc = ms->memory_read (address, &op1, &ws);
 	      sregs->hold += ws;
 	      if (mexc)
 		{
@@ -1366,7 +1366,7 @@ riscv_dispatch_instruction (sregs)
 		}
 	      else
 		{
-		  sregs->fsi[rd << 1] = data;
+		  sregs->fsi[rd << 1] = op1;
 		  sregs->fsi[(rd << 1) + 1] = -1;
 		}
 	      break;
@@ -1377,10 +1377,10 @@ riscv_dispatch_instruction (sregs)
 		  sregs->wpaddress = address;
 		  break;
 		}
-	      mexc = ms->memory_read (address, &data, &ws);
+	      mexc = ms->memory_read (address, &op1, &ws);
 	      sregs->hold += ws;
 	      if (!mexc)
-		mexc = ms->memory_read (address + 4, &result, &ws);
+		mexc = ms->memory_read (address + 4, &op2, &ws);
 	      sregs->hold += ws;
 	      if (mexc)
 		{
@@ -1389,8 +1389,8 @@ riscv_dispatch_instruction (sregs)
 		}
 	      else
 		{
-		  sregs->fsi[rd << 1] = data;
-		  sregs->fsi[(rd << 1) + 1] = result;
+		  sregs->fsi[rd << 1] = op1;
+		  sregs->fsi[(rd << 1) + 1] = op2;
 		}
 	      break;
 	    default:
@@ -3216,7 +3216,7 @@ riscv_print_insn (uint32 addr)
 {
   char tmp[128];
   uint32 insn;
-  uint32 hold;
+  int32 hold;
 
   ms->memory_iread (addr, &insn, &hold);
   riscv_disas (tmp, addr, insn);
diff --git a/sis.h b/sis.h
index f4e2dab..13caddd 100644
--- a/sis.h
+++ b/sis.h
@@ -246,8 +246,8 @@ extern const struct cpu_arch riscv;
 extern const struct memsys erc32sys;
 
 /* func.c */
-extern unsigned char romb[];
-extern unsigned char ramb[];
+extern char romb[];
+extern char ramb[];
 extern struct	pstate  sregs[];
 extern struct   estate ebase;
 extern struct   evcell evbuf[];
@@ -341,7 +341,7 @@ struct memsys {
     int	        (*memory_read) (uint32 addr, uint32 *data, int32 *ws);
     int	        (*memory_write) (uint32 addr, uint32 *data, int32 sz, int32 *ws);
     int	        (*sis_memory_write) (uint32 addr,
-				  const unsigned char *data, uint32 length);
+				  const char *data, uint32 length);
     int	        (*sis_memory_read) (uint32 addr, char *data,
 				 uint32 length);
     void	(*boot_init) (void);
@@ -363,8 +363,8 @@ extern int      new_socket;
 
 /* interf.c */
 
-extern int 	sim_read (uint32 mem, unsigned char *buf, int length);
-extern int 	sim_write (uint32 mem, const unsigned char *buf, int length);
+extern int 	sim_read (uint32 mem, char *buf, int length);
+extern int 	sim_write (uint32 mem, const char *buf, int length);
 extern void 	sim_create_inferior();
 extern void 	sim_resume(int step);
 extern int 	sim_insert_swbreakpoint(uint32 addr, int len);
diff --git a/sparc.c b/sparc.c
index 229fac1..0daed96 100644
--- a/sparc.c
+++ b/sparc.c
@@ -93,7 +93,7 @@ wpmask (uint32 op3)
       return (0);		/* byte */
     case 2:
       return (1);		/* half-word */
-    case 3:
+    default:
       return (7);		/* double word */
     }
 }
@@ -136,10 +136,10 @@ sparc_dispatch_instruction (sregs)
 {
 
   uint32 cwp, op, op2, op3, asi, rd, cond, rs1, rs2;
-  uint32 ldep, icc;
-  int32 operand1, operand2, *rdd, result, eicc, new_cwp;
-  int32 pc, npc, data, address, ws, mexc, fcc, annul;
-  int32 ddata[2];
+  uint32 ldep, icc, *rdd, data;
+  int32 operand1, operand2, result, eicc, new_cwp;
+  int32 pc, npc, address, ws, mexc, fcc, annul;
+  uint32 ddata[2];
 
   sregs->ninst++;
   cwp = ((sregs->psr & PSR_CWP) << 4);
@@ -856,7 +856,7 @@ sparc_dispatch_instruction (sregs)
 		  break;
 		}
 	      sregs->psr = (sregs->psr & 0xff000000) |
-		(rs1 ^ operand2) & 0x00f03fff;
+		((rs1 ^ operand2) & 0x00f03fff);
 	      break;
 	    case WRWIM:
 	      if (!(sregs->psr & PSR_S))
@@ -963,7 +963,7 @@ sparc_dispatch_instruction (sregs)
 	  sregs->icnt = T_ST;	/* Set store instruction count */
 	  if (ebase.wpwnum)
 	    {
-	      if (ebase.wphit = check_wpw (sregs, address, wpmask (op3)))
+	      if ((ebase.wphit = check_wpw (sregs, address, wpmask (op3))))
 		{
 		  sregs->trap = WPT_TRAP;
 		  break;
@@ -978,7 +978,7 @@ sparc_dispatch_instruction (sregs)
 	  sregs->icnt = T_LD;	/* Set load instruction count */
 	  if (ebase.wprnum)
 	    {
-	      if (ebase.wphit = check_wpr (sregs, address, wpmask (op3)))
+	      if ((ebase.wphit = check_wpr (sregs, address, wpmask (op3))))
 		{
 		  sregs->trap = WPT_TRAP;
 		  break;
@@ -3458,7 +3458,7 @@ sparc_print_insn (uint32 addr)
 {
   char tmp[128];
   uint32 insn;
-  uint32 hold;
+  int32 hold;
 
   ms->memory_iread (addr, &insn, &hold);
   sparc_disas (tmp, addr, insn);