/* SPDX-License-Identifier: BSD-2-Clause */

/**
 * @file
 *
 * @ingroup RTEMSDeviceGRLIB
 *
 * @brief This header file defines the L4STAT register block interface.
 */

/*
 * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */

/*
 * This file is part of the RTEMS quality process and was automatically
 * generated.  If you find something that needs to be fixed or
 * worded better please post a report or patch to an RTEMS mailing list
 * or raise a bug report:
 *
 * https://www.rtems.org/bugs.html
 *
 * For information on updating and regenerating please refer to the How-To
 * section in the Software Requirements Engineering chapter of the
 * RTEMS Software Engineering manual.  The manual is provided as a part of
 * a release.  For development sources please refer to the online
 * documentation at:
 *
 * https://docs.rtems.org
 */

/* Generated from spec:/dev/grlib/if/l4stat-header */

#ifndef _DEV_GRLIB_L4STAT_H
#define _DEV_GRLIB_L4STAT_H

#ifdef __cplusplus
extern "C" {
#endif

/* Generated from spec:/dev/grlib/if/l4stat */

/**
 * @defgroup DevGrlibIfL4stat L4STAT
 *
 * @ingroup RTEMSDeviceGRLIB
 *
 * @brief This group contains the L4STAT interfaces.
 *
 * @{
 */

/**
 * @defgroup DevGrlibIfL4statCVAL CVAL
 *
 * @brief Counter 0-15 value register
 *
 * @{
 */

#define L4STAT_CVAL_CVAL_SHIFT 0
#define L4STAT_CVAL_CVAL_MASK 0xffffffffU
#define L4STAT_CVAL_CVAL_GET( _reg ) \
  ( ( ( _reg ) >> 0 ) & 0xffffffffU )
#define L4STAT_CVAL_CVAL( _val ) ( ( _val ) << 0 )

/** @} */

/**
 * @defgroup DevGrlibIfL4statCCTRL CCTRL
 *
 * @brief Counter 0-15 control register
 *
 * @{
 */

#define L4STAT_CCTRL_NCPU_SHIFT 28
#define L4STAT_CCTRL_NCPU_MASK 0xf0000000U
#define L4STAT_CCTRL_NCPU_GET( _reg ) \
  ( ( ( _reg ) >> 28 ) & 0xfU )
#define L4STAT_CCTRL_NCPU( _val ) ( ( _val ) << 28 )

#define L4STAT_CCTRL_NCNT_SHIFT 23
#define L4STAT_CCTRL_NCNT_MASK 0xf800000U
#define L4STAT_CCTRL_NCNT_GET( _reg ) \
  ( ( ( _reg ) >> 23 ) & 0x1fU )
#define L4STAT_CCTRL_NCNT( _val ) ( ( _val ) << 23 )

#define L4STAT_CCTRL_MC 0x400000U

#define L4STAT_CCTRL_IA 0x200000U

#define L4STAT_CCTRL_DS 0x100000U

#define L4STAT_CCTRL_EE 0x80000U

#define L4STAT_CCTRL_AE 0x40000U

#define L4STAT_CCTRL_EL 0x20000U

#define L4STAT_CCTRL_CD 0x10000U

#define L4STAT_CCTRL_SU_SHIFT 14
#define L4STAT_CCTRL_SU_MASK 0xc000U
#define L4STAT_CCTRL_SU_GET( _reg ) \
  ( ( ( _reg ) >> 14 ) & 0x3U )
#define L4STAT_CCTRL_SU( _val ) ( ( _val ) << 14 )

#define L4STAT_CCTRL_CL 0x2000U

#define L4STAT_CCTRL_EN 0x1000U

#define L4STAT_CCTRL_EVENT_ID_SHIFT 4
#define L4STAT_CCTRL_EVENT_ID_MASK 0xff0U
#define L4STAT_CCTRL_EVENT_ID_GET( _reg ) \
  ( ( ( _reg ) >> 4 ) & 0xffU )
#define L4STAT_CCTRL_EVENT_ID( _val ) ( ( _val ) << 4 )

#define L4STAT_CCTRL_CPU_AHBM_SHIFT 0
#define L4STAT_CCTRL_CPU_AHBM_MASK 0xfU
#define L4STAT_CCTRL_CPU_AHBM_GET( _reg ) \
  ( ( ( _reg ) >> 0 ) & 0xfU )
#define L4STAT_CCTRL_CPU_AHBM( _val ) ( ( _val ) << 0 )

/** @} */

/**
 * @defgroup DevGrlibIfL4statCSVAL CSVAL
 *
 * @brief Counter 0-15 max/latch register
 *
 * @{
 */

#define L4STAT_CSVAL_CSVAL_SHIFT 0
#define L4STAT_CSVAL_CSVAL_MASK 0xffffffffU
#define L4STAT_CSVAL_CSVAL_GET( _reg ) \
  ( ( ( _reg ) >> 0 ) & 0xffffffffU )
#define L4STAT_CSVAL_CSVAL( _val ) ( ( _val ) << 0 )

/** @} */

/**
 * @defgroup DevGrlibIfL4statTSTAMP TSTAMP
 *
 * @brief Timestamp register
 *
 * @{
 */

#define L4STAT_TSTAMP_TSTAMP_SHIFT 0
#define L4STAT_TSTAMP_TSTAMP_MASK 0xffffffffU
#define L4STAT_TSTAMP_TSTAMP_GET( _reg ) \
  ( ( ( _reg ) >> 0 ) & 0xffffffffU )
#define L4STAT_TSTAMP_TSTAMP( _val ) ( ( _val ) << 0 )

/** @} */

/**
 * @brief This structure defines the L4STAT register block memory map.
 */
typedef struct {
  /**
   * @brief See @ref DevGrlibIfL4statCVAL.
   */
  uint32_t cval_0;

  uint32_t reserved_4_3c[ 14 ];

  /**
   * @brief See @ref DevGrlibIfL4statCVAL.
   */
  uint32_t cval_1;

  uint32_t reserved_40_80[ 16 ];

  /**
   * @brief See @ref DevGrlibIfL4statCCTRL.
   */
  uint32_t cctrl_0;

  uint32_t reserved_84_cc[ 18 ];

  /**
   * @brief See @ref DevGrlibIfL4statCCTRL.
   */
  uint32_t cctrl_1;

  uint32_t reserved_d0_100[ 12 ];

  /**
   * @brief See @ref DevGrlibIfL4statCSVAL.
   */
  uint32_t csval_0;

  uint32_t reserved_104_13c[ 14 ];

  /**
   * @brief See @ref DevGrlibIfL4statCSVAL.
   */
  uint32_t csval_1;

  uint32_t reserved_140_180[ 16 ];

  /**
   * @brief See @ref DevGrlibIfL4statTSTAMP.
   */
  uint32_t tstamp;
} l4stat;

/** @} */

#ifdef __cplusplus
}
#endif

#endif /* _DEV_GRLIB_L4STAT_H */