From 6855664ee60dd07ef0ac52e9e16fa31dc194f5bd Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Tue, 8 Jun 2021 15:53:18 +0200 Subject: grlib: Add generated headers --- bsps/include/grlib/ahbstat-regs.h | 150 +++++ bsps/include/grlib/ahbtrace-regs.h | 257 ++++++++ bsps/include/grlib/apbuart-regs.h | 246 ++++++++ bsps/include/grlib/dsu4-regs.h | 634 +++++++++++++++++++ bsps/include/grlib/ftmctrl-regs.h | 239 +++++++ bsps/include/grlib/gptimer-regs.h | 323 ++++++++++ bsps/include/grlib/gr1553b-regs.h | 1043 ++++++++++++++++++++++++++++++ bsps/include/grlib/gr740thsens-regs.h | 184 ++++++ bsps/include/grlib/grcan-regs.h | 561 +++++++++++++++++ bsps/include/grlib/grclkgate-regs.h | 177 ++++++ bsps/include/grlib/grethgbit-regs.h | 362 +++++++++++ bsps/include/grlib/grgpio-regs.h | 486 ++++++++++++++ bsps/include/grlib/grgprbank-regs.h | 439 +++++++++++++ bsps/include/grlib/grgpreg-regs.h | 128 ++++ bsps/include/grlib/griommu-regs.h | 654 +++++++++++++++++++ bsps/include/grlib/grpci2-regs.h | 679 ++++++++++++++++++++ bsps/include/grlib/grspw2-regs.h | 461 ++++++++++++++ bsps/include/grlib/grspwrouter-regs.h | 701 +++++++++++++++++++++ bsps/include/grlib/irqamp-regs.h | 636 +++++++++++++++++++ bsps/include/grlib/l2cache-regs.h | 590 +++++++++++++++++ bsps/include/grlib/l4stat-regs.h | 241 +++++++ bsps/include/grlib/memscrub-regs.h | 428 +++++++++++++ bsps/include/grlib/mmctrl-regs.h | 322 ++++++++++ bsps/include/grlib/spictrl-regs.h | 373 +++++++++++ bsps/include/grlib/spwpnp-regs.h | 427 +++++++++++++ bsps/include/grlib/spwrmap-regs.h | 1114 +++++++++++++++++++++++++++++++++ bsps/include/grlib/spwtdp-regs.h | 981 +++++++++++++++++++++++++++++ bsps/sparc/include/grlib/io.h | 210 +++++++ 28 files changed, 13046 insertions(+) create mode 100644 bsps/include/grlib/ahbstat-regs.h create mode 100644 bsps/include/grlib/ahbtrace-regs.h create mode 100644 bsps/include/grlib/apbuart-regs.h create mode 100644 bsps/include/grlib/dsu4-regs.h create mode 100644 bsps/include/grlib/ftmctrl-regs.h create mode 100644 bsps/include/grlib/gptimer-regs.h create mode 100644 bsps/include/grlib/gr1553b-regs.h create mode 100644 bsps/include/grlib/gr740thsens-regs.h create mode 100644 bsps/include/grlib/grcan-regs.h create mode 100644 bsps/include/grlib/grclkgate-regs.h create mode 100644 bsps/include/grlib/grethgbit-regs.h create mode 100644 bsps/include/grlib/grgpio-regs.h create mode 100644 bsps/include/grlib/grgprbank-regs.h create mode 100644 bsps/include/grlib/grgpreg-regs.h create mode 100644 bsps/include/grlib/griommu-regs.h create mode 100644 bsps/include/grlib/grpci2-regs.h create mode 100644 bsps/include/grlib/grspw2-regs.h create mode 100644 bsps/include/grlib/grspwrouter-regs.h create mode 100644 bsps/include/grlib/irqamp-regs.h create mode 100644 bsps/include/grlib/l2cache-regs.h create mode 100644 bsps/include/grlib/l4stat-regs.h create mode 100644 bsps/include/grlib/memscrub-regs.h create mode 100644 bsps/include/grlib/mmctrl-regs.h create mode 100644 bsps/include/grlib/spictrl-regs.h create mode 100644 bsps/include/grlib/spwpnp-regs.h create mode 100644 bsps/include/grlib/spwrmap-regs.h create mode 100644 bsps/include/grlib/spwtdp-regs.h create mode 100644 bsps/sparc/include/grlib/io.h diff --git a/bsps/include/grlib/ahbstat-regs.h b/bsps/include/grlib/ahbstat-regs.h new file mode 100644 index 0000000000..589c2bdf14 --- /dev/null +++ b/bsps/include/grlib/ahbstat-regs.h @@ -0,0 +1,150 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSDeviceGRLIBAHBSTAT + * + * @brief This header file defines the AHBSTAT register block interface. + */ + +/* + * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file is part of the RTEMS quality process and was automatically + * generated. If you find something that needs to be fixed or + * worded better please post a report or patch to an RTEMS mailing list + * or raise a bug report: + * + * https://www.rtems.org/bugs.html + * + * For information on updating and regenerating please refer to the How-To + * section in the Software Requirements Engineering chapter of the + * RTEMS Software Engineering manual. The manual is provided as a part of + * a release. For development sources please refer to the online + * documentation at: + * + * https://docs.rtems.org + */ + +/* Generated from spec:/dev/grlib/if/ahbstat-header */ + +#ifndef _GRLIB_AHBSTAT_REGS_H +#define _GRLIB_AHBSTAT_REGS_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Generated from spec:/dev/grlib/if/ahbstat */ + +/** + * @defgroup RTEMSDeviceGRLIBAHBSTAT AHBSTAT + * + * @ingroup RTEMSDeviceGRLIB + * + * @brief This group contains the AHBSTAT interfaces. + * + * @{ + */ + +/** + * @defgroup RTEMSDeviceGRLIBAHBSTATAHBS AHB Status register (AHBS) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define AHBSTAT_AHBS_ME 0x2000U + +#define AHBSTAT_AHBS_FW 0x1000U + +#define AHBSTAT_AHBS_CF 0x800U + +#define AHBSTAT_AHBS_AF 0x400U + +#define AHBSTAT_AHBS_CE 0x200U + +#define AHBSTAT_AHBS_NE 0x100U + +#define AHBSTAT_AHBS_HWRITE 0x80U + +#define AHBSTAT_AHBS_HMASTER_SHIFT 3 +#define AHBSTAT_AHBS_HMASTER_MASK 0x78U +#define AHBSTAT_AHBS_HMASTER_GET( _reg ) \ + ( ( ( _reg ) >> 3 ) & 0xfU ) +#define AHBSTAT_AHBS_HMASTER( _val ) ( ( _val ) << 3 ) + +#define AHBSTAT_AHBS_HSIZE_SHIFT 0 +#define AHBSTAT_AHBS_HSIZE_MASK 0x7U +#define AHBSTAT_AHBS_HSIZE_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0x7U ) +#define AHBSTAT_AHBS_HSIZE( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBAHBSTATAHBFAR \ + * AHB Failing address register (AHBFAR) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define AHBSTAT_AHBFAR_HADDR_SHIFT 0 +#define AHBSTAT_AHBFAR_HADDR_MASK 0xffffffffU +#define AHBSTAT_AHBFAR_HADDR_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define AHBSTAT_AHBFAR_HADDR( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @brief This structure defines the AHBSTAT register block memory map. + */ +typedef struct ahbstat { + /** + * @brief See @ref RTEMSDeviceGRLIBAHBSTATAHBS. + */ + uint32_t ahbs; + + /** + * @brief See @ref RTEMSDeviceGRLIBAHBSTATAHBFAR. + */ + uint32_t ahbfar; +} ahbstat; + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GRLIB_AHBSTAT_REGS_H */ diff --git a/bsps/include/grlib/ahbtrace-regs.h b/bsps/include/grlib/ahbtrace-regs.h new file mode 100644 index 0000000000..c269916c81 --- /dev/null +++ b/bsps/include/grlib/ahbtrace-regs.h @@ -0,0 +1,257 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSDeviceGRLIBAHBTRACE + * + * @brief This header file defines the AHBTRACE register block interface. + */ + +/* + * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file is part of the RTEMS quality process and was automatically + * generated. If you find something that needs to be fixed or + * worded better please post a report or patch to an RTEMS mailing list + * or raise a bug report: + * + * https://www.rtems.org/bugs.html + * + * For information on updating and regenerating please refer to the How-To + * section in the Software Requirements Engineering chapter of the + * RTEMS Software Engineering manual. The manual is provided as a part of + * a release. For development sources please refer to the online + * documentation at: + * + * https://docs.rtems.org + */ + +/* Generated from spec:/dev/grlib/if/ahbtrace-header */ + +#ifndef _GRLIB_AHBTRACE_REGS_H +#define _GRLIB_AHBTRACE_REGS_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Generated from spec:/dev/grlib/if/ahbtrace */ + +/** + * @defgroup RTEMSDeviceGRLIBAHBTRACE AHBTRACE + * + * @ingroup RTEMSDeviceGRLIB + * + * @brief This group contains the AHBTRACE interfaces. + * + * @{ + */ + +/** + * @defgroup RTEMSDeviceGRLIBAHBTRACECTRL Trace buffer control register (CTRL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define AHBTRACE_CTRL_DCNT_SHIFT 16 +#define AHBTRACE_CTRL_DCNT_MASK 0x7f0000U +#define AHBTRACE_CTRL_DCNT_GET( _reg ) \ + ( ( ( _reg ) >> 16 ) & 0x7fU ) +#define AHBTRACE_CTRL_DCNT( _val ) ( ( _val ) << 16 ) + +#define AHBTRACE_CTRL_PF 0x100U + +#define AHBTRACE_CTRL_BW_SHIFT 6 +#define AHBTRACE_CTRL_BW_MASK 0xc0U +#define AHBTRACE_CTRL_BW_GET( _reg ) \ + ( ( ( _reg ) >> 6 ) & 0x3U ) +#define AHBTRACE_CTRL_BW( _val ) ( ( _val ) << 6 ) + +#define AHBTRACE_CTRL_RF 0x20U + +#define AHBTRACE_CTRL_AF 0x10U + +#define AHBTRACE_CTRL_FR 0x8U + +#define AHBTRACE_CTRL_FW 0x4U + +#define AHBTRACE_CTRL_DM 0x2U + +#define AHBTRACE_CTRL_EN 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBAHBTRACEINDEX Trace buffer index register (INDEX) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define AHBTRACE_INDEX_INDEX_SHIFT 4 +#define AHBTRACE_INDEX_INDEX_MASK 0x7f0U +#define AHBTRACE_INDEX_INDEX_GET( _reg ) \ + ( ( ( _reg ) >> 4 ) & 0x7fU ) +#define AHBTRACE_INDEX_INDEX( _val ) ( ( _val ) << 4 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBAHBTRACETIMETAG \ + * Trace buffer time tag register (TIMETAG) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define AHBTRACE_TIMETAG_TIMETAG_SHIFT 0 +#define AHBTRACE_TIMETAG_TIMETAG_MASK 0xffffffffU +#define AHBTRACE_TIMETAG_TIMETAG_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define AHBTRACE_TIMETAG_TIMETAG( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBAHBTRACEMSFILT \ + * Trace buffer master/slave filter register (MSFILT) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define AHBTRACE_MSFILT_SMASK_15_0_SHIFT 16 +#define AHBTRACE_MSFILT_SMASK_15_0_MASK 0xffff0000U +#define AHBTRACE_MSFILT_SMASK_15_0_GET( _reg ) \ + ( ( ( _reg ) >> 16 ) & 0xffffU ) +#define AHBTRACE_MSFILT_SMASK_15_0( _val ) ( ( _val ) << 16 ) + +#define AHBTRACE_MSFILT_MMASK_15_0_SHIFT 0 +#define AHBTRACE_MSFILT_MMASK_15_0_MASK 0xffffU +#define AHBTRACE_MSFILT_MMASK_15_0_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffU ) +#define AHBTRACE_MSFILT_MMASK_15_0( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBAHBTRACETBBA \ + * Trace buffer break address registers (TBBA) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define AHBTRACE_TBBA_BADDR_31_2_SHIFT 2 +#define AHBTRACE_TBBA_BADDR_31_2_MASK 0xfffffffcU +#define AHBTRACE_TBBA_BADDR_31_2_GET( _reg ) \ + ( ( ( _reg ) >> 2 ) & 0x3fffffffU ) +#define AHBTRACE_TBBA_BADDR_31_2( _val ) ( ( _val ) << 2 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBAHBTRACETBBM \ + * Trace buffer break mask registers (TBBM) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define AHBTRACE_TBBM_BMASK_31_2_SHIFT 2 +#define AHBTRACE_TBBM_BMASK_31_2_MASK 0xfffffffcU +#define AHBTRACE_TBBM_BMASK_31_2_GET( _reg ) \ + ( ( ( _reg ) >> 2 ) & 0x3fffffffU ) +#define AHBTRACE_TBBM_BMASK_31_2( _val ) ( ( _val ) << 2 ) + +#define AHBTRACE_TBBM_LD 0x2U + +#define AHBTRACE_TBBM_ST 0x1U + +/** @} */ + +/** + * @brief This structure defines the AHBTRACE register block memory map. + */ +typedef struct ahbtrace { + /** + * @brief See @ref RTEMSDeviceGRLIBAHBTRACECTRL. + */ + uint32_t ctrl; + + /** + * @brief See @ref RTEMSDeviceGRLIBAHBTRACEINDEX. + */ + uint32_t index; + + /** + * @brief See @ref RTEMSDeviceGRLIBAHBTRACETIMETAG. + */ + uint32_t timetag; + + /** + * @brief See @ref RTEMSDeviceGRLIBAHBTRACEMSFILT. + */ + uint32_t msfilt; + + /** + * @brief See @ref RTEMSDeviceGRLIBAHBTRACETBBA. + */ + uint32_t tbba_0; + + /** + * @brief See @ref RTEMSDeviceGRLIBAHBTRACETBBM. + */ + uint32_t tbbm_0; + + /** + * @brief See @ref RTEMSDeviceGRLIBAHBTRACETBBA. + */ + uint32_t tbba_1; + + /** + * @brief See @ref RTEMSDeviceGRLIBAHBTRACETBBM. + */ + uint32_t tbbm_1; +} ahbtrace; + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GRLIB_AHBTRACE_REGS_H */ diff --git a/bsps/include/grlib/apbuart-regs.h b/bsps/include/grlib/apbuart-regs.h new file mode 100644 index 0000000000..9f0d7c95ba --- /dev/null +++ b/bsps/include/grlib/apbuart-regs.h @@ -0,0 +1,246 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSDeviceGRLIBAPBUART + * + * @brief This header file defines the APBUART register block interface. + */ + +/* + * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file is part of the RTEMS quality process and was automatically + * generated. If you find something that needs to be fixed or + * worded better please post a report or patch to an RTEMS mailing list + * or raise a bug report: + * + * https://www.rtems.org/bugs.html + * + * For information on updating and regenerating please refer to the How-To + * section in the Software Requirements Engineering chapter of the + * RTEMS Software Engineering manual. The manual is provided as a part of + * a release. For development sources please refer to the online + * documentation at: + * + * https://docs.rtems.org + */ + +/* Generated from spec:/dev/grlib/if/apbuart-header */ + +#ifndef _GRLIB_APBUART_REGS_H +#define _GRLIB_APBUART_REGS_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Generated from spec:/dev/grlib/if/apbuart */ + +/** + * @defgroup RTEMSDeviceGRLIBAPBUART APBUART + * + * @ingroup RTEMSDeviceGRLIB + * + * @brief This group contains the APBUART interfaces. + * + * @{ + */ + +/** + * @defgroup RTEMSDeviceGRLIBAPBUARTDATA UART data register (DATA) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define APBUART_DATA_DATA_SHIFT 0 +#define APBUART_DATA_DATA_MASK 0xffU +#define APBUART_DATA_DATA_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffU ) +#define APBUART_DATA_DATA( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBAPBUARTSTATUS UART status register (STATUS) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define APBUART_STATUS_RCNT_SHIFT 26 +#define APBUART_STATUS_RCNT_MASK 0xfc000000U +#define APBUART_STATUS_RCNT_GET( _reg ) \ + ( ( ( _reg ) >> 26 ) & 0x3fU ) +#define APBUART_STATUS_RCNT( _val ) ( ( _val ) << 26 ) + +#define APBUART_STATUS_TCNT_SHIFT 20 +#define APBUART_STATUS_TCNT_MASK 0x3f00000U +#define APBUART_STATUS_TCNT_GET( _reg ) \ + ( ( ( _reg ) >> 20 ) & 0x3fU ) +#define APBUART_STATUS_TCNT( _val ) ( ( _val ) << 20 ) + +#define APBUART_STATUS_RF 0x400U + +#define APBUART_STATUS_TF 0x200U + +#define APBUART_STATUS_RH 0x100U + +#define APBUART_STATUS_TH 0x80U + +#define APBUART_STATUS_FE 0x40U + +#define APBUART_STATUS_PE 0x20U + +#define APBUART_STATUS_OV 0x10U + +#define APBUART_STATUS_BR 0x8U + +#define APBUART_STATUS_TE 0x4U + +#define APBUART_STATUS_TS 0x2U + +#define APBUART_STATUS_DR 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBAPBUARTCTRL UART control register (CTRL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define APBUART_CTRL_FA 0x80000000U + +#define APBUART_CTRL_SI 0x4000U + +#define APBUART_CTRL_DI 0x2000U + +#define APBUART_CTRL_BI 0x1000U + +#define APBUART_CTRL_DB 0x800U + +#define APBUART_CTRL_RF 0x400U + +#define APBUART_CTRL_TF 0x200U + +#define APBUART_CTRL_EC 0x100U + +#define APBUART_CTRL_LB 0x80U + +#define APBUART_CTRL_FL 0x40U + +#define APBUART_CTRL_PE 0x20U + +#define APBUART_CTRL_PS 0x10U + +#define APBUART_CTRL_TI 0x8U + +#define APBUART_CTRL_RI 0x4U + +#define APBUART_CTRL_TE 0x2U + +#define APBUART_CTRL_RE 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBAPBUARTSCALER UART scaler reload register (SCALER) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define APBUART_SCALER_SCALER_RELOAD_VALUE_SHIFT 0 +#define APBUART_SCALER_SCALER_RELOAD_VALUE_MASK 0xfffffU +#define APBUART_SCALER_SCALER_RELOAD_VALUE_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xfffffU ) +#define APBUART_SCALER_SCALER_RELOAD_VALUE( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBAPBUARTFIFO UART FIFO debug register (FIFO) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define APBUART_FIFO_DATA_SHIFT 0 +#define APBUART_FIFO_DATA_MASK 0xffU +#define APBUART_FIFO_DATA_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffU ) +#define APBUART_FIFO_DATA( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @brief This structure defines the APBUART register block memory map. + */ +typedef struct apbuart { + /** + * @brief See @ref RTEMSDeviceGRLIBAPBUARTDATA. + */ + uint32_t data; + + /** + * @brief See @ref RTEMSDeviceGRLIBAPBUARTSTATUS. + */ + uint32_t status; + + /** + * @brief See @ref RTEMSDeviceGRLIBAPBUARTCTRL. + */ + uint32_t ctrl; + + /** + * @brief See @ref RTEMSDeviceGRLIBAPBUARTSCALER. + */ + uint32_t scaler; + + /** + * @brief See @ref RTEMSDeviceGRLIBAPBUARTFIFO. + */ + uint32_t fifo; +} apbuart; + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GRLIB_APBUART_REGS_H */ diff --git a/bsps/include/grlib/dsu4-regs.h b/bsps/include/grlib/dsu4-regs.h new file mode 100644 index 0000000000..30f104ab88 --- /dev/null +++ b/bsps/include/grlib/dsu4-regs.h @@ -0,0 +1,634 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSDeviceGRLIBDSU4 + * + * @brief This header file defines the DSU4 register block interface. + */ + +/* + * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file is part of the RTEMS quality process and was automatically + * generated. If you find something that needs to be fixed or + * worded better please post a report or patch to an RTEMS mailing list + * or raise a bug report: + * + * https://www.rtems.org/bugs.html + * + * For information on updating and regenerating please refer to the How-To + * section in the Software Requirements Engineering chapter of the + * RTEMS Software Engineering manual. The manual is provided as a part of + * a release. For development sources please refer to the online + * documentation at: + * + * https://docs.rtems.org + */ + +/* Generated from spec:/dev/grlib/if/dsu4-header */ + +#ifndef _GRLIB_DSU4_REGS_H +#define _GRLIB_DSU4_REGS_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Generated from spec:/dev/grlib/if/dsu4 */ + +/** + * @defgroup RTEMSDeviceGRLIBDSU4 DSU4 + * + * @ingroup RTEMSDeviceGRLIB + * + * @brief This group contains the DSU4 interfaces. + * + * @{ + */ + +/** + * @defgroup RTEMSDeviceGRLIBDSU4CTRL DSU control register (CTRL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define DSU4_CTRL_PW 0x800U + +#define DSU4_CTRL_HL 0x400U + +#define DSU4_CTRL_PE 0x200U + +#define DSU4_CTRL_EB 0x100U + +#define DSU4_CTRL_EE 0x80U + +#define DSU4_CTRL_DM 0x40U + +#define DSU4_CTRL_BZ 0x20U + +#define DSU4_CTRL_BX 0x10U + +#define DSU4_CTRL_BS 0x8U + +#define DSU4_CTRL_BW 0x4U + +#define DSU4_CTRL_BE 0x2U + +#define DSU4_CTRL_TE 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBDSU4DTTC DSU time tag counter register (DTTC) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define DSU4_DTTC_TIMETAG_SHIFT 0 +#define DSU4_DTTC_TIMETAG_MASK 0xffffffffU +#define DSU4_DTTC_TIMETAG_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define DSU4_DTTC_TIMETAG( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBDSU4BRSS DSU break and single step register (BRSS) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define DSU4_BRSS_SS_3_0_SHIFT 16 +#define DSU4_BRSS_SS_3_0_MASK 0xf0000U +#define DSU4_BRSS_SS_3_0_GET( _reg ) \ + ( ( ( _reg ) >> 16 ) & 0xfU ) +#define DSU4_BRSS_SS_3_0( _val ) ( ( _val ) << 16 ) + +#define DSU4_BRSS_BN_3_0_SHIFT 0 +#define DSU4_BRSS_BN_3_0_MASK 0xfU +#define DSU4_BRSS_BN_3_0_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xfU ) +#define DSU4_BRSS_BN_3_0( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBDSU4DBGM DSU debug mode mask register (DBGM) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define DSU4_DBGM_DM_3_0_SHIFT 16 +#define DSU4_DBGM_DM_3_0_MASK 0xf0000U +#define DSU4_DBGM_DM_3_0_GET( _reg ) \ + ( ( ( _reg ) >> 16 ) & 0xfU ) +#define DSU4_DBGM_DM_3_0( _val ) ( ( _val ) << 16 ) + +#define DSU4_DBGM_ED_3_0_SHIFT 0 +#define DSU4_DBGM_ED_3_0_MASK 0xfU +#define DSU4_DBGM_ED_3_0_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xfU ) +#define DSU4_DBGM_ED_3_0( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBDSU4DTR DSU trap register (DTR) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define DSU4_DTR_EM 0x1000U + +#define DSU4_DTR_TRAPTYPE_SHIFT 4 +#define DSU4_DTR_TRAPTYPE_MASK 0xff0U +#define DSU4_DTR_TRAPTYPE_GET( _reg ) \ + ( ( ( _reg ) >> 4 ) & 0xffU ) +#define DSU4_DTR_TRAPTYPE( _val ) ( ( _val ) << 4 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBDSU4DASI DSU ASI diagnostic access register (DASI) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define DSU4_DASI_ASI_SHIFT 0 +#define DSU4_DASI_ASI_MASK 0xffU +#define DSU4_DASI_ASI_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffU ) +#define DSU4_DASI_ASI( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBDSU4ATBC AHB trace buffer control register (ATBC) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define DSU4_ATBC_DCNT_SHIFT 16 +#define DSU4_ATBC_DCNT_MASK 0xff0000U +#define DSU4_ATBC_DCNT_GET( _reg ) \ + ( ( ( _reg ) >> 16 ) & 0xffU ) +#define DSU4_ATBC_DCNT( _val ) ( ( _val ) << 16 ) + +#define DSU4_ATBC_DF 0x100U + +#define DSU4_ATBC_SF 0x80U + +#define DSU4_ATBC_TE 0x40U + +#define DSU4_ATBC_TF 0x20U + +#define DSU4_ATBC_BW_SHIFT 3 +#define DSU4_ATBC_BW_MASK 0x18U +#define DSU4_ATBC_BW_GET( _reg ) \ + ( ( ( _reg ) >> 3 ) & 0x3U ) +#define DSU4_ATBC_BW( _val ) ( ( _val ) << 3 ) + +#define DSU4_ATBC_BR 0x4U + +#define DSU4_ATBC_DM 0x2U + +#define DSU4_ATBC_EN 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBDSU4ATBI AHB trace buffer index register (ATBI) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define DSU4_ATBI_INDEX_SHIFT 4 +#define DSU4_ATBI_INDEX_MASK 0xff0U +#define DSU4_ATBI_INDEX_GET( _reg ) \ + ( ( ( _reg ) >> 4 ) & 0xffU ) +#define DSU4_ATBI_INDEX( _val ) ( ( _val ) << 4 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBDSU4ATBFC \ + * AHB trace buffer filter control register (ATBFC) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define DSU4_ATBFC_WPF_SHIFT 12 +#define DSU4_ATBFC_WPF_MASK 0x3000U +#define DSU4_ATBFC_WPF_GET( _reg ) \ + ( ( ( _reg ) >> 12 ) & 0x3U ) +#define DSU4_ATBFC_WPF( _val ) ( ( _val ) << 12 ) + +#define DSU4_ATBFC_BPF_SHIFT 8 +#define DSU4_ATBFC_BPF_MASK 0x300U +#define DSU4_ATBFC_BPF_GET( _reg ) \ + ( ( ( _reg ) >> 8 ) & 0x3U ) +#define DSU4_ATBFC_BPF( _val ) ( ( _val ) << 8 ) + +#define DSU4_ATBFC_PF 0x8U + +#define DSU4_ATBFC_AF 0x4U + +#define DSU4_ATBFC_FR 0x2U + +#define DSU4_ATBFC_FW 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBDSU4ATBFM \ + * AHB trace buffer filter mask register (ATBFM) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define DSU4_ATBFM_SMASK_15_0_SHIFT 16 +#define DSU4_ATBFM_SMASK_15_0_MASK 0xffff0000U +#define DSU4_ATBFM_SMASK_15_0_GET( _reg ) \ + ( ( ( _reg ) >> 16 ) & 0xffffU ) +#define DSU4_ATBFM_SMASK_15_0( _val ) ( ( _val ) << 16 ) + +#define DSU4_ATBFM_MMASK_15_0_SHIFT 0 +#define DSU4_ATBFM_MMASK_15_0_MASK 0xffffU +#define DSU4_ATBFM_MMASK_15_0_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffU ) +#define DSU4_ATBFM_MMASK_15_0( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBDSU4ATBBA \ + * AHB trace buffer break address registers (ATBBA) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define DSU4_ATBBA_BADDR_31_2_SHIFT 2 +#define DSU4_ATBBA_BADDR_31_2_MASK 0xfffffffcU +#define DSU4_ATBBA_BADDR_31_2_GET( _reg ) \ + ( ( ( _reg ) >> 2 ) & 0x3fffffffU ) +#define DSU4_ATBBA_BADDR_31_2( _val ) ( ( _val ) << 2 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBDSU4ATBBM \ + * AHB trace buffer break mask registers (ATBBM) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define DSU4_ATBBM_BMASK_31_2_SHIFT 2 +#define DSU4_ATBBM_BMASK_31_2_MASK 0xfffffffcU +#define DSU4_ATBBM_BMASK_31_2_GET( _reg ) \ + ( ( ( _reg ) >> 2 ) & 0x3fffffffU ) +#define DSU4_ATBBM_BMASK_31_2( _val ) ( ( _val ) << 2 ) + +#define DSU4_ATBBM_LD 0x2U + +#define DSU4_ATBBM_ST 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBDSU4ICNT Instruction trace count register (ICNT) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define DSU4_ICNT_CE 0x80000000U + +#define DSU4_ICNT_IC 0x40000000U + +#define DSU4_ICNT_PE 0x20000000U + +#define DSU4_ICNT_ICOUNT_28_0_SHIFT 0 +#define DSU4_ICNT_ICOUNT_28_0_MASK 0x1fffffffU +#define DSU4_ICNT_ICOUNT_28_0_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0x1fffffffU ) +#define DSU4_ICNT_ICOUNT_28_0( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBDSU4AHBWPC \ + * AHB watchpoint control register (AHBWPC) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define DSU4_AHBWPC_IN 0x40U + +#define DSU4_AHBWPC_CP 0x20U + +#define DSU4_AHBWPC_EN 0x10U + +#define DSU4_AHBWPC_IN 0x4U + +#define DSU4_AHBWPC_CP 0x2U + +#define DSU4_AHBWPC_EN 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBDSU4AHBWPD AHB watchpoint data registers (AHBWPD) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define DSU4_AHBWPD_DATA_SHIFT 0 +#define DSU4_AHBWPD_DATA_MASK 0xffffffffU +#define DSU4_AHBWPD_DATA_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define DSU4_AHBWPD_DATA( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBDSU4AHBWPM AHB watchpoint mask registers (AHBWPM) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define DSU4_AHBWPM_MASK_SHIFT 0 +#define DSU4_AHBWPM_MASK_MASK 0xffffffffU +#define DSU4_AHBWPM_MASK_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define DSU4_AHBWPM_MASK( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBDSU4ITBC0 \ + * Instruction trace buffer control register 0 (ITBC0) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define DSU4_ITBC0_TFILT_SHIFT 28 +#define DSU4_ITBC0_TFILT_MASK 0xf0000000U +#define DSU4_ITBC0_TFILT_GET( _reg ) \ + ( ( ( _reg ) >> 28 ) & 0xfU ) +#define DSU4_ITBC0_TFILT( _val ) ( ( _val ) << 28 ) + +#define DSU4_ITBC0_ITPOINTER_SHIFT 0 +#define DSU4_ITBC0_ITPOINTER_MASK 0xffffU +#define DSU4_ITBC0_ITPOINTER_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffU ) +#define DSU4_ITBC0_ITPOINTER( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBDSU4ITBC1 \ + * Instruction trace buffer control register 1 (ITBC1) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define DSU4_ITBC1_WO 0x8000000U + +#define DSU4_ITBC1_TLIM_SHIFT 24 +#define DSU4_ITBC1_TLIM_MASK 0x7000000U +#define DSU4_ITBC1_TLIM_GET( _reg ) \ + ( ( ( _reg ) >> 24 ) & 0x7U ) +#define DSU4_ITBC1_TLIM( _val ) ( ( _val ) << 24 ) + +#define DSU4_ITBC1_TOV 0x800000U + +/** @} */ + +/** + * @brief This structure defines the DSU4 register block memory map. + */ +typedef struct dsu4 { + /** + * @brief See @ref RTEMSDeviceGRLIBDSU4CTRL. + */ + uint32_t ctrl; + + uint32_t reserved_4_8; + + /** + * @brief See @ref RTEMSDeviceGRLIBDSU4DTTC. + */ + uint32_t dttc; + + uint32_t reserved_c_20[ 5 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBDSU4BRSS. + */ + uint32_t brss; + + /** + * @brief See @ref RTEMSDeviceGRLIBDSU4DBGM. + */ + uint32_t dbgm; + + uint32_t reserved_28_40[ 6 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBDSU4ATBC. + */ + uint32_t atbc; + + /** + * @brief See @ref RTEMSDeviceGRLIBDSU4ATBI. + */ + uint32_t atbi; + + /** + * @brief See @ref RTEMSDeviceGRLIBDSU4ATBFC. + */ + uint32_t atbfc; + + /** + * @brief See @ref RTEMSDeviceGRLIBDSU4ATBFM. + */ + uint32_t atbfm; + + /** + * @brief See @ref RTEMSDeviceGRLIBDSU4ATBBA. + */ + uint32_t atbba_0; + + /** + * @brief See @ref RTEMSDeviceGRLIBDSU4ATBBM. + */ + uint32_t atbbm_0; + + /** + * @brief See @ref RTEMSDeviceGRLIBDSU4ATBBA. + */ + uint32_t atbba_1; + + /** + * @brief See @ref RTEMSDeviceGRLIBDSU4ATBBM. + */ + uint32_t atbbm_1; + + uint32_t reserved_60_70[ 4 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBDSU4ICNT. + */ + uint32_t icnt; + + uint32_t reserved_74_80[ 3 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBDSU4AHBWPC. + */ + uint32_t ahbwpc; + + uint32_t reserved_84_90[ 3 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBDSU4AHBWPD. + */ + uint32_t ahbwpd_0; + + uint32_t reserved_94_9c[ 2 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBDSU4AHBWPD. + */ + uint32_t ahbwpd_1; + + /** + * @brief See @ref RTEMSDeviceGRLIBDSU4AHBWPM. + */ + uint32_t ahbwpm_0; + + uint32_t reserved_a4_ac[ 2 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBDSU4AHBWPM. + */ + uint32_t ahbwpm_1; + + /** + * @brief See @ref RTEMSDeviceGRLIBDSU4AHBWPD. + */ + uint32_t ahbwpd_2; + + uint32_t reserved_b4_bc[ 2 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBDSU4AHBWPD. + */ + uint32_t ahbwpd_3; + + /** + * @brief See @ref RTEMSDeviceGRLIBDSU4AHBWPM. + */ + uint32_t ahbwpm_2; + + uint32_t reserved_c4_cc[ 2 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBDSU4AHBWPM. + */ + uint32_t ahbwpm_3; + + uint32_t reserved_d0_110000[ 278476 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBDSU4ITBC0. + */ + uint32_t itbc0; + + /** + * @brief See @ref RTEMSDeviceGRLIBDSU4ITBC1. + */ + uint32_t itbc1; + + uint32_t reserved_110008_400020[ 770054 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBDSU4DTR. + */ + uint32_t dtr; + + /** + * @brief See @ref RTEMSDeviceGRLIBDSU4DASI. + */ + uint32_t dasi; +} dsu4; + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GRLIB_DSU4_REGS_H */ diff --git a/bsps/include/grlib/ftmctrl-regs.h b/bsps/include/grlib/ftmctrl-regs.h new file mode 100644 index 0000000000..7b53f1eb30 --- /dev/null +++ b/bsps/include/grlib/ftmctrl-regs.h @@ -0,0 +1,239 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSDeviceGRLIBFTMCTRL + * + * @brief This header file defines the FTMCTRL register block interface. + */ + +/* + * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file is part of the RTEMS quality process and was automatically + * generated. If you find something that needs to be fixed or + * worded better please post a report or patch to an RTEMS mailing list + * or raise a bug report: + * + * https://www.rtems.org/bugs.html + * + * For information on updating and regenerating please refer to the How-To + * section in the Software Requirements Engineering chapter of the + * RTEMS Software Engineering manual. The manual is provided as a part of + * a release. For development sources please refer to the online + * documentation at: + * + * https://docs.rtems.org + */ + +/* Generated from spec:/dev/grlib/if/ftmctrl-header */ + +#ifndef _GRLIB_FTMCTRL_REGS_H +#define _GRLIB_FTMCTRL_REGS_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Generated from spec:/dev/grlib/if/ftmctrl */ + +/** + * @defgroup RTEMSDeviceGRLIBFTMCTRL FTMCTRL + * + * @ingroup RTEMSDeviceGRLIB + * + * @brief This group contains the FTMCTRL interfaces. + * + * @{ + */ + +/** + * @defgroup RTEMSDeviceGRLIBFTMCTRLMCFG1 \ + * Memory configuration register 1 (MCFG1) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define FTMCTRL_MCFG1_PBRDY 0x80000000U + +#define FTMCTRL_MCFG1_ABRDY 0x40000000U + +#define FTMCTRL_MCFG1_IOBUSW 0x20000000U + +#define FTMCTRL_MCFG1_IBRDY_SHIFT 27 +#define FTMCTRL_MCFG1_IBRDY_MASK 0x18000000U +#define FTMCTRL_MCFG1_IBRDY_GET( _reg ) \ + ( ( ( _reg ) >> 27 ) & 0x3U ) +#define FTMCTRL_MCFG1_IBRDY( _val ) ( ( _val ) << 27 ) + +#define FTMCTRL_MCFG1_BEXCN 0x4000000U + +#define FTMCTRL_MCFG1_IO_WAITSTATES 0x1000000U + +#define FTMCTRL_MCFG1_IOEN_SHIFT 20 +#define FTMCTRL_MCFG1_IOEN_MASK 0xf00000U +#define FTMCTRL_MCFG1_IOEN_GET( _reg ) \ + ( ( ( _reg ) >> 20 ) & 0xfU ) +#define FTMCTRL_MCFG1_IOEN( _val ) ( ( _val ) << 20 ) + +#define FTMCTRL_MCFG1_ROMBANKSZ 0x80000U + +#define FTMCTRL_MCFG1_PWEN_SHIFT 14 +#define FTMCTRL_MCFG1_PWEN_MASK 0x3c000U +#define FTMCTRL_MCFG1_PWEN_GET( _reg ) \ + ( ( ( _reg ) >> 14 ) & 0xfU ) +#define FTMCTRL_MCFG1_PWEN( _val ) ( ( _val ) << 14 ) + +#define FTMCTRL_MCFG1_PROM_WIDTH_SHIFT 12 +#define FTMCTRL_MCFG1_PROM_WIDTH_MASK 0x3000U +#define FTMCTRL_MCFG1_PROM_WIDTH_GET( _reg ) \ + ( ( ( _reg ) >> 12 ) & 0x3U ) +#define FTMCTRL_MCFG1_PROM_WIDTH( _val ) ( ( _val ) << 12 ) + +#define FTMCTRL_MCFG1_PROM_WRITE_WS 0x800U + +#define FTMCTRL_MCFG1_PROM_READ_WS_SHIFT 8 +#define FTMCTRL_MCFG1_PROM_READ_WS_MASK 0x300U +#define FTMCTRL_MCFG1_PROM_READ_WS_GET( _reg ) \ + ( ( ( _reg ) >> 8 ) & 0x3U ) +#define FTMCTRL_MCFG1_PROM_READ_WS( _val ) ( ( _val ) << 8 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBFTMCTRLMCFG3 \ + * Memory configuration register 3 (MCFG3) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define FTMCTRL_MCFG3_ME 0x8000000U + +#define FTMCTRL_MCFG3_WB 0x800U + +#define FTMCTRL_MCFG3_RB 0x400U + +#define FTMCTRL_MCFG3_PE 0x100U + +#define FTMCTRL_MCFG3_TCB_SHIFT 0 +#define FTMCTRL_MCFG3_TCB_MASK 0xffU +#define FTMCTRL_MCFG3_TCB_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffU ) +#define FTMCTRL_MCFG3_TCB( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBFTMCTRLMCFG5 \ + * Memory configuration register 5 (MCFG5) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define FTMCTRL_MCFG5_IOHWS_SHIFT 23 +#define FTMCTRL_MCFG5_IOHWS_MASK 0x3f800000U +#define FTMCTRL_MCFG5_IOHWS_GET( _reg ) \ + ( ( ( _reg ) >> 23 ) & 0x7fU ) +#define FTMCTRL_MCFG5_IOHWS( _val ) ( ( _val ) << 23 ) + +#define FTMCTRL_MCFG5_ROMHWS_SHIFT 7 +#define FTMCTRL_MCFG5_ROMHWS_MASK 0x3f80U +#define FTMCTRL_MCFG5_ROMHWS_GET( _reg ) \ + ( ( ( _reg ) >> 7 ) & 0x7fU ) +#define FTMCTRL_MCFG5_ROMHWS( _val ) ( ( _val ) << 7 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBFTMCTRLMCFG7 \ + * Memory configuration register 7 (MCFG7) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define FTMCTRL_MCFG7_BRDYNCNT_SHIFT 16 +#define FTMCTRL_MCFG7_BRDYNCNT_MASK 0xffff0000U +#define FTMCTRL_MCFG7_BRDYNCNT_GET( _reg ) \ + ( ( ( _reg ) >> 16 ) & 0xffffU ) +#define FTMCTRL_MCFG7_BRDYNCNT( _val ) ( ( _val ) << 16 ) + +#define FTMCTRL_MCFG7_BRDYNRLD_SHIFT 0 +#define FTMCTRL_MCFG7_BRDYNRLD_MASK 0xffffU +#define FTMCTRL_MCFG7_BRDYNRLD_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffU ) +#define FTMCTRL_MCFG7_BRDYNRLD( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @brief This structure defines the FTMCTRL register block memory map. + */ +typedef struct ftmctrl { + /** + * @brief See @ref RTEMSDeviceGRLIBFTMCTRLMCFG1. + */ + uint32_t mcfg1; + + uint32_t reserved_4_8; + + /** + * @brief See @ref RTEMSDeviceGRLIBFTMCTRLMCFG3. + */ + uint32_t mcfg3; + + uint32_t reserved_c_10; + + /** + * @brief See @ref RTEMSDeviceGRLIBFTMCTRLMCFG5. + */ + uint32_t mcfg5; + + uint32_t reserved_14_18; + + /** + * @brief See @ref RTEMSDeviceGRLIBFTMCTRLMCFG7. + */ + uint32_t mcfg7; +} ftmctrl; + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GRLIB_FTMCTRL_REGS_H */ diff --git a/bsps/include/grlib/gptimer-regs.h b/bsps/include/grlib/gptimer-regs.h new file mode 100644 index 0000000000..d0d0001f80 --- /dev/null +++ b/bsps/include/grlib/gptimer-regs.h @@ -0,0 +1,323 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSDeviceGRLIBGPTIMER + * + * @brief This header file defines the GPTIMER register block interface. + */ + +/* + * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file is part of the RTEMS quality process and was automatically + * generated. If you find something that needs to be fixed or + * worded better please post a report or patch to an RTEMS mailing list + * or raise a bug report: + * + * https://www.rtems.org/bugs.html + * + * For information on updating and regenerating please refer to the How-To + * section in the Software Requirements Engineering chapter of the + * RTEMS Software Engineering manual. The manual is provided as a part of + * a release. For development sources please refer to the online + * documentation at: + * + * https://docs.rtems.org + */ + +/* Generated from spec:/dev/grlib/if/gptimer-header */ + +#ifndef _GRLIB_GPTIMER_REGS_H +#define _GRLIB_GPTIMER_REGS_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Generated from spec:/dev/grlib/if/group */ + +/** + * @defgroup RTEMSDeviceGRLIB GRLIB + * + * @ingroup RTEMSDeviceDrivers + * + * @brief This group contains the GRLIB interfaces. + */ + +/* Generated from spec:/dev/grlib/if/gptimer-timer */ + +/** + * @defgroup RTEMSDeviceGRLIBGPTIMERTimer GPTIMER TIMER + * + * @ingroup RTEMSDeviceGRLIBGPTIMER + * + * @brief This group contains the GPTIMER TIMER interfaces. + * + * @{ + */ + +/** + * @defgroup RTEMSDeviceGRLIBGPTIMERTimerTCNTVAL \ + * Timer n counter value register (TCNTVAL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GPTIMER_TCNTVAL_TCVAL_SHIFT 0 +#define GPTIMER_TCNTVAL_TCVAL_MASK 0xffffffffU +#define GPTIMER_TCNTVAL_TCVAL_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define GPTIMER_TCNTVAL_TCVAL( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBGPTIMERTimerTRLDVAL \ + * Timer n counter reload value register (TRLDVAL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GPTIMER_TRLDVAL_TRLDVAL_SHIFT 0 +#define GPTIMER_TRLDVAL_TRLDVAL_MASK 0xffffffffU +#define GPTIMER_TRLDVAL_TRLDVAL_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define GPTIMER_TRLDVAL_TRLDVAL( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBGPTIMERTimerTCTRL Timer n control register (TCTRL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GPTIMER_TCTRL_WS 0x100U + +#define GPTIMER_TCTRL_WN 0x80U + +#define GPTIMER_TCTRL_DH 0x40U + +#define GPTIMER_TCTRL_CH 0x20U + +#define GPTIMER_TCTRL_IP 0x10U + +#define GPTIMER_TCTRL_IE 0x8U + +#define GPTIMER_TCTRL_LD 0x4U + +#define GPTIMER_TCTRL_RS 0x2U + +#define GPTIMER_TCTRL_EN 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBGPTIMERTimerTLATCH Timer n latch register (TLATCH) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GPTIMER_TLATCH_LTCV_SHIFT 0 +#define GPTIMER_TLATCH_LTCV_MASK 0xffffffffU +#define GPTIMER_TLATCH_LTCV_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define GPTIMER_TLATCH_LTCV( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @brief This structure defines the GPTIMER TIMER register block memory map. + */ +typedef struct gptimer_timer { + /** + * @brief See @ref RTEMSDeviceGRLIBGPTIMERTimerTCNTVAL. + */ + uint32_t tcntval; + + /** + * @brief See @ref RTEMSDeviceGRLIBGPTIMERTimerTRLDVAL. + */ + uint32_t trldval; + + /** + * @brief See @ref RTEMSDeviceGRLIBGPTIMERTimerTCTRL. + */ + uint32_t tctrl; + + /** + * @brief See @ref RTEMSDeviceGRLIBGPTIMERTimerTLATCH. + */ + uint32_t tlatch; +} gptimer_timer; + +/** @} */ + +/* Generated from spec:/dev/grlib/if/gptimer */ + +/** + * @defgroup RTEMSDeviceGRLIBGPTIMER GPTIMER + * + * @ingroup RTEMSDeviceGRLIB + * + * @brief This group contains the GPTIMER interfaces. + * + * @{ + */ + +/** + * @defgroup RTEMSDeviceGRLIBGPTIMERSCALER Scaler value register (SCALER) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GPTIMER_SCALER_SCALER_SHIFT 0 +#define GPTIMER_SCALER_SCALER_MASK 0xffffU +#define GPTIMER_SCALER_SCALER_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffU ) +#define GPTIMER_SCALER_SCALER( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBGPTIMERSRELOAD \ + * Scaler reload value register (SRELOAD) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GPTIMER_SRELOAD_SRELOAD_SHIFT 0 +#define GPTIMER_SRELOAD_SRELOAD_MASK 0xffffU +#define GPTIMER_SRELOAD_SRELOAD_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffU ) +#define GPTIMER_SRELOAD_SRELOAD( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBGPTIMERCONFIG Configuration register (CONFIG) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GPTIMER_CONFIG_EV 0x2000U + +#define GPTIMER_CONFIG_ES 0x1000U + +#define GPTIMER_CONFIG_EL 0x800U + +#define GPTIMER_CONFIG_EE 0x400U + +#define GPTIMER_CONFIG_DF 0x200U + +#define GPTIMER_CONFIG_SI 0x100U + +#define GPTIMER_CONFIG_IRQ_SHIFT 3 +#define GPTIMER_CONFIG_IRQ_MASK 0xf8U +#define GPTIMER_CONFIG_IRQ_GET( _reg ) \ + ( ( ( _reg ) >> 3 ) & 0x1fU ) +#define GPTIMER_CONFIG_IRQ( _val ) ( ( _val ) << 3 ) + +#define GPTIMER_CONFIG_TIMERS_SHIFT 0 +#define GPTIMER_CONFIG_TIMERS_MASK 0x7U +#define GPTIMER_CONFIG_TIMERS_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0x7U ) +#define GPTIMER_CONFIG_TIMERS( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBGPTIMERLATCHCFG \ + * Timer latch configuration register (LATCHCFG) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GPTIMER_LATCHCFG_LATCHSEL_SHIFT 0 +#define GPTIMER_LATCHCFG_LATCHSEL_MASK 0xffffffffU +#define GPTIMER_LATCHCFG_LATCHSEL_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define GPTIMER_LATCHCFG_LATCHSEL( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @brief This structure defines the GPTIMER register block memory map. + */ +typedef struct gptimer { + /** + * @brief See @ref RTEMSDeviceGRLIBGPTIMERSCALER. + */ + uint32_t scaler; + + /** + * @brief See @ref RTEMSDeviceGRLIBGPTIMERSRELOAD. + */ + uint32_t sreload; + + /** + * @brief See @ref RTEMSDeviceGRLIBGPTIMERCONFIG. + */ + uint32_t config; + + /** + * @brief See @ref RTEMSDeviceGRLIBGPTIMERLATCHCFG. + */ + uint32_t latchcfg; + + /** + * @brief See @ref RTEMSDeviceGRLIBGPTIMERTimer. + */ + gptimer_timer timer[ 15 ]; +} gptimer; + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GRLIB_GPTIMER_REGS_H */ diff --git a/bsps/include/grlib/gr1553b-regs.h b/bsps/include/grlib/gr1553b-regs.h new file mode 100644 index 0000000000..d045acd5bd --- /dev/null +++ b/bsps/include/grlib/gr1553b-regs.h @@ -0,0 +1,1043 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSDeviceGR1553B + * + * @brief This header file defines the GR1553B register block interface. + */ + +/* + * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file is part of the RTEMS quality process and was automatically + * generated. If you find something that needs to be fixed or + * worded better please post a report or patch to an RTEMS mailing list + * or raise a bug report: + * + * https://www.rtems.org/bugs.html + * + * For information on updating and regenerating please refer to the How-To + * section in the Software Requirements Engineering chapter of the + * RTEMS Software Engineering manual. The manual is provided as a part of + * a release. For development sources please refer to the online + * documentation at: + * + * https://docs.rtems.org + */ + +/* Generated from spec:/dev/grlib/if/gr1553b-header */ + +#ifndef _GRLIB_GR1553B_REGS_H +#define _GRLIB_GR1553B_REGS_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Generated from spec:/dev/grlib/if/gr1553b */ + +/** + * @defgroup RTEMSDeviceGR1553B GR1553B + * + * @ingroup RTEMSDeviceGRLIB + * + * @brief This group contains the GR1553B interfaces. + * + * @{ + */ + +/** + * @defgroup RTEMSDeviceGR1553BIRQ GR1553B IRQ Register (IRQ) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR1553B_IRQ_BMTOF 0x20000U + +#define GR1553B_IRQ_BMD 0x10000U + +#define GR1553B_IRQ_RTTE 0x400U + +#define GR1553B_IRQ_RTD 0x200U + +#define GR1553B_IRQ_RTEV 0x100U + +#define GR1553B_IRQ_BCWK 0x4U + +#define GR1553B_IRQ_BCD 0x2U + +#define GR1553B_IRQ_BCEV 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGR1553BIRQE GR1553B IRQ Enable Register (IRQE) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR1553B_IRQE_BMTOE 0x20000U + +#define GR1553B_IRQE_BMDE 0x10000U + +#define GR1553B_IRQE_RTTEE 0x400U + +#define GR1553B_IRQE_RTDE 0x200U + +#define GR1553B_IRQE_RTEVE 0x100U + +#define GR1553B_IRQE_BCWKE 0x4U + +#define GR1553B_IRQE_BCDE 0x2U + +#define GR1553B_IRQE_BCEVE 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGR1553BHC GR1553B Hardware Configuration Register (HC) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR1553B_HC_MOD 0x80000000U + +#define GR1553B_HC_CVER 0x1000U + +#define GR1553B_HC_XKEYS 0x800U + +#define GR1553B_HC_ENDIAN_SHIFT 9 +#define GR1553B_HC_ENDIAN_MASK 0x600U +#define GR1553B_HC_ENDIAN_GET( _reg ) \ + ( ( ( _reg ) >> 9 ) & 0x3U ) +#define GR1553B_HC_ENDIAN( _val ) ( ( _val ) << 9 ) + +#define GR1553B_HC_SCLK 0x100U + +#define GR1553B_HC_CCFREQ_SHIFT 0 +#define GR1553B_HC_CCFREQ_MASK 0xffU +#define GR1553B_HC_CCFREQ_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffU ) +#define GR1553B_HC_CCFREQ( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGR1553BBCSC \ + * GR1553B BC Status and Config Register (BCSC) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR1553B_BCSC_BCSUP 0x80000000U + +#define GR1553B_BCSC_BCFEAT_SHIFT 28 +#define GR1553B_BCSC_BCFEAT_MASK 0x70000000U +#define GR1553B_BCSC_BCFEAT_GET( _reg ) \ + ( ( ( _reg ) >> 28 ) & 0x7U ) +#define GR1553B_BCSC_BCFEAT( _val ) ( ( _val ) << 28 ) + +#define GR1553B_BCSC_BCCHK 0x10000U + +#define GR1553B_BCSC_ASADL_SHIFT 11 +#define GR1553B_BCSC_ASADL_MASK 0xf800U +#define GR1553B_BCSC_ASADL_GET( _reg ) \ + ( ( ( _reg ) >> 11 ) & 0x1fU ) +#define GR1553B_BCSC_ASADL( _val ) ( ( _val ) << 11 ) + +#define GR1553B_BCSC_ASST_SHIFT 8 +#define GR1553B_BCSC_ASST_MASK 0x300U +#define GR1553B_BCSC_ASST_GET( _reg ) \ + ( ( ( _reg ) >> 8 ) & 0x3U ) +#define GR1553B_BCSC_ASST( _val ) ( ( _val ) << 8 ) + +#define GR1553B_BCSC_SCADL_SHIFT 3 +#define GR1553B_BCSC_SCADL_MASK 0xf8U +#define GR1553B_BCSC_SCADL_GET( _reg ) \ + ( ( ( _reg ) >> 3 ) & 0x1fU ) +#define GR1553B_BCSC_SCADL( _val ) ( ( _val ) << 3 ) + +#define GR1553B_BCSC_SCST_SHIFT 0 +#define GR1553B_BCSC_SCST_MASK 0x7U +#define GR1553B_BCSC_SCST_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0x7U ) +#define GR1553B_BCSC_SCST( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGR1553BBCA GR1553B BC Action Register (BCA) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR1553B_BCA_BCKEY_SHIFT 16 +#define GR1553B_BCA_BCKEY_MASK 0xffff0000U +#define GR1553B_BCA_BCKEY_GET( _reg ) \ + ( ( ( _reg ) >> 16 ) & 0xffffU ) +#define GR1553B_BCA_BCKEY( _val ) ( ( _val ) << 16 ) + +#define GR1553B_BCA_ASSTP 0x200U + +#define GR1553B_BCA_ASSRT 0x100U + +#define GR1553B_BCA_CLRT 0x10U + +#define GR1553B_BCA_SETT 0x8U + +#define GR1553B_BCA_SCSTP 0x4U + +#define GR1553B_BCA_SCSUS 0x2U + +#define GR1553B_BCA_SCSRT 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGR1553BBCTNP \ + * GR1553B BC Transfer list next pointer register (BCTNP) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR1553B_BCTNP_POINTER_SHIFT 0 +#define GR1553B_BCTNP_POINTER_MASK 0xffffffffU +#define GR1553B_BCTNP_POINTER_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define GR1553B_BCTNP_POINTER( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGR1553BBCANP \ + * GR1553B BC Asynchronous list next pointer register (BCANP) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR1553B_BCANP_POINTER_SHIFT 0 +#define GR1553B_BCANP_POINTER_MASK 0xffffffffU +#define GR1553B_BCANP_POINTER_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define GR1553B_BCANP_POINTER( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGR1553BBCT GR1553B BC Timer register (BCT) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR1553B_BCT_SCTM_SHIFT 0 +#define GR1553B_BCT_SCTM_MASK 0xffffffU +#define GR1553B_BCT_SCTM_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffU ) +#define GR1553B_BCT_SCTM( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGR1553BBCRP \ + * GR1553B BC Transfer-triggered IRQ ring position register (BCRP) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR1553B_BCRP_POSITION_SHIFT 0 +#define GR1553B_BCRP_POSITION_MASK 0xffffffffU +#define GR1553B_BCRP_POSITION_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define GR1553B_BCRP_POSITION( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGR1553BBCBS GR1553B BC per-RT Bus swap register (BCBS) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR1553B_BCBS_SWAP_SHIFT 0 +#define GR1553B_BCBS_SWAP_MASK 0xffffffffU +#define GR1553B_BCBS_SWAP_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define GR1553B_BCBS_SWAP( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGR1553BBCTCP \ + * GR1553B BC Transfer list current slot pointer (BCTCP) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR1553B_BCTCP_POINTER_SHIFT 0 +#define GR1553B_BCTCP_POINTER_MASK 0xffffffffU +#define GR1553B_BCTCP_POINTER_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define GR1553B_BCTCP_POINTER( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGR1553BBCACP \ + * GR1553B BC Asynchronous list current slot pointer (BCACP) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR1553B_BCACP_POINTER_SHIFT 0 +#define GR1553B_BCACP_POINTER_MASK 0xffffffffU +#define GR1553B_BCACP_POINTER_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define GR1553B_BCACP_POINTER( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGR1553BRTS GR1553B RT Status register (RTS) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR1553B_RTS_RTSUP 0x80000000U + +#define GR1553B_RTS_ACT 0x8U + +#define GR1553B_RTS_SHDA 0x4U + +#define GR1553B_RTS_SHDB 0x2U + +#define GR1553B_RTS_RUN 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGR1553BRTC GR1553B RT Config register (RTC) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR1553B_RTC_RTKEY_SHIFT 16 +#define GR1553B_RTC_RTKEY_MASK 0xffff0000U +#define GR1553B_RTC_RTKEY_GET( _reg ) \ + ( ( ( _reg ) >> 16 ) & 0xffffU ) +#define GR1553B_RTC_RTKEY( _val ) ( ( _val ) << 16 ) + +#define GR1553B_RTC_SYS 0x8000U + +#define GR1553B_RTC_SYDS 0x4000U + +#define GR1553B_RTC_BRS 0x2000U + +#define GR1553B_RTC_RTEIS 0x40U + +#define GR1553B_RTC_RTADDR_SHIFT 1 +#define GR1553B_RTC_RTADDR_MASK 0x3eU +#define GR1553B_RTC_RTADDR_GET( _reg ) \ + ( ( ( _reg ) >> 1 ) & 0x1fU ) +#define GR1553B_RTC_RTADDR( _val ) ( ( _val ) << 1 ) + +#define GR1553B_RTC_RTEN 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGR1553BRTBS GR1553B RT Bus status register (RTBS) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR1553B_RTBS_TFDE 0x100U + +#define GR1553B_RTBS_SREQ 0x10U + +#define GR1553B_RTBS_BUSY 0x8U + +#define GR1553B_RTBS_SSF 0x4U + +#define GR1553B_RTBS_DBCA 0x2U + +#define GR1553B_RTBS_TFLG 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGR1553BRTSW GR1553B RT Status words register (RTSW) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR1553B_RTSW_BITW_SHIFT 16 +#define GR1553B_RTSW_BITW_MASK 0xffff0000U +#define GR1553B_RTSW_BITW_GET( _reg ) \ + ( ( ( _reg ) >> 16 ) & 0xffffU ) +#define GR1553B_RTSW_BITW( _val ) ( ( _val ) << 16 ) + +#define GR1553B_RTSW_VECW_SHIFT 0 +#define GR1553B_RTSW_VECW_MASK 0xffffU +#define GR1553B_RTSW_VECW_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffU ) +#define GR1553B_RTSW_VECW( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGR1553BRTSY GR1553B RT Sync register (RTSY) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR1553B_RTSY_SYTM_SHIFT 16 +#define GR1553B_RTSY_SYTM_MASK 0xffff0000U +#define GR1553B_RTSY_SYTM_GET( _reg ) \ + ( ( ( _reg ) >> 16 ) & 0xffffU ) +#define GR1553B_RTSY_SYTM( _val ) ( ( _val ) << 16 ) + +#define GR1553B_RTSY_SYD_SHIFT 0 +#define GR1553B_RTSY_SYD_MASK 0xffffU +#define GR1553B_RTSY_SYD_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffU ) +#define GR1553B_RTSY_SYD( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGR1553BRTSTBA \ + * GR1553B RT Subaddress table base address register (RTSTBA) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR1553B_RTSTBA_SATB_SHIFT 9 +#define GR1553B_RTSTBA_SATB_MASK 0xfffffe00U +#define GR1553B_RTSTBA_SATB_GET( _reg ) \ + ( ( ( _reg ) >> 9 ) & 0x7fffffU ) +#define GR1553B_RTSTBA_SATB( _val ) ( ( _val ) << 9 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGR1553BRTMCC \ + * GR1553B RT Mode code control register (RTMCC) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR1553B_RTMCC_RRTB_SHIFT 28 +#define GR1553B_RTMCC_RRTB_MASK 0x30000000U +#define GR1553B_RTMCC_RRTB_GET( _reg ) \ + ( ( ( _reg ) >> 28 ) & 0x3U ) +#define GR1553B_RTMCC_RRTB( _val ) ( ( _val ) << 28 ) + +#define GR1553B_RTMCC_RRT_SHIFT 26 +#define GR1553B_RTMCC_RRT_MASK 0xc000000U +#define GR1553B_RTMCC_RRT_GET( _reg ) \ + ( ( ( _reg ) >> 26 ) & 0x3U ) +#define GR1553B_RTMCC_RRT( _val ) ( ( _val ) << 26 ) + +#define GR1553B_RTMCC_ITFB_SHIFT 24 +#define GR1553B_RTMCC_ITFB_MASK 0x3000000U +#define GR1553B_RTMCC_ITFB_GET( _reg ) \ + ( ( ( _reg ) >> 24 ) & 0x3U ) +#define GR1553B_RTMCC_ITFB( _val ) ( ( _val ) << 24 ) + +#define GR1553B_RTMCC_ITF_SHIFT 22 +#define GR1553B_RTMCC_ITF_MASK 0xc00000U +#define GR1553B_RTMCC_ITF_GET( _reg ) \ + ( ( ( _reg ) >> 22 ) & 0x3U ) +#define GR1553B_RTMCC_ITF( _val ) ( ( _val ) << 22 ) + +#define GR1553B_RTMCC_ISTB_SHIFT 20 +#define GR1553B_RTMCC_ISTB_MASK 0x300000U +#define GR1553B_RTMCC_ISTB_GET( _reg ) \ + ( ( ( _reg ) >> 20 ) & 0x3U ) +#define GR1553B_RTMCC_ISTB( _val ) ( ( _val ) << 20 ) + +#define GR1553B_RTMCC_IST_SHIFT 18 +#define GR1553B_RTMCC_IST_MASK 0xc0000U +#define GR1553B_RTMCC_IST_GET( _reg ) \ + ( ( ( _reg ) >> 18 ) & 0x3U ) +#define GR1553B_RTMCC_IST( _val ) ( ( _val ) << 18 ) + +#define GR1553B_RTMCC_DBC_SHIFT 16 +#define GR1553B_RTMCC_DBC_MASK 0x30000U +#define GR1553B_RTMCC_DBC_GET( _reg ) \ + ( ( ( _reg ) >> 16 ) & 0x3U ) +#define GR1553B_RTMCC_DBC( _val ) ( ( _val ) << 16 ) + +#define GR1553B_RTMCC_TBW_SHIFT 14 +#define GR1553B_RTMCC_TBW_MASK 0xc000U +#define GR1553B_RTMCC_TBW_GET( _reg ) \ + ( ( ( _reg ) >> 14 ) & 0x3U ) +#define GR1553B_RTMCC_TBW( _val ) ( ( _val ) << 14 ) + +#define GR1553B_RTMCC_TVW_SHIFT 12 +#define GR1553B_RTMCC_TVW_MASK 0x3000U +#define GR1553B_RTMCC_TVW_GET( _reg ) \ + ( ( ( _reg ) >> 12 ) & 0x3U ) +#define GR1553B_RTMCC_TVW( _val ) ( ( _val ) << 12 ) + +#define GR1553B_RTMCC_TSB_SHIFT 10 +#define GR1553B_RTMCC_TSB_MASK 0xc00U +#define GR1553B_RTMCC_TSB_GET( _reg ) \ + ( ( ( _reg ) >> 10 ) & 0x3U ) +#define GR1553B_RTMCC_TSB( _val ) ( ( _val ) << 10 ) + +#define GR1553B_RTMCC_TS_SHIFT 8 +#define GR1553B_RTMCC_TS_MASK 0x300U +#define GR1553B_RTMCC_TS_GET( _reg ) \ + ( ( ( _reg ) >> 8 ) & 0x3U ) +#define GR1553B_RTMCC_TS( _val ) ( ( _val ) << 8 ) + +#define GR1553B_RTMCC_SDB_SHIFT 6 +#define GR1553B_RTMCC_SDB_MASK 0xc0U +#define GR1553B_RTMCC_SDB_GET( _reg ) \ + ( ( ( _reg ) >> 6 ) & 0x3U ) +#define GR1553B_RTMCC_SDB( _val ) ( ( _val ) << 6 ) + +#define GR1553B_RTMCC_SD_SHIFT 4 +#define GR1553B_RTMCC_SD_MASK 0x30U +#define GR1553B_RTMCC_SD_GET( _reg ) \ + ( ( ( _reg ) >> 4 ) & 0x3U ) +#define GR1553B_RTMCC_SD( _val ) ( ( _val ) << 4 ) + +#define GR1553B_RTMCC_SB_SHIFT 2 +#define GR1553B_RTMCC_SB_MASK 0xcU +#define GR1553B_RTMCC_SB_GET( _reg ) \ + ( ( ( _reg ) >> 2 ) & 0x3U ) +#define GR1553B_RTMCC_SB( _val ) ( ( _val ) << 2 ) + +#define GR1553B_RTMCC_S_SHIFT 0 +#define GR1553B_RTMCC_S_MASK 0x3U +#define GR1553B_RTMCC_S_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0x3U ) +#define GR1553B_RTMCC_S( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGR1553BRTTTC \ + * GR1553B RT Time tag control register (RTTTC) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR1553B_RTTTC_TRES_SHIFT 16 +#define GR1553B_RTTTC_TRES_MASK 0xffff0000U +#define GR1553B_RTTTC_TRES_GET( _reg ) \ + ( ( ( _reg ) >> 16 ) & 0xffffU ) +#define GR1553B_RTTTC_TRES( _val ) ( ( _val ) << 16 ) + +#define GR1553B_RTTTC_TVAL_SHIFT 0 +#define GR1553B_RTTTC_TVAL_MASK 0xffffU +#define GR1553B_RTTTC_TVAL_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffU ) +#define GR1553B_RTTTC_TVAL( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGR1553BRTELM \ + * GR1553B RT Event log size mask register (RTELM) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR1553B_RTELM_MASK_SHIFT 0 +#define GR1553B_RTELM_MASK_MASK 0xffffffffU +#define GR1553B_RTELM_MASK_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define GR1553B_RTELM_MASK( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGR1553BRTELP \ + * GR1553B RT Event log position register (RTELP) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR1553B_RTELP_POINTER_SHIFT 0 +#define GR1553B_RTELP_POINTER_MASK 0xffffffffU +#define GR1553B_RTELP_POINTER_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define GR1553B_RTELP_POINTER( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGR1553BRTELIP \ + * GR1553B RT Event Log interrupt position register (RTELIP) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR1553B_RTELIP_POINTER_SHIFT 0 +#define GR1553B_RTELIP_POINTER_MASK 0xffffffffU +#define GR1553B_RTELIP_POINTER_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define GR1553B_RTELIP_POINTER( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGR1553BBMS GR1553B BM Status register (BMS) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR1553B_BMS_BMSUP 0x80000000U + +#define GR1553B_BMS_KEYEN 0x40000000U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGR1553BBMC GR1553B BM Control register (BMC) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR1553B_BMC_BMKEY_SHIFT 16 +#define GR1553B_BMC_BMKEY_MASK 0xffff0000U +#define GR1553B_BMC_BMKEY_GET( _reg ) \ + ( ( ( _reg ) >> 16 ) & 0xffffU ) +#define GR1553B_BMC_BMKEY( _val ) ( ( _val ) << 16 ) + +#define GR1553B_BMC_WRSTP 0x20U + +#define GR1553B_BMC_EXST 0x10U + +#define GR1553B_BMC_IMCL 0x8U + +#define GR1553B_BMC_UDWL 0x4U + +#define GR1553B_BMC_MANL 0x2U + +#define GR1553B_BMC_BMEN 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGR1553BBMRTAF \ + * GR1553B BM RT Address filter register (BMRTAF) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR1553B_BMRTAF_MASK_SHIFT 0 +#define GR1553B_BMRTAF_MASK_MASK 0xffffffffU +#define GR1553B_BMRTAF_MASK_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define GR1553B_BMRTAF_MASK( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGR1553BBMRTSF \ + * GR1553B BM RT Subaddress filter register (BMRTSF) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR1553B_BMRTSF_MASK_SHIFT 0 +#define GR1553B_BMRTSF_MASK_MASK 0xffffffffU +#define GR1553B_BMRTSF_MASK_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define GR1553B_BMRTSF_MASK( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGR1553BBMRTMC \ + * GR1553B BM RT Mode code filter register (BMRTMC) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR1553B_BMRTMC_STSB 0x40000U + +#define GR1553B_BMRTMC_STS 0x20000U + +#define GR1553B_BMRTMC_TLC 0x10000U + +#define GR1553B_BMRTMC_TSW 0x8000U + +#define GR1553B_BMRTMC_RRTB 0x4000U + +#define GR1553B_BMRTMC_RRT 0x2000U + +#define GR1553B_BMRTMC_ITFB 0x1000U + +#define GR1553B_BMRTMC_ITF 0x800U + +#define GR1553B_BMRTMC_ISTB 0x400U + +#define GR1553B_BMRTMC_IST 0x200U + +#define GR1553B_BMRTMC_DBC 0x100U + +#define GR1553B_BMRTMC_TBW 0x80U + +#define GR1553B_BMRTMC_TVW 0x40U + +#define GR1553B_BMRTMC_TSB 0x20U + +#define GR1553B_BMRTMC_TS 0x10U + +#define GR1553B_BMRTMC_SDB 0x8U + +#define GR1553B_BMRTMC_SD 0x4U + +#define GR1553B_BMRTMC_SB 0x2U + +#define GR1553B_BMRTMC_S 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGR1553BBMLBS GR1553B BM Log buffer start (BMLBS) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR1553B_BMLBS_START_SHIFT 0 +#define GR1553B_BMLBS_START_MASK 0xffffffffU +#define GR1553B_BMLBS_START_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define GR1553B_BMLBS_START( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGR1553BBMLBE GR1553B BM Log buffer end (BMLBE) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR1553B_BMLBE_END_SHIFT 0 +#define GR1553B_BMLBE_END_MASK 0xffffffffU +#define GR1553B_BMLBE_END_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define GR1553B_BMLBE_END( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGR1553BBMLBP GR1553B BM Log buffer position (BMLBP) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR1553B_BMLBP_POSITION_SHIFT 0 +#define GR1553B_BMLBP_POSITION_MASK 0xffffffffU +#define GR1553B_BMLBP_POSITION_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define GR1553B_BMLBP_POSITION( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGR1553BBMTTC \ + * GR1553B BM Time tag control register (BMTTC) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR1553B_BMTTC_TRES_SHIFT 24 +#define GR1553B_BMTTC_TRES_MASK 0xff000000U +#define GR1553B_BMTTC_TRES_GET( _reg ) \ + ( ( ( _reg ) >> 24 ) & 0xffU ) +#define GR1553B_BMTTC_TRES( _val ) ( ( _val ) << 24 ) + +#define GR1553B_BMTTC_TVAL_SHIFT 0 +#define GR1553B_BMTTC_TVAL_MASK 0xffffffU +#define GR1553B_BMTTC_TVAL_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffU ) +#define GR1553B_BMTTC_TVAL( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @brief This structure defines the GR1553B register block memory map. + */ +typedef struct gr1553b { + /** + * @brief See @ref RTEMSDeviceGR1553BIRQ. + */ + uint32_t irq; + + /** + * @brief See @ref RTEMSDeviceGR1553BIRQE. + */ + uint32_t irqe; + + uint32_t reserved_8_10[ 2 ]; + + /** + * @brief See @ref RTEMSDeviceGR1553BHC. + */ + uint32_t hc; + + uint32_t reserved_14_40[ 11 ]; + + /** + * @brief See @ref RTEMSDeviceGR1553BBCSC. + */ + uint32_t bcsc; + + /** + * @brief See @ref RTEMSDeviceGR1553BBCA. + */ + uint32_t bca; + + /** + * @brief See @ref RTEMSDeviceGR1553BBCTNP. + */ + uint32_t bctnp; + + /** + * @brief See @ref RTEMSDeviceGR1553BBCANP. + */ + uint32_t bcanp; + + /** + * @brief See @ref RTEMSDeviceGR1553BBCT. + */ + uint32_t bct; + + uint32_t reserved_54_58; + + /** + * @brief See @ref RTEMSDeviceGR1553BBCRP. + */ + uint32_t bcrp; + + /** + * @brief See @ref RTEMSDeviceGR1553BBCBS. + */ + uint32_t bcbs; + + uint32_t reserved_60_68[ 2 ]; + + /** + * @brief See @ref RTEMSDeviceGR1553BBCTCP. + */ + uint32_t bctcp; + + /** + * @brief See @ref RTEMSDeviceGR1553BBCACP. + */ + uint32_t bcacp; + + uint32_t reserved_70_80[ 4 ]; + + /** + * @brief See @ref RTEMSDeviceGR1553BRTS. + */ + uint32_t rts; + + /** + * @brief See @ref RTEMSDeviceGR1553BRTC. + */ + uint32_t rtc; + + /** + * @brief See @ref RTEMSDeviceGR1553BRTBS. + */ + uint32_t rtbs; + + /** + * @brief See @ref RTEMSDeviceGR1553BRTSW. + */ + uint32_t rtsw; + + /** + * @brief See @ref RTEMSDeviceGR1553BRTSY. + */ + uint32_t rtsy; + + /** + * @brief See @ref RTEMSDeviceGR1553BRTSTBA. + */ + uint32_t rtstba; + + /** + * @brief See @ref RTEMSDeviceGR1553BRTMCC. + */ + uint32_t rtmcc; + + uint32_t reserved_9c_a4[ 2 ]; + + /** + * @brief See @ref RTEMSDeviceGR1553BRTTTC. + */ + uint32_t rtttc; + + uint32_t reserved_a8_ac; + + /** + * @brief See @ref RTEMSDeviceGR1553BRTELM. + */ + uint32_t rtelm; + + /** + * @brief See @ref RTEMSDeviceGR1553BRTELP. + */ + uint32_t rtelp; + + /** + * @brief See @ref RTEMSDeviceGR1553BRTELIP. + */ + uint32_t rtelip; + + uint32_t reserved_b8_c0[ 2 ]; + + /** + * @brief See @ref RTEMSDeviceGR1553BBMS. + */ + uint32_t bms; + + /** + * @brief See @ref RTEMSDeviceGR1553BBMC. + */ + uint32_t bmc; + + /** + * @brief See @ref RTEMSDeviceGR1553BBMRTAF. + */ + uint32_t bmrtaf; + + /** + * @brief See @ref RTEMSDeviceGR1553BBMRTSF. + */ + uint32_t bmrtsf; + + /** + * @brief See @ref RTEMSDeviceGR1553BBMRTMC. + */ + uint32_t bmrtmc; + + /** + * @brief See @ref RTEMSDeviceGR1553BBMLBS. + */ + uint32_t bmlbs; + + /** + * @brief See @ref RTEMSDeviceGR1553BBMLBE. + */ + uint32_t bmlbe; + + /** + * @brief See @ref RTEMSDeviceGR1553BBMLBP. + */ + uint32_t bmlbp; + + /** + * @brief See @ref RTEMSDeviceGR1553BBMTTC. + */ + uint32_t bmttc; +} gr1553b; + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GRLIB_GR1553B_REGS_H */ diff --git a/bsps/include/grlib/gr740thsens-regs.h b/bsps/include/grlib/gr740thsens-regs.h new file mode 100644 index 0000000000..172ea1fd02 --- /dev/null +++ b/bsps/include/grlib/gr740thsens-regs.h @@ -0,0 +1,184 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSDeviceGR740THSENS + * + * @brief This header file defines the GR740THSENS register block interface. + */ + +/* + * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file is part of the RTEMS quality process and was automatically + * generated. If you find something that needs to be fixed or + * worded better please post a report or patch to an RTEMS mailing list + * or raise a bug report: + * + * https://www.rtems.org/bugs.html + * + * For information on updating and regenerating please refer to the How-To + * section in the Software Requirements Engineering chapter of the + * RTEMS Software Engineering manual. The manual is provided as a part of + * a release. For development sources please refer to the online + * documentation at: + * + * https://docs.rtems.org + */ + +/* Generated from spec:/dev/grlib/if/gr740thsens-header */ + +#ifndef _GRLIB_GR740THSENS_REGS_H +#define _GRLIB_GR740THSENS_REGS_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Generated from spec:/dev/grlib/if/gr740thsens */ + +/** + * @defgroup RTEMSDeviceGR740THSENS GR740THSENS + * + * @ingroup RTEMSDeviceGRLIB + * + * @brief This group contains the GR740THSENS interfaces. + * + * @{ + */ + +/** + * @defgroup RTEMSDeviceGR740THSENSCTRL Control register (CTRL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR740THSENS_CTRL_DIV_SHIFT 16 +#define GR740THSENS_CTRL_DIV_MASK 0x3ff0000U +#define GR740THSENS_CTRL_DIV_GET( _reg ) \ + ( ( ( _reg ) >> 16 ) & 0x3ffU ) +#define GR740THSENS_CTRL_DIV( _val ) ( ( _val ) << 16 ) + +#define GR740THSENS_CTRL_ALEN 0x100U + +#define GR740THSENS_CTRL_PDN 0x80U + +#define GR740THSENS_CTRL_DCORRECT_SHIFT 2 +#define GR740THSENS_CTRL_DCORRECT_MASK 0x7cU +#define GR740THSENS_CTRL_DCORRECT_GET( _reg ) \ + ( ( ( _reg ) >> 2 ) & 0x1fU ) +#define GR740THSENS_CTRL_DCORRECT( _val ) ( ( _val ) << 2 ) + +#define GR740THSENS_CTRL_SRSTN 0x2U + +#define GR740THSENS_CTRL_CLKEN 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGR740THSENSSTATUS Status register (STATUS) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR740THSENS_STATUS_MAX_SHIFT 24 +#define GR740THSENS_STATUS_MAX_MASK 0x7f000000U +#define GR740THSENS_STATUS_MAX_GET( _reg ) \ + ( ( ( _reg ) >> 24 ) & 0x7fU ) +#define GR740THSENS_STATUS_MAX( _val ) ( ( _val ) << 24 ) + +#define GR740THSENS_STATUS_MIN_SHIFT 16 +#define GR740THSENS_STATUS_MIN_MASK 0x7f0000U +#define GR740THSENS_STATUS_MIN_GET( _reg ) \ + ( ( ( _reg ) >> 16 ) & 0x7fU ) +#define GR740THSENS_STATUS_MIN( _val ) ( ( _val ) << 16 ) + +#define GR740THSENS_STATUS_SCLK 0x8000U + +#define GR740THSENS_STATUS_WE 0x400U + +#define GR740THSENS_STATUS_UPD 0x200U + +#define GR740THSENS_STATUS_ALACT 0x100U + +#define GR740THSENS_STATUS_DATA_SHIFT 0 +#define GR740THSENS_STATUS_DATA_MASK 0x7fU +#define GR740THSENS_STATUS_DATA_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0x7fU ) +#define GR740THSENS_STATUS_DATA( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGR740THSENSTHRES Threshold register (THRES) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR740THSENS_THRES_THRES_SHIFT 0 +#define GR740THSENS_THRES_THRES_MASK 0x7fU +#define GR740THSENS_THRES_THRES_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0x7fU ) +#define GR740THSENS_THRES_THRES( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @brief This structure defines the GR740THSENS register block memory map. + */ +typedef struct gr740thsens { + /** + * @brief See @ref RTEMSDeviceGR740THSENSCTRL. + */ + uint32_t ctrl; + + /** + * @brief See @ref RTEMSDeviceGR740THSENSSTATUS. + */ + uint32_t status; + + /** + * @brief See @ref RTEMSDeviceGR740THSENSTHRES. + */ + uint32_t thres; +} gr740thsens; + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GRLIB_GR740THSENS_REGS_H */ diff --git a/bsps/include/grlib/grcan-regs.h b/bsps/include/grlib/grcan-regs.h new file mode 100644 index 0000000000..85879c60c9 --- /dev/null +++ b/bsps/include/grlib/grcan-regs.h @@ -0,0 +1,561 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSDeviceGRCAN + * + * @brief This header file defines the GRCAN register block interface. + */ + +/* + * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file is part of the RTEMS quality process and was automatically + * generated. If you find something that needs to be fixed or + * worded better please post a report or patch to an RTEMS mailing list + * or raise a bug report: + * + * https://www.rtems.org/bugs.html + * + * For information on updating and regenerating please refer to the How-To + * section in the Software Requirements Engineering chapter of the + * RTEMS Software Engineering manual. The manual is provided as a part of + * a release. For development sources please refer to the online + * documentation at: + * + * https://docs.rtems.org + */ + +/* Generated from spec:/dev/grlib/if/grcan-header */ + +#ifndef _GRLIB_GRCAN_REGS_H +#define _GRLIB_GRCAN_REGS_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Generated from spec:/dev/grlib/if/grcan */ + +/** + * @defgroup RTEMSDeviceGRCAN GRCAN + * + * @ingroup RTEMSDeviceGRLIB + * + * @brief This group contains the GRCAN interfaces. + * + * @{ + */ + +/** + * @defgroup RTEMSDeviceGRCANCanCONF Configuration Register (CanCONF) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRCAN_CANCONF_SCALER_SHIFT 24 +#define GRCAN_CANCONF_SCALER_MASK 0xff000000U +#define GRCAN_CANCONF_SCALER_GET( _reg ) \ + ( ( ( _reg ) >> 24 ) & 0xffU ) +#define GRCAN_CANCONF_SCALER( _val ) ( ( _val ) << 24 ) + +#define GRCAN_CANCONF_PS1_SHIFT 20 +#define GRCAN_CANCONF_PS1_MASK 0xf00000U +#define GRCAN_CANCONF_PS1_GET( _reg ) \ + ( ( ( _reg ) >> 20 ) & 0xfU ) +#define GRCAN_CANCONF_PS1( _val ) ( ( _val ) << 20 ) + +#define GRCAN_CANCONF_PS2_SHIFT 16 +#define GRCAN_CANCONF_PS2_MASK 0xf0000U +#define GRCAN_CANCONF_PS2_GET( _reg ) \ + ( ( ( _reg ) >> 16 ) & 0xfU ) +#define GRCAN_CANCONF_PS2( _val ) ( ( _val ) << 16 ) + +#define GRCAN_CANCONF_RSJ_SHIFT 12 +#define GRCAN_CANCONF_RSJ_MASK 0x7000U +#define GRCAN_CANCONF_RSJ_GET( _reg ) \ + ( ( ( _reg ) >> 12 ) & 0x7U ) +#define GRCAN_CANCONF_RSJ( _val ) ( ( _val ) << 12 ) + +#define GRCAN_CANCONF_BPR_SHIFT 8 +#define GRCAN_CANCONF_BPR_MASK 0x300U +#define GRCAN_CANCONF_BPR_GET( _reg ) \ + ( ( ( _reg ) >> 8 ) & 0x3U ) +#define GRCAN_CANCONF_BPR( _val ) ( ( _val ) << 8 ) + +#define GRCAN_CANCONF_SAM 0x20U + +#define GRCAN_CANCONF_SILNT 0x10U + +#define GRCAN_CANCONF_SELECT 0x8U + +#define GRCAN_CANCONF_ENABLE1 0x4U + +#define GRCAN_CANCONF_ENABLE0 0x2U + +#define GRCAN_CANCONF_ABORT 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRCANCanSTAT Status Register (CanSTAT) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRCAN_CANSTAT_TXCHANNELS_SHIFT 28 +#define GRCAN_CANSTAT_TXCHANNELS_MASK 0xf0000000U +#define GRCAN_CANSTAT_TXCHANNELS_GET( _reg ) \ + ( ( ( _reg ) >> 28 ) & 0xfU ) +#define GRCAN_CANSTAT_TXCHANNELS( _val ) ( ( _val ) << 28 ) + +#define GRCAN_CANSTAT_RXCHANNELS_SHIFT 24 +#define GRCAN_CANSTAT_RXCHANNELS_MASK 0xf000000U +#define GRCAN_CANSTAT_RXCHANNELS_GET( _reg ) \ + ( ( ( _reg ) >> 24 ) & 0xfU ) +#define GRCAN_CANSTAT_RXCHANNELS( _val ) ( ( _val ) << 24 ) + +#define GRCAN_CANSTAT_TXERRCNT_SHIFT 16 +#define GRCAN_CANSTAT_TXERRCNT_MASK 0xff0000U +#define GRCAN_CANSTAT_TXERRCNT_GET( _reg ) \ + ( ( ( _reg ) >> 16 ) & 0xffU ) +#define GRCAN_CANSTAT_TXERRCNT( _val ) ( ( _val ) << 16 ) + +#define GRCAN_CANSTAT_RXERRCNT_SHIFT 8 +#define GRCAN_CANSTAT_RXERRCNT_MASK 0xff00U +#define GRCAN_CANSTAT_RXERRCNT_GET( _reg ) \ + ( ( ( _reg ) >> 8 ) & 0xffU ) +#define GRCAN_CANSTAT_RXERRCNT( _val ) ( ( _val ) << 8 ) + +#define GRCAN_CANSTAT_ACTIVE 0x10U + +#define GRCAN_CANSTAT_AHBERR 0x8U + +#define GRCAN_CANSTAT_OR 0x4U + +#define GRCAN_CANSTAT_OFF 0x2U + +#define GRCAN_CANSTAT_PASS 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRCANCanCTRL Control Register (CanCTRL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRCAN_CANCTRL_RESET 0x2U + +#define GRCAN_CANCTRL_ENABLE 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRCANCanMASK SYNC Mask Filter Register (CanMASK) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRCAN_CANMASK_MASK_SHIFT 0 +#define GRCAN_CANMASK_MASK_MASK 0x1fffffffU +#define GRCAN_CANMASK_MASK_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0x1fffffffU ) +#define GRCAN_CANMASK_MASK( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRCANCanCODE SYNC Code Filter Register (CanCODE) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRCAN_CANCODE_SYNC_SHIFT 0 +#define GRCAN_CANCODE_SYNC_MASK 0x1fffffffU +#define GRCAN_CANCODE_SYNC_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0x1fffffffU ) +#define GRCAN_CANCODE_SYNC( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRCANCanTxCTRL \ + * Transmit Channel Control Register (CanTxCTRL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRCAN_CANTXCTRL_SINGLE 0x4U + +#define GRCAN_CANTXCTRL_ONGOING 0x2U + +#define GRCAN_CANTXCTRL_ENABLE 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRCANCanTxADDR \ + * Transmit Channel Address Register (CanTxADDR) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRCAN_CANTXADDR_ADDR_SHIFT 10 +#define GRCAN_CANTXADDR_ADDR_MASK 0xfffffc00U +#define GRCAN_CANTXADDR_ADDR_GET( _reg ) \ + ( ( ( _reg ) >> 10 ) & 0x3fffffU ) +#define GRCAN_CANTXADDR_ADDR( _val ) ( ( _val ) << 10 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRCANCanTxSIZE \ + * Transmit Channel Size Register (CanTxSIZE) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRCAN_CANTXSIZE_SIZE_SHIFT 6 +#define GRCAN_CANTXSIZE_SIZE_MASK 0x1fffc0U +#define GRCAN_CANTXSIZE_SIZE_GET( _reg ) \ + ( ( ( _reg ) >> 6 ) & 0x7fffU ) +#define GRCAN_CANTXSIZE_SIZE( _val ) ( ( _val ) << 6 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRCANCanTxWR Transmit Channel Write Register (CanTxWR) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRCAN_CANTXWR_WRITE_SHIFT 4 +#define GRCAN_CANTXWR_WRITE_MASK 0xffff0U +#define GRCAN_CANTXWR_WRITE_GET( _reg ) \ + ( ( ( _reg ) >> 4 ) & 0xffffU ) +#define GRCAN_CANTXWR_WRITE( _val ) ( ( _val ) << 4 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRCANCanTxRD Transmit Channel Read Register (CanTxRD) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRCAN_CANTXRD_READ_SHIFT 4 +#define GRCAN_CANTXRD_READ_MASK 0xffff0U +#define GRCAN_CANTXRD_READ_GET( _reg ) \ + ( ( ( _reg ) >> 4 ) & 0xffffU ) +#define GRCAN_CANTXRD_READ( _val ) ( ( _val ) << 4 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRCANCanTxRD Transmit Channel Read Register (CanTxRD) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRCAN_CANTXRD_IRQ_SHIFT 4 +#define GRCAN_CANTXRD_IRQ_MASK 0xffff0U +#define GRCAN_CANTXRD_IRQ_GET( _reg ) \ + ( ( ( _reg ) >> 4 ) & 0xffffU ) +#define GRCAN_CANTXRD_IRQ( _val ) ( ( _val ) << 4 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRCANCanRxCTRL \ + * Receive Channel Control Register (CanRxCTRL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRCAN_CANRXCTRL_ONGOING 0x2U + +#define GRCAN_CANRXCTRL_ENABLE 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRCANCanRxADDR \ + * Receive Channel Address Register (CanRxADDR) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRCAN_CANRXADDR_ADDR_SHIFT 10 +#define GRCAN_CANRXADDR_ADDR_MASK 0xfffffc00U +#define GRCAN_CANRXADDR_ADDR_GET( _reg ) \ + ( ( ( _reg ) >> 10 ) & 0x3fffffU ) +#define GRCAN_CANRXADDR_ADDR( _val ) ( ( _val ) << 10 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRCANCanRxSIZE \ + * Receive Channel Size Register (CanRxSIZE) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRCAN_CANRXSIZE_SIZE_SHIFT 6 +#define GRCAN_CANRXSIZE_SIZE_MASK 0x1fffc0U +#define GRCAN_CANRXSIZE_SIZE_GET( _reg ) \ + ( ( ( _reg ) >> 6 ) & 0x7fffU ) +#define GRCAN_CANRXSIZE_SIZE( _val ) ( ( _val ) << 6 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRCANCanRxWR Receive Channel Write Register (CanRxWR) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRCAN_CANRXWR_WRITE_SHIFT 4 +#define GRCAN_CANRXWR_WRITE_MASK 0xffff0U +#define GRCAN_CANRXWR_WRITE_GET( _reg ) \ + ( ( ( _reg ) >> 4 ) & 0xffffU ) +#define GRCAN_CANRXWR_WRITE( _val ) ( ( _val ) << 4 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRCANCanRxRD Receive Channel Read Register (CanRxRD) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRCAN_CANRXRD_READ_SHIFT 4 +#define GRCAN_CANRXRD_READ_MASK 0xffff0U +#define GRCAN_CANRXRD_READ_GET( _reg ) \ + ( ( ( _reg ) >> 4 ) & 0xffffU ) +#define GRCAN_CANRXRD_READ( _val ) ( ( _val ) << 4 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRCANCanRxIRQ \ + * Receive Channel Interrupt Register (CanRxIRQ) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRCAN_CANRXIRQ_IRQ_SHIFT 4 +#define GRCAN_CANRXIRQ_IRQ_MASK 0xffff0U +#define GRCAN_CANRXIRQ_IRQ_GET( _reg ) \ + ( ( ( _reg ) >> 4 ) & 0xffffU ) +#define GRCAN_CANRXIRQ_IRQ( _val ) ( ( _val ) << 4 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRCANCanRxMASK \ + * Receive Channel Mask Register (CanRxMASK) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRCAN_CANRXMASK_AM_SHIFT 0 +#define GRCAN_CANRXMASK_AM_MASK 0x1fffffffU +#define GRCAN_CANRXMASK_AM_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0x1fffffffU ) +#define GRCAN_CANRXMASK_AM( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRCANCanRxCODE \ + * Receive Channel Code Register (CanRxCODE) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRCAN_CANRXCODE_AC_SHIFT 0 +#define GRCAN_CANRXCODE_AC_MASK 0x1fffffffU +#define GRCAN_CANRXCODE_AC_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0x1fffffffU ) +#define GRCAN_CANRXCODE_AC( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @brief This structure defines the GRCAN register block memory map. + */ +typedef struct grcan { + /** + * @brief See @ref RTEMSDeviceGRCANCanCONF. + */ + uint32_t canconf; + + /** + * @brief See @ref RTEMSDeviceGRCANCanSTAT. + */ + uint32_t canstat; + + /** + * @brief See @ref RTEMSDeviceGRCANCanCTRL. + */ + uint32_t canctrl; + + uint32_t reserved_c_18[ 3 ]; + + /** + * @brief See @ref RTEMSDeviceGRCANCanMASK. + */ + uint32_t canmask; + + /** + * @brief See @ref RTEMSDeviceGRCANCanCODE. + */ + uint32_t cancode; + + uint32_t reserved_20_200[ 120 ]; + + /** + * @brief See @ref RTEMSDeviceGRCANCanTxCTRL. + */ + uint32_t cantxctrl; + + /** + * @brief See @ref RTEMSDeviceGRCANCanTxADDR. + */ + uint32_t cantxaddr; + + /** + * @brief See @ref RTEMSDeviceGRCANCanTxSIZE. + */ + uint32_t cantxsize; + + /** + * @brief See @ref RTEMSDeviceGRCANCanTxWR. + */ + uint32_t cantxwr; + + /** + * @brief See @ref RTEMSDeviceGRCANCanTxRD. + */ + uint32_t cantxrd_0; + + /** + * @brief See @ref RTEMSDeviceGRCANCanTxRD. + */ + uint32_t cantxrd_1; + + uint32_t reserved_218_300[ 58 ]; + + /** + * @brief See @ref RTEMSDeviceGRCANCanRxCTRL. + */ + uint32_t canrxctrl; + + /** + * @brief See @ref RTEMSDeviceGRCANCanRxADDR. + */ + uint32_t canrxaddr; + + /** + * @brief See @ref RTEMSDeviceGRCANCanRxSIZE. + */ + uint32_t canrxsize; + + /** + * @brief See @ref RTEMSDeviceGRCANCanRxWR. + */ + uint32_t canrxwr; + + /** + * @brief See @ref RTEMSDeviceGRCANCanRxRD. + */ + uint32_t canrxrd; + + /** + * @brief See @ref RTEMSDeviceGRCANCanRxIRQ. + */ + uint32_t canrxirq; + + /** + * @brief See @ref RTEMSDeviceGRCANCanRxMASK. + */ + uint32_t canrxmask; + + /** + * @brief See @ref RTEMSDeviceGRCANCanRxCODE. + */ + uint32_t canrxcode; +} grcan; + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GRLIB_GRCAN_REGS_H */ diff --git a/bsps/include/grlib/grclkgate-regs.h b/bsps/include/grlib/grclkgate-regs.h new file mode 100644 index 0000000000..cd66d6854e --- /dev/null +++ b/bsps/include/grlib/grclkgate-regs.h @@ -0,0 +1,177 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSDeviceGRCLKGATE + * + * @brief This header file defines the GRCLKGATE register block interface. + */ + +/* + * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file is part of the RTEMS quality process and was automatically + * generated. If you find something that needs to be fixed or + * worded better please post a report or patch to an RTEMS mailing list + * or raise a bug report: + * + * https://www.rtems.org/bugs.html + * + * For information on updating and regenerating please refer to the How-To + * section in the Software Requirements Engineering chapter of the + * RTEMS Software Engineering manual. The manual is provided as a part of + * a release. For development sources please refer to the online + * documentation at: + * + * https://docs.rtems.org + */ + +/* Generated from spec:/dev/grlib/if/grclkgate-header */ + +#ifndef _GRLIB_GRCLKGATE_REGS_H +#define _GRLIB_GRCLKGATE_REGS_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Generated from spec:/dev/grlib/if/grclkgate */ + +/** + * @defgroup RTEMSDeviceGRCLKGATE GRCLKGATE + * + * @ingroup RTEMSDeviceGRLIB + * + * @brief This group contains the GRCLKGATE interfaces. + * + * @{ + */ + +/** + * @defgroup RTEMSDeviceGRCLKGATEUNLOCK Unlock register (UNLOCK) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRCLKGATE_UNLOCK_UNLOCK_SHIFT 0 +#define GRCLKGATE_UNLOCK_UNLOCK_MASK 0x7ffU +#define GRCLKGATE_UNLOCK_UNLOCK_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0x7ffU ) +#define GRCLKGATE_UNLOCK_UNLOCK( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRCLKGATECLKEN Clock enable register (CLKEN) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRCLKGATE_CLKEN_ENABLE_SHIFT 0 +#define GRCLKGATE_CLKEN_ENABLE_MASK 0x7ffU +#define GRCLKGATE_CLKEN_ENABLE_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0x7ffU ) +#define GRCLKGATE_CLKEN_ENABLE( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRCLKGATERESET Reset register (RESET) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRCLKGATE_RESET_RESET_SHIFT 0 +#define GRCLKGATE_RESET_RESET_MASK 0x7ffU +#define GRCLKGATE_RESET_RESET_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0x7ffU ) +#define GRCLKGATE_RESET_RESET( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRCLKGATEOVERRIDE CPU/FPU override register (OVERRIDE) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRCLKGATE_OVERRIDE_FOVERRIDE_SHIFT 16 +#define GRCLKGATE_OVERRIDE_FOVERRIDE_MASK 0xf0000U +#define GRCLKGATE_OVERRIDE_FOVERRIDE_GET( _reg ) \ + ( ( ( _reg ) >> 16 ) & 0xfU ) +#define GRCLKGATE_OVERRIDE_FOVERRIDE( _val ) ( ( _val ) << 16 ) + +#define GRCLKGATE_OVERRIDE_OVERRIDE_SHIFT 0 +#define GRCLKGATE_OVERRIDE_OVERRIDE_MASK 0xfU +#define GRCLKGATE_OVERRIDE_OVERRIDE_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xfU ) +#define GRCLKGATE_OVERRIDE_OVERRIDE( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @brief This structure defines the GRCLKGATE register block memory map. + */ +typedef struct grclkgate { + /** + * @brief See @ref RTEMSDeviceGRCLKGATEUNLOCK. + */ + uint32_t unlock; + + /** + * @brief See @ref RTEMSDeviceGRCLKGATECLKEN. + */ + uint32_t clken; + + /** + * @brief See @ref RTEMSDeviceGRCLKGATERESET. + */ + uint32_t reset; + + /** + * @brief See @ref RTEMSDeviceGRCLKGATEOVERRIDE. + */ + uint32_t override; +} grclkgate; + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GRLIB_GRCLKGATE_REGS_H */ diff --git a/bsps/include/grlib/grethgbit-regs.h b/bsps/include/grlib/grethgbit-regs.h new file mode 100644 index 0000000000..1959742bc5 --- /dev/null +++ b/bsps/include/grlib/grethgbit-regs.h @@ -0,0 +1,362 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSDeviceGRETHGBIT + * + * @brief This header file defines the GRETH_GBIT register block interface. + */ + +/* + * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file is part of the RTEMS quality process and was automatically + * generated. If you find something that needs to be fixed or + * worded better please post a report or patch to an RTEMS mailing list + * or raise a bug report: + * + * https://www.rtems.org/bugs.html + * + * For information on updating and regenerating please refer to the How-To + * section in the Software Requirements Engineering chapter of the + * RTEMS Software Engineering manual. The manual is provided as a part of + * a release. For development sources please refer to the online + * documentation at: + * + * https://docs.rtems.org + */ + +/* Generated from spec:/dev/grlib/if/grethgbit-header */ + +#ifndef _GRLIB_GRETHGBIT_REGS_H +#define _GRLIB_GRETHGBIT_REGS_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Generated from spec:/dev/grlib/if/grethgbit */ + +/** + * @defgroup RTEMSDeviceGRETHGBIT GRETH_GBIT + * + * @ingroup RTEMSDeviceGRLIB + * + * @brief This group contains the GRETH_GBIT interfaces. + * + * @{ + */ + +/** + * @defgroup RTEMSDeviceGRETHGBITCR control register (CR) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRETHGBIT_CR_EA 0x80000000U + +#define GRETHGBIT_CR_BS_SHIFT 28 +#define GRETHGBIT_CR_BS_MASK 0x70000000U +#define GRETHGBIT_CR_BS_GET( _reg ) \ + ( ( ( _reg ) >> 28 ) & 0x7U ) +#define GRETHGBIT_CR_BS( _val ) ( ( _val ) << 28 ) + +#define GRETHGBIT_CR_GA 0x8000000U + +#define GRETHGBIT_CR_MA 0x4000000U + +#define GRETHGBIT_CR_MC 0x2000000U + +#define GRETHGBIT_CR_ED 0x4000U + +#define GRETHGBIT_CR_RD 0x2000U + +#define GRETHGBIT_CR_DD 0x1000U + +#define GRETHGBIT_CR_ME 0x800U + +#define GRETHGBIT_CR_PI 0x400U + +#define GRETHGBIT_CR_BM 0x200U + +#define GRETHGBIT_CR_GB 0x100U + +#define GRETHGBIT_CR_SP 0x80U + +#define GRETHGBIT_CR_RS 0x40U + +#define GRETHGBIT_CR_PM 0x20U + +#define GRETHGBIT_CR_FD 0x10U + +#define GRETHGBIT_CR_RI 0x8U + +#define GRETHGBIT_CR_TI 0x4U + +#define GRETHGBIT_CR_RE 0x2U + +#define GRETHGBIT_CR_TE 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRETHGBITSR status register. (SR) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRETHGBIT_SR_PS 0x100U + +#define GRETHGBIT_SR_IA 0x80U + +#define GRETHGBIT_SR_TS 0x40U + +#define GRETHGBIT_SR_TA 0x20U + +#define GRETHGBIT_SR_RA 0x10U + +#define GRETHGBIT_SR_TI 0x8U + +#define GRETHGBIT_SR_RI 0x4U + +#define GRETHGBIT_SR_TE 0x2U + +#define GRETHGBIT_SR_RE 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRETHGBITMACMSB MAC address MSB. (MACMSB) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRETHGBIT_MACMSB_MSB_SHIFT 0 +#define GRETHGBIT_MACMSB_MSB_MASK 0xffffU +#define GRETHGBIT_MACMSB_MSB_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffU ) +#define GRETHGBIT_MACMSB_MSB( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRETHGBITMACLSB MAC address LSB. (MACLSB) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRETHGBIT_MACLSB_LSB_SHIFT 0 +#define GRETHGBIT_MACLSB_LSB_MASK 0xffffffffU +#define GRETHGBIT_MACLSB_LSB_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define GRETHGBIT_MACLSB_LSB( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRETHGBITMDIO MDIO control/status register. (MDIO) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRETHGBIT_MDIO_DATA_SHIFT 16 +#define GRETHGBIT_MDIO_DATA_MASK 0xffff0000U +#define GRETHGBIT_MDIO_DATA_GET( _reg ) \ + ( ( ( _reg ) >> 16 ) & 0xffffU ) +#define GRETHGBIT_MDIO_DATA( _val ) ( ( _val ) << 16 ) + +#define GRETHGBIT_MDIO_PHYADDR_SHIFT 11 +#define GRETHGBIT_MDIO_PHYADDR_MASK 0xf800U +#define GRETHGBIT_MDIO_PHYADDR_GET( _reg ) \ + ( ( ( _reg ) >> 11 ) & 0x1fU ) +#define GRETHGBIT_MDIO_PHYADDR( _val ) ( ( _val ) << 11 ) + +#define GRETHGBIT_MDIO_REGADDR_SHIFT 6 +#define GRETHGBIT_MDIO_REGADDR_MASK 0x7c0U +#define GRETHGBIT_MDIO_REGADDR_GET( _reg ) \ + ( ( ( _reg ) >> 6 ) & 0x1fU ) +#define GRETHGBIT_MDIO_REGADDR( _val ) ( ( _val ) << 6 ) + +#define GRETHGBIT_MDIO_BU 0x8U + +#define GRETHGBIT_MDIO_LF 0x4U + +#define GRETHGBIT_MDIO_RD 0x2U + +#define GRETHGBIT_MDIO_WR 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRETHGBITTDTBA \ + * transmitter descriptor table base address register. (TDTBA) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRETHGBIT_TDTBA_BASEADDR_SHIFT 10 +#define GRETHGBIT_TDTBA_BASEADDR_MASK 0xfffffc00U +#define GRETHGBIT_TDTBA_BASEADDR_GET( _reg ) \ + ( ( ( _reg ) >> 10 ) & 0x3fffffU ) +#define GRETHGBIT_TDTBA_BASEADDR( _val ) ( ( _val ) << 10 ) + +#define GRETHGBIT_TDTBA_DESCPNT_SHIFT 3 +#define GRETHGBIT_TDTBA_DESCPNT_MASK 0x3f8U +#define GRETHGBIT_TDTBA_DESCPNT_GET( _reg ) \ + ( ( ( _reg ) >> 3 ) & 0x7fU ) +#define GRETHGBIT_TDTBA_DESCPNT( _val ) ( ( _val ) << 3 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRETHGBITRDTBA \ + * receiver descriptor table base address register. (RDTBA) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRETHGBIT_RDTBA_BASEADDR_SHIFT 10 +#define GRETHGBIT_RDTBA_BASEADDR_MASK 0xfffffc00U +#define GRETHGBIT_RDTBA_BASEADDR_GET( _reg ) \ + ( ( ( _reg ) >> 10 ) & 0x3fffffU ) +#define GRETHGBIT_RDTBA_BASEADDR( _val ) ( ( _val ) << 10 ) + +#define GRETHGBIT_RDTBA_DESCPNT_SHIFT 3 +#define GRETHGBIT_RDTBA_DESCPNT_MASK 0x3f8U +#define GRETHGBIT_RDTBA_DESCPNT_GET( _reg ) \ + ( ( ( _reg ) >> 3 ) & 0x7fU ) +#define GRETHGBIT_RDTBA_DESCPNT( _val ) ( ( _val ) << 3 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRETHGBITEDCLMACMSB EDCL MAC address MSB. (EDCLMACMSB) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRETHGBIT_EDCLMACMSB_MSB_SHIFT 0 +#define GRETHGBIT_EDCLMACMSB_MSB_MASK 0xffffU +#define GRETHGBIT_EDCLMACMSB_MSB_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffU ) +#define GRETHGBIT_EDCLMACMSB_MSB( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRETHGBITEDCLMACLSB EDCL MAC address LSB. (EDCLMACLSB) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRETHGBIT_EDCLMACLSB_LSB_SHIFT 0 +#define GRETHGBIT_EDCLMACLSB_LSB_MASK 0xffffffffU +#define GRETHGBIT_EDCLMACLSB_LSB_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define GRETHGBIT_EDCLMACLSB_LSB( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @brief This structure defines the GRETH_GBIT register block memory map. + */ +typedef struct grethgbit { + /** + * @brief See @ref RTEMSDeviceGRETHGBITCR. + */ + uint32_t cr; + + /** + * @brief See @ref RTEMSDeviceGRETHGBITSR. + */ + uint32_t sr; + + /** + * @brief See @ref RTEMSDeviceGRETHGBITMACMSB. + */ + uint32_t macmsb; + + /** + * @brief See @ref RTEMSDeviceGRETHGBITMACLSB. + */ + uint32_t maclsb; + + /** + * @brief See @ref RTEMSDeviceGRETHGBITMDIO. + */ + uint32_t mdio; + + /** + * @brief See @ref RTEMSDeviceGRETHGBITTDTBA. + */ + uint32_t tdtba; + + /** + * @brief See @ref RTEMSDeviceGRETHGBITRDTBA. + */ + uint32_t rdtba; + + uint32_t reserved_1c_28[ 3 ]; + + /** + * @brief See @ref RTEMSDeviceGRETHGBITEDCLMACMSB. + */ + uint32_t edclmacmsb; + + /** + * @brief See @ref RTEMSDeviceGRETHGBITEDCLMACLSB. + */ + uint32_t edclmaclsb; +} grethgbit; + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GRLIB_GRETHGBIT_REGS_H */ diff --git a/bsps/include/grlib/grgpio-regs.h b/bsps/include/grlib/grgpio-regs.h new file mode 100644 index 0000000000..7afe2ed67f --- /dev/null +++ b/bsps/include/grlib/grgpio-regs.h @@ -0,0 +1,486 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSDeviceGRGPIO + * + * @brief This header file defines the GRGPIO register block interface. + */ + +/* + * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file is part of the RTEMS quality process and was automatically + * generated. If you find something that needs to be fixed or + * worded better please post a report or patch to an RTEMS mailing list + * or raise a bug report: + * + * https://www.rtems.org/bugs.html + * + * For information on updating and regenerating please refer to the How-To + * section in the Software Requirements Engineering chapter of the + * RTEMS Software Engineering manual. The manual is provided as a part of + * a release. For development sources please refer to the online + * documentation at: + * + * https://docs.rtems.org + */ + +/* Generated from spec:/dev/grlib/if/grgpio-header */ + +#ifndef _GRLIB_GRGPIO_REGS_H +#define _GRLIB_GRGPIO_REGS_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Generated from spec:/dev/grlib/if/grgpio */ + +/** + * @defgroup RTEMSDeviceGRGPIO GRGPIO + * + * @ingroup RTEMSDeviceGRLIB + * + * @brief This group contains the GRGPIO interfaces. + * + * @{ + */ + +/** + * @defgroup RTEMSDeviceGRGPIODATA I/O port data register (DATA) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRGPIO_DATA_DATA_SHIFT 0 +#define GRGPIO_DATA_DATA_MASK 0xffffffffU +#define GRGPIO_DATA_DATA_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define GRGPIO_DATA_DATA( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRGPIOOUTPUT I/O port output register (OUTPUT) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRGPIO_OUTPUT_DATA_SHIFT 0 +#define GRGPIO_OUTPUT_DATA_MASK 0xffffffffU +#define GRGPIO_OUTPUT_DATA_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define GRGPIO_OUTPUT_DATA( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRGPIODIRECTION I/O port direction register (DIRECTION) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRGPIO_DIRECTION_DIR_SHIFT 0 +#define GRGPIO_DIRECTION_DIR_MASK 0xffffffffU +#define GRGPIO_DIRECTION_DIR_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define GRGPIO_DIRECTION_DIR( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRGPIOIMASK Interrupt mask register (IMASK) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRGPIO_IMASK_MASK_SHIFT 0 +#define GRGPIO_IMASK_MASK_MASK 0xffffffffU +#define GRGPIO_IMASK_MASK_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define GRGPIO_IMASK_MASK( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRGPIOIPOL Interrupt polarity register (IPOL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRGPIO_IPOL_POL_SHIFT 0 +#define GRGPIO_IPOL_POL_MASK 0xffffffffU +#define GRGPIO_IPOL_POL_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define GRGPIO_IPOL_POL( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRGPIOIEDGE Interrupt edge register (IEDGE) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRGPIO_IEDGE_EDGE_SHIFT 0 +#define GRGPIO_IEDGE_EDGE_MASK 0xffffffffU +#define GRGPIO_IEDGE_EDGE_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define GRGPIO_IEDGE_EDGE( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRGPIOBYPASS Bypass register (BYPASS) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRGPIO_BYPASS_BYPASS_SHIFT 0 +#define GRGPIO_BYPASS_BYPASS_MASK 0xffffffffU +#define GRGPIO_BYPASS_BYPASS_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define GRGPIO_BYPASS_BYPASS( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRGPIOCAP Capability register (CAP) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRGPIO_CAP_PU 0x40000U + +#define GRGPIO_CAP_IER 0x20000U + +#define GRGPIO_CAP_IFL 0x10000U + +#define GRGPIO_CAP_IRQGEN_SHIFT 8 +#define GRGPIO_CAP_IRQGEN_MASK 0x1f00U +#define GRGPIO_CAP_IRQGEN_GET( _reg ) \ + ( ( ( _reg ) >> 8 ) & 0x1fU ) +#define GRGPIO_CAP_IRQGEN( _val ) ( ( _val ) << 8 ) + +#define GRGPIO_CAP_NLINES_SHIFT 0 +#define GRGPIO_CAP_NLINES_MASK 0x1fU +#define GRGPIO_CAP_NLINES_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0x1fU ) +#define GRGPIO_CAP_NLINES( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRGPIOIRQMAPR \ + * Interrupt map register n, where n = 0 .. 3 (IRQMAPR) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRGPIO_IRQMAPR_IRQMAP_I_SHIFT 24 +#define GRGPIO_IRQMAPR_IRQMAP_I_MASK 0x7f000000U +#define GRGPIO_IRQMAPR_IRQMAP_I_GET( _reg ) \ + ( ( ( _reg ) >> 24 ) & 0x7fU ) +#define GRGPIO_IRQMAPR_IRQMAP_I( _val ) ( ( _val ) << 24 ) + +#define GRGPIO_IRQMAPR_IRQMAP_I_1_SHIFT 16 +#define GRGPIO_IRQMAPR_IRQMAP_I_1_MASK 0x1f0000U +#define GRGPIO_IRQMAPR_IRQMAP_I_1_GET( _reg ) \ + ( ( ( _reg ) >> 16 ) & 0x1fU ) +#define GRGPIO_IRQMAPR_IRQMAP_I_1( _val ) ( ( _val ) << 16 ) + +#define GRGPIO_IRQMAPR_IRQMAP_I_2_SHIFT 8 +#define GRGPIO_IRQMAPR_IRQMAP_I_2_MASK 0x1f00U +#define GRGPIO_IRQMAPR_IRQMAP_I_2_GET( _reg ) \ + ( ( ( _reg ) >> 8 ) & 0x1fU ) +#define GRGPIO_IRQMAPR_IRQMAP_I_2( _val ) ( ( _val ) << 8 ) + +#define GRGPIO_IRQMAPR_IRQMAP_I_3 0x10U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRGPIOIAVAIL Interrupt available register (IAVAIL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRGPIO_IAVAIL_IMASK_SHIFT 0 +#define GRGPIO_IAVAIL_IMASK_MASK 0xffffffffU +#define GRGPIO_IAVAIL_IMASK_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define GRGPIO_IAVAIL_IMASK( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRGPIOIFLAG Interrupt flag register (IFLAG) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRGPIO_IFLAG_IFLAG_SHIFT 0 +#define GRGPIO_IFLAG_IFLAG_MASK 0xffffffffU +#define GRGPIO_IFLAG_IFLAG_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define GRGPIO_IFLAG_IFLAG( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRGPIOIPEN Interrupt enable register (IPEN) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRGPIO_IPEN_IPEN_SHIFT 0 +#define GRGPIO_IPEN_IPEN_MASK 0xffffffffU +#define GRGPIO_IPEN_IPEN_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define GRGPIO_IPEN_IPEN( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRGPIOPULSE Pulse register (PULSE) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRGPIO_PULSE_PULSE_SHIFT 0 +#define GRGPIO_PULSE_PULSE_MASK 0xffffffffU +#define GRGPIO_PULSE_PULSE_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define GRGPIO_PULSE_PULSE( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRGPIOLOR Logical-OR registers (LOR) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRGPIO_LOR_DATA_SHIFT 0 +#define GRGPIO_LOR_DATA_MASK 0xffffffffU +#define GRGPIO_LOR_DATA_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define GRGPIO_LOR_DATA( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRGPIOLAND Logical-AND registers (LAND) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRGPIO_LAND_DATA_SHIFT 0 +#define GRGPIO_LAND_DATA_MASK 0xffffffffU +#define GRGPIO_LAND_DATA_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define GRGPIO_LAND_DATA( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRGPIOLXOR Logical-XOR registers (LXOR) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRGPIO_LXOR_DATA_SHIFT 0 +#define GRGPIO_LXOR_DATA_MASK 0xffffffffU +#define GRGPIO_LXOR_DATA_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define GRGPIO_LXOR_DATA( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @brief This structure defines the GRGPIO register block memory map. + */ +typedef struct grgpio { + /** + * @brief See @ref RTEMSDeviceGRGPIODATA. + */ + uint32_t data; + + /** + * @brief See @ref RTEMSDeviceGRGPIOOUTPUT. + */ + uint32_t output; + + /** + * @brief See @ref RTEMSDeviceGRGPIODIRECTION. + */ + uint32_t direction; + + /** + * @brief See @ref RTEMSDeviceGRGPIOIMASK. + */ + uint32_t imask; + + /** + * @brief See @ref RTEMSDeviceGRGPIOIPOL. + */ + uint32_t ipol; + + /** + * @brief See @ref RTEMSDeviceGRGPIOIEDGE. + */ + uint32_t iedge; + + /** + * @brief See @ref RTEMSDeviceGRGPIOBYPASS. + */ + uint32_t bypass; + + /** + * @brief See @ref RTEMSDeviceGRGPIOCAP. + */ + uint32_t cap; + + /** + * @brief See @ref RTEMSDeviceGRGPIOIRQMAPR. + */ + uint32_t irqmapr[ 8 ]; + + /** + * @brief See @ref RTEMSDeviceGRGPIOIAVAIL. + */ + uint32_t iavail; + + /** + * @brief See @ref RTEMSDeviceGRGPIOIFLAG. + */ + uint32_t iflag; + + /** + * @brief See @ref RTEMSDeviceGRGPIOIPEN. + */ + uint32_t ipen; + + /** + * @brief See @ref RTEMSDeviceGRGPIOPULSE. + */ + uint32_t pulse; + + uint32_t reserved_50_54; + + /** + * @brief See @ref RTEMSDeviceGRGPIOLOR. + */ + uint32_t lor_output; + + /** + * @brief See @ref RTEMSDeviceGRGPIOLOR. + */ + uint32_t lor_direction; + + /** + * @brief See @ref RTEMSDeviceGRGPIOLOR. + */ + uint32_t lor_imask; + + uint32_t reserved_60_64; + + /** + * @brief See @ref RTEMSDeviceGRGPIOLAND. + */ + uint32_t land_output; + + /** + * @brief See @ref RTEMSDeviceGRGPIOLAND. + */ + uint32_t land_direction; + + /** + * @brief See @ref RTEMSDeviceGRGPIOLAND. + */ + uint32_t land_imask; + + uint32_t reserved_70_74; + + /** + * @brief See @ref RTEMSDeviceGRGPIOLXOR. + */ + uint32_t lxor_output; + + /** + * @brief See @ref RTEMSDeviceGRGPIOLXOR. + */ + uint32_t lxor_direction; + + /** + * @brief See @ref RTEMSDeviceGRGPIOLXOR. + */ + uint32_t lxor_imask; +} grgpio; + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GRLIB_GRGPIO_REGS_H */ diff --git a/bsps/include/grlib/grgprbank-regs.h b/bsps/include/grlib/grgprbank-regs.h new file mode 100644 index 0000000000..cd579f54a6 --- /dev/null +++ b/bsps/include/grlib/grgprbank-regs.h @@ -0,0 +1,439 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSDeviceGRGPRBANK + * + * @brief This header file defines the GRGPRBANK register block interface. + */ + +/* + * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file is part of the RTEMS quality process and was automatically + * generated. If you find something that needs to be fixed or + * worded better please post a report or patch to an RTEMS mailing list + * or raise a bug report: + * + * https://www.rtems.org/bugs.html + * + * For information on updating and regenerating please refer to the How-To + * section in the Software Requirements Engineering chapter of the + * RTEMS Software Engineering manual. The manual is provided as a part of + * a release. For development sources please refer to the online + * documentation at: + * + * https://docs.rtems.org + */ + +/* Generated from spec:/dev/grlib/if/grgprbank-header */ + +#ifndef _GRLIB_GRGPRBANK_REGS_H +#define _GRLIB_GRGPRBANK_REGS_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Generated from spec:/dev/grlib/if/grgprbank */ + +/** + * @defgroup RTEMSDeviceGRGPRBANK GPRBANK + * + * @ingroup RTEMSDeviceGRLIB + * + * @brief This group contains the GPRBANK interfaces. + * + * @{ + */ + +/** + * @defgroup RTEMSDeviceGRGPRBANKFTMFUNC \ + * FTMCTRL function enable register (FTMFUNC) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRGPRBANK_FTMFUNC_FTMEN_SHIFT 0 +#define GRGPRBANK_FTMFUNC_FTMEN_MASK 0x3fffffU +#define GRGPRBANK_FTMFUNC_FTMEN_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0x3fffffU ) +#define GRGPRBANK_FTMFUNC_FTMEN( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRGPRBANKALTFUNC \ + * Alternative function enable register (ALTFUNC) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRGPRBANK_ALTFUNC_ALTEN_SHIFT 0 +#define GRGPRBANK_ALTFUNC_ALTEN_MASK 0x3fffffU +#define GRGPRBANK_ALTFUNC_ALTEN_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0x3fffffU ) +#define GRGPRBANK_ALTFUNC_ALTEN( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRGPRBANKLVDSMCLK \ + * LVDS and memory clock pad enable register (LVDSMCLK) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRGPRBANK_LVDSMCLK_SMEM 0x20000U + +#define GRGPRBANK_LVDSMCLK_DMEM 0x10000U + +#define GRGPRBANK_LVDSMCLK_SPWOE_SHIFT 0 +#define GRGPRBANK_LVDSMCLK_SPWOE_MASK 0xffU +#define GRGPRBANK_LVDSMCLK_SPWOE_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffU ) +#define GRGPRBANK_LVDSMCLK_SPWOE( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRGPRBANKPLLNEWCFG \ + * PLL new configuration register (PLLNEWCFG) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRGPRBANK_PLLNEWCFG_SWTAG_SHIFT 27 +#define GRGPRBANK_PLLNEWCFG_SWTAG_MASK 0x18000000U +#define GRGPRBANK_PLLNEWCFG_SWTAG_GET( _reg ) \ + ( ( ( _reg ) >> 27 ) & 0x3U ) +#define GRGPRBANK_PLLNEWCFG_SWTAG( _val ) ( ( _val ) << 27 ) + +#define GRGPRBANK_PLLNEWCFG_SPWPLLCFG_SHIFT 18 +#define GRGPRBANK_PLLNEWCFG_SPWPLLCFG_MASK 0x7fc0000U +#define GRGPRBANK_PLLNEWCFG_SPWPLLCFG_GET( _reg ) \ + ( ( ( _reg ) >> 18 ) & 0x1ffU ) +#define GRGPRBANK_PLLNEWCFG_SPWPLLCFG( _val ) ( ( _val ) << 18 ) + +#define GRGPRBANK_PLLNEWCFG_MEMPLLCFG_SHIFT 9 +#define GRGPRBANK_PLLNEWCFG_MEMPLLCFG_MASK 0x3fe00U +#define GRGPRBANK_PLLNEWCFG_MEMPLLCFG_GET( _reg ) \ + ( ( ( _reg ) >> 9 ) & 0x1ffU ) +#define GRGPRBANK_PLLNEWCFG_MEMPLLCFG( _val ) ( ( _val ) << 9 ) + +#define GRGPRBANK_PLLNEWCFG_SYSPLLCFG_SHIFT 0 +#define GRGPRBANK_PLLNEWCFG_SYSPLLCFG_MASK 0x1ffU +#define GRGPRBANK_PLLNEWCFG_SYSPLLCFG_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0x1ffU ) +#define GRGPRBANK_PLLNEWCFG_SYSPLLCFG( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRGPRBANKPLLRECFG \ + * PLL reconfigure command register (PLLRECFG) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRGPRBANK_PLLRECFG_RECONF_SHIFT 0 +#define GRGPRBANK_PLLRECFG_RECONF_MASK 0x7U +#define GRGPRBANK_PLLRECFG_RECONF_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0x7U ) +#define GRGPRBANK_PLLRECFG_RECONF( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRGPRBANKPLLCURCFG \ + * PLL current configuration register (PLLCURCFG) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRGPRBANK_PLLCURCFG_SWTAG_SHIFT 27 +#define GRGPRBANK_PLLCURCFG_SWTAG_MASK 0x18000000U +#define GRGPRBANK_PLLCURCFG_SWTAG_GET( _reg ) \ + ( ( ( _reg ) >> 27 ) & 0x3U ) +#define GRGPRBANK_PLLCURCFG_SWTAG( _val ) ( ( _val ) << 27 ) + +#define GRGPRBANK_PLLCURCFG_SPWPLLCFG_SHIFT 18 +#define GRGPRBANK_PLLCURCFG_SPWPLLCFG_MASK 0x7fc0000U +#define GRGPRBANK_PLLCURCFG_SPWPLLCFG_GET( _reg ) \ + ( ( ( _reg ) >> 18 ) & 0x1ffU ) +#define GRGPRBANK_PLLCURCFG_SPWPLLCFG( _val ) ( ( _val ) << 18 ) + +#define GRGPRBANK_PLLCURCFG_MEMPLLCFG_SHIFT 9 +#define GRGPRBANK_PLLCURCFG_MEMPLLCFG_MASK 0x3fe00U +#define GRGPRBANK_PLLCURCFG_MEMPLLCFG_GET( _reg ) \ + ( ( ( _reg ) >> 9 ) & 0x1ffU ) +#define GRGPRBANK_PLLCURCFG_MEMPLLCFG( _val ) ( ( _val ) << 9 ) + +#define GRGPRBANK_PLLCURCFG_SYSPLLCFG_SHIFT 0 +#define GRGPRBANK_PLLCURCFG_SYSPLLCFG_MASK 0x1ffU +#define GRGPRBANK_PLLCURCFG_SYSPLLCFG_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0x1ffU ) +#define GRGPRBANK_PLLCURCFG_SYSPLLCFG( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRGPRBANKDRVSTR1 \ + * Drive strength configuration register 1 (DRVSTR1) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRGPRBANK_DRVSTR1_S9_SHIFT 18 +#define GRGPRBANK_DRVSTR1_S9_MASK 0xc0000U +#define GRGPRBANK_DRVSTR1_S9_GET( _reg ) \ + ( ( ( _reg ) >> 18 ) & 0x3U ) +#define GRGPRBANK_DRVSTR1_S9( _val ) ( ( _val ) << 18 ) + +#define GRGPRBANK_DRVSTR1_S8_SHIFT 16 +#define GRGPRBANK_DRVSTR1_S8_MASK 0x30000U +#define GRGPRBANK_DRVSTR1_S8_GET( _reg ) \ + ( ( ( _reg ) >> 16 ) & 0x3U ) +#define GRGPRBANK_DRVSTR1_S8( _val ) ( ( _val ) << 16 ) + +#define GRGPRBANK_DRVSTR1_S7_SHIFT 14 +#define GRGPRBANK_DRVSTR1_S7_MASK 0xc000U +#define GRGPRBANK_DRVSTR1_S7_GET( _reg ) \ + ( ( ( _reg ) >> 14 ) & 0x3U ) +#define GRGPRBANK_DRVSTR1_S7( _val ) ( ( _val ) << 14 ) + +#define GRGPRBANK_DRVSTR1_S6_SHIFT 12 +#define GRGPRBANK_DRVSTR1_S6_MASK 0x3000U +#define GRGPRBANK_DRVSTR1_S6_GET( _reg ) \ + ( ( ( _reg ) >> 12 ) & 0x3U ) +#define GRGPRBANK_DRVSTR1_S6( _val ) ( ( _val ) << 12 ) + +#define GRGPRBANK_DRVSTR1_S5_SHIFT 10 +#define GRGPRBANK_DRVSTR1_S5_MASK 0xc00U +#define GRGPRBANK_DRVSTR1_S5_GET( _reg ) \ + ( ( ( _reg ) >> 10 ) & 0x3U ) +#define GRGPRBANK_DRVSTR1_S5( _val ) ( ( _val ) << 10 ) + +#define GRGPRBANK_DRVSTR1_S4_SHIFT 8 +#define GRGPRBANK_DRVSTR1_S4_MASK 0x300U +#define GRGPRBANK_DRVSTR1_S4_GET( _reg ) \ + ( ( ( _reg ) >> 8 ) & 0x3U ) +#define GRGPRBANK_DRVSTR1_S4( _val ) ( ( _val ) << 8 ) + +#define GRGPRBANK_DRVSTR1_S3_SHIFT 6 +#define GRGPRBANK_DRVSTR1_S3_MASK 0xc0U +#define GRGPRBANK_DRVSTR1_S3_GET( _reg ) \ + ( ( ( _reg ) >> 6 ) & 0x3U ) +#define GRGPRBANK_DRVSTR1_S3( _val ) ( ( _val ) << 6 ) + +#define GRGPRBANK_DRVSTR1_S2_SHIFT 4 +#define GRGPRBANK_DRVSTR1_S2_MASK 0x30U +#define GRGPRBANK_DRVSTR1_S2_GET( _reg ) \ + ( ( ( _reg ) >> 4 ) & 0x3U ) +#define GRGPRBANK_DRVSTR1_S2( _val ) ( ( _val ) << 4 ) + +#define GRGPRBANK_DRVSTR1_S1_SHIFT 2 +#define GRGPRBANK_DRVSTR1_S1_MASK 0xcU +#define GRGPRBANK_DRVSTR1_S1_GET( _reg ) \ + ( ( ( _reg ) >> 2 ) & 0x3U ) +#define GRGPRBANK_DRVSTR1_S1( _val ) ( ( _val ) << 2 ) + +#define GRGPRBANK_DRVSTR1_S0_SHIFT 0 +#define GRGPRBANK_DRVSTR1_S0_MASK 0x3U +#define GRGPRBANK_DRVSTR1_S0_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0x3U ) +#define GRGPRBANK_DRVSTR1_S0( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRGPRBANKDRVSTR2 \ + * Drive strength configuration register 2 (DRVSTR2) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRGPRBANK_DRVSTR2_S19_SHIFT 18 +#define GRGPRBANK_DRVSTR2_S19_MASK 0xc0000U +#define GRGPRBANK_DRVSTR2_S19_GET( _reg ) \ + ( ( ( _reg ) >> 18 ) & 0x3U ) +#define GRGPRBANK_DRVSTR2_S19( _val ) ( ( _val ) << 18 ) + +#define GRGPRBANK_DRVSTR2_S18_SHIFT 16 +#define GRGPRBANK_DRVSTR2_S18_MASK 0x30000U +#define GRGPRBANK_DRVSTR2_S18_GET( _reg ) \ + ( ( ( _reg ) >> 16 ) & 0x3U ) +#define GRGPRBANK_DRVSTR2_S18( _val ) ( ( _val ) << 16 ) + +#define GRGPRBANK_DRVSTR2_S17_SHIFT 14 +#define GRGPRBANK_DRVSTR2_S17_MASK 0xc000U +#define GRGPRBANK_DRVSTR2_S17_GET( _reg ) \ + ( ( ( _reg ) >> 14 ) & 0x3U ) +#define GRGPRBANK_DRVSTR2_S17( _val ) ( ( _val ) << 14 ) + +#define GRGPRBANK_DRVSTR2_S16_SHIFT 12 +#define GRGPRBANK_DRVSTR2_S16_MASK 0x3000U +#define GRGPRBANK_DRVSTR2_S16_GET( _reg ) \ + ( ( ( _reg ) >> 12 ) & 0x3U ) +#define GRGPRBANK_DRVSTR2_S16( _val ) ( ( _val ) << 12 ) + +#define GRGPRBANK_DRVSTR2_S15_SHIFT 10 +#define GRGPRBANK_DRVSTR2_S15_MASK 0xc00U +#define GRGPRBANK_DRVSTR2_S15_GET( _reg ) \ + ( ( ( _reg ) >> 10 ) & 0x3U ) +#define GRGPRBANK_DRVSTR2_S15( _val ) ( ( _val ) << 10 ) + +#define GRGPRBANK_DRVSTR2_S14_SHIFT 8 +#define GRGPRBANK_DRVSTR2_S14_MASK 0x300U +#define GRGPRBANK_DRVSTR2_S14_GET( _reg ) \ + ( ( ( _reg ) >> 8 ) & 0x3U ) +#define GRGPRBANK_DRVSTR2_S14( _val ) ( ( _val ) << 8 ) + +#define GRGPRBANK_DRVSTR2_S13_SHIFT 6 +#define GRGPRBANK_DRVSTR2_S13_MASK 0xc0U +#define GRGPRBANK_DRVSTR2_S13_GET( _reg ) \ + ( ( ( _reg ) >> 6 ) & 0x3U ) +#define GRGPRBANK_DRVSTR2_S13( _val ) ( ( _val ) << 6 ) + +#define GRGPRBANK_DRVSTR2_S12_SHIFT 4 +#define GRGPRBANK_DRVSTR2_S12_MASK 0x30U +#define GRGPRBANK_DRVSTR2_S12_GET( _reg ) \ + ( ( ( _reg ) >> 4 ) & 0x3U ) +#define GRGPRBANK_DRVSTR2_S12( _val ) ( ( _val ) << 4 ) + +#define GRGPRBANK_DRVSTR2_S11_SHIFT 2 +#define GRGPRBANK_DRVSTR2_S11_MASK 0xcU +#define GRGPRBANK_DRVSTR2_S11_GET( _reg ) \ + ( ( ( _reg ) >> 2 ) & 0x3U ) +#define GRGPRBANK_DRVSTR2_S11( _val ) ( ( _val ) << 2 ) + +#define GRGPRBANK_DRVSTR2_S10_SHIFT 0 +#define GRGPRBANK_DRVSTR2_S10_MASK 0x3U +#define GRGPRBANK_DRVSTR2_S10_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0x3U ) +#define GRGPRBANK_DRVSTR2_S10( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRGPRBANKLOCKDOWN \ + * Configuration lockdown register (LOCKDOWN) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRGPRBANK_LOCKDOWN_PERMANENT_SHIFT 16 +#define GRGPRBANK_LOCKDOWN_PERMANENT_MASK 0xff0000U +#define GRGPRBANK_LOCKDOWN_PERMANENT_GET( _reg ) \ + ( ( ( _reg ) >> 16 ) & 0xffU ) +#define GRGPRBANK_LOCKDOWN_PERMANENT( _val ) ( ( _val ) << 16 ) + +#define GRGPRBANK_LOCKDOWN_REVOCABLE_SHIFT 0 +#define GRGPRBANK_LOCKDOWN_REVOCABLE_MASK 0xffU +#define GRGPRBANK_LOCKDOWN_REVOCABLE_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffU ) +#define GRGPRBANK_LOCKDOWN_REVOCABLE( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @brief This structure defines the GPRBANK register block memory map. + */ +typedef struct grgprbank { + /** + * @brief See @ref RTEMSDeviceGRGPRBANKFTMFUNC. + */ + uint32_t ftmfunc; + + /** + * @brief See @ref RTEMSDeviceGRGPRBANKALTFUNC. + */ + uint32_t altfunc; + + /** + * @brief See @ref RTEMSDeviceGRGPRBANKLVDSMCLK. + */ + uint32_t lvdsmclk; + + /** + * @brief See @ref RTEMSDeviceGRGPRBANKPLLNEWCFG. + */ + uint32_t pllnewcfg; + + /** + * @brief See @ref RTEMSDeviceGRGPRBANKPLLRECFG. + */ + uint32_t pllrecfg; + + /** + * @brief See @ref RTEMSDeviceGRGPRBANKPLLCURCFG. + */ + uint32_t pllcurcfg; + + /** + * @brief See @ref RTEMSDeviceGRGPRBANKDRVSTR1. + */ + uint32_t drvstr1; + + /** + * @brief See @ref RTEMSDeviceGRGPRBANKDRVSTR2. + */ + uint32_t drvstr2; + + /** + * @brief See @ref RTEMSDeviceGRGPRBANKLOCKDOWN. + */ + uint32_t lockdown; +} grgprbank; + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GRLIB_GRGPRBANK_REGS_H */ diff --git a/bsps/include/grlib/grgpreg-regs.h b/bsps/include/grlib/grgpreg-regs.h new file mode 100644 index 0000000000..52a21559bd --- /dev/null +++ b/bsps/include/grlib/grgpreg-regs.h @@ -0,0 +1,128 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSDeviceGRGPREG + * + * @brief This header file defines the GRGPREG register block interface. + */ + +/* + * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file is part of the RTEMS quality process and was automatically + * generated. If you find something that needs to be fixed or + * worded better please post a report or patch to an RTEMS mailing list + * or raise a bug report: + * + * https://www.rtems.org/bugs.html + * + * For information on updating and regenerating please refer to the How-To + * section in the Software Requirements Engineering chapter of the + * RTEMS Software Engineering manual. The manual is provided as a part of + * a release. For development sources please refer to the online + * documentation at: + * + * https://docs.rtems.org + */ + +/* Generated from spec:/dev/grlib/if/grgpreg-header */ + +#ifndef _GRLIB_GRGPREG_REGS_H +#define _GRLIB_GRGPREG_REGS_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Generated from spec:/dev/grlib/if/grgpreg */ + +/** + * @defgroup RTEMSDeviceGRGPREG GRGPREG + * + * @ingroup RTEMSDeviceGRLIB + * + * @brief This group contains the GRGPREG interfaces. + * + * @{ + */ + +/** + * @defgroup RTEMSDeviceGRGPREGBOOTSTRAP Bootstrap register (BOOTSTRAP) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRGPREG_BOOTSTRAP_B10 0x2000000U + +#define GRGPREG_BOOTSTRAP_B9 0x1000000U + +#define GRGPREG_BOOTSTRAP_B8 0x800000U + +#define GRGPREG_BOOTSTRAP_B7 0x400000U + +#define GRGPREG_BOOTSTRAP_B6 0x200000U + +#define GRGPREG_BOOTSTRAP_B5 0x100000U + +#define GRGPREG_BOOTSTRAP_B4 0x80000U + +#define GRGPREG_BOOTSTRAP_B3 0x40000U + +#define GRGPREG_BOOTSTRAP_B2 0x20000U + +#define GRGPREG_BOOTSTRAP_B1 0x10000U + +#define GRGPREG_BOOTSTRAP_GPIO_SHIFT 0 +#define GRGPREG_BOOTSTRAP_GPIO_MASK 0xffffU +#define GRGPREG_BOOTSTRAP_GPIO_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffU ) +#define GRGPREG_BOOTSTRAP_GPIO( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @brief This structure defines the GRGPREG register block memory map. + */ +typedef struct grgpreg { + /** + * @brief See @ref RTEMSDeviceGRGPREGBOOTSTRAP. + */ + uint32_t bootstrap; +} grgpreg; + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GRLIB_GRGPREG_REGS_H */ diff --git a/bsps/include/grlib/griommu-regs.h b/bsps/include/grlib/griommu-regs.h new file mode 100644 index 0000000000..b7f7334d96 --- /dev/null +++ b/bsps/include/grlib/griommu-regs.h @@ -0,0 +1,654 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSDeviceGRIOMMU + * + * @brief This header file defines the GRIOMMU register block interface. + */ + +/* + * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file is part of the RTEMS quality process and was automatically + * generated. If you find something that needs to be fixed or + * worded better please post a report or patch to an RTEMS mailing list + * or raise a bug report: + * + * https://www.rtems.org/bugs.html + * + * For information on updating and regenerating please refer to the How-To + * section in the Software Requirements Engineering chapter of the + * RTEMS Software Engineering manual. The manual is provided as a part of + * a release. For development sources please refer to the online + * documentation at: + * + * https://docs.rtems.org + */ + +/* Generated from spec:/dev/grlib/if/griommu-header */ + +#ifndef _GRLIB_GRIOMMU_REGS_H +#define _GRLIB_GRIOMMU_REGS_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Generated from spec:/dev/grlib/if/griommu */ + +/** + * @defgroup RTEMSDeviceGRIOMMU GRIOMMU + * + * @ingroup RTEMSDeviceGRLIB + * + * @brief This group contains the GRIOMMU interfaces. + * + * @{ + */ + +/** + * @defgroup RTEMSDeviceGRIOMMUCAP0 Capability register 0 (CAP0) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRIOMMU_CAP0_A 0x80000000U + +#define GRIOMMU_CAP0_AC 0x40000000U + +#define GRIOMMU_CAP0_CA 0x20000000U + +#define GRIOMMU_CAP0_CP 0x10000000U + +#define GRIOMMU_CAP0_NARB_SHIFT 20 +#define GRIOMMU_CAP0_NARB_MASK 0xf00000U +#define GRIOMMU_CAP0_NARB_GET( _reg ) \ + ( ( ( _reg ) >> 20 ) & 0xfU ) +#define GRIOMMU_CAP0_NARB( _val ) ( ( _val ) << 20 ) + +#define GRIOMMU_CAP0_CS 0x80000U + +#define GRIOMMU_CAP0_FT_SHIFT 17 +#define GRIOMMU_CAP0_FT_MASK 0x60000U +#define GRIOMMU_CAP0_FT_GET( _reg ) \ + ( ( ( _reg ) >> 17 ) & 0x3U ) +#define GRIOMMU_CAP0_FT( _val ) ( ( _val ) << 17 ) + +#define GRIOMMU_CAP0_ST 0x10000U + +#define GRIOMMU_CAP0_I 0x8000U + +#define GRIOMMU_CAP0_IT 0x4000U + +#define GRIOMMU_CAP0_IA 0x2000U + +#define GRIOMMU_CAP0_IP 0x1000U + +#define GRIOMMU_CAP0_MB 0x100U + +#define GRIOMMU_CAP0_GRPS_SHIFT 4 +#define GRIOMMU_CAP0_GRPS_MASK 0xf0U +#define GRIOMMU_CAP0_GRPS_GET( _reg ) \ + ( ( ( _reg ) >> 4 ) & 0xfU ) +#define GRIOMMU_CAP0_GRPS( _val ) ( ( _val ) << 4 ) + +#define GRIOMMU_CAP0_MSTS_SHIFT 0 +#define GRIOMMU_CAP0_MSTS_MASK 0xfU +#define GRIOMMU_CAP0_MSTS_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xfU ) +#define GRIOMMU_CAP0_MSTS( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRIOMMUCAP1 Capability register 1 (CAP1) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRIOMMU_CAP1_CADDR_SHIFT 20 +#define GRIOMMU_CAP1_CADDR_MASK 0xfff00000U +#define GRIOMMU_CAP1_CADDR_GET( _reg ) \ + ( ( ( _reg ) >> 20 ) & 0xfffU ) +#define GRIOMMU_CAP1_CADDR( _val ) ( ( _val ) << 20 ) + +#define GRIOMMU_CAP1_CMASK_SHIFT 16 +#define GRIOMMU_CAP1_CMASK_MASK 0xf0000U +#define GRIOMMU_CAP1_CMASK_GET( _reg ) \ + ( ( ( _reg ) >> 16 ) & 0xfU ) +#define GRIOMMU_CAP1_CMASK( _val ) ( ( _val ) << 16 ) + +#define GRIOMMU_CAP1_CTAGBITS_SHIFT 8 +#define GRIOMMU_CAP1_CTAGBITS_MASK 0xff00U +#define GRIOMMU_CAP1_CTAGBITS_GET( _reg ) \ + ( ( ( _reg ) >> 8 ) & 0xffU ) +#define GRIOMMU_CAP1_CTAGBITS( _val ) ( ( _val ) << 8 ) + +#define GRIOMMU_CAP1_CISIZE_SHIFT 5 +#define GRIOMMU_CAP1_CISIZE_MASK 0xe0U +#define GRIOMMU_CAP1_CISIZE_GET( _reg ) \ + ( ( ( _reg ) >> 5 ) & 0x7U ) +#define GRIOMMU_CAP1_CISIZE( _val ) ( ( _val ) << 5 ) + +#define GRIOMMU_CAP1_CLINES_SHIFT 0 +#define GRIOMMU_CAP1_CLINES_MASK 0x1fU +#define GRIOMMU_CAP1_CLINES_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0x1fU ) +#define GRIOMMU_CAP1_CLINES( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRIOMMUCAP2 Capability register 2 (CAP2) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRIOMMU_CAP2_TMASK_SHIFT 24 +#define GRIOMMU_CAP2_TMASK_MASK 0xff000000U +#define GRIOMMU_CAP2_TMASK_GET( _reg ) \ + ( ( ( _reg ) >> 24 ) & 0xffU ) +#define GRIOMMU_CAP2_TMASK( _val ) ( ( _val ) << 24 ) + +#define GRIOMMU_CAP2_MTYPE_SHIFT 18 +#define GRIOMMU_CAP2_MTYPE_MASK 0xc0000U +#define GRIOMMU_CAP2_MTYPE_GET( _reg ) \ + ( ( ( _reg ) >> 18 ) & 0x3U ) +#define GRIOMMU_CAP2_MTYPE( _val ) ( ( _val ) << 18 ) + +#define GRIOMMU_CAP2_TTYPE_SHIFT 16 +#define GRIOMMU_CAP2_TTYPE_MASK 0x30000U +#define GRIOMMU_CAP2_TTYPE_GET( _reg ) \ + ( ( ( _reg ) >> 16 ) & 0x3U ) +#define GRIOMMU_CAP2_TTYPE( _val ) ( ( _val ) << 16 ) + +#define GRIOMMU_CAP2_TTAGBITS_SHIFT 8 +#define GRIOMMU_CAP2_TTAGBITS_MASK 0xff00U +#define GRIOMMU_CAP2_TTAGBITS_GET( _reg ) \ + ( ( ( _reg ) >> 8 ) & 0xffU ) +#define GRIOMMU_CAP2_TTAGBITS( _val ) ( ( _val ) << 8 ) + +#define GRIOMMU_CAP2_ISIZE_SHIFT 5 +#define GRIOMMU_CAP2_ISIZE_MASK 0xe0U +#define GRIOMMU_CAP2_ISIZE_GET( _reg ) \ + ( ( ( _reg ) >> 5 ) & 0x7U ) +#define GRIOMMU_CAP2_ISIZE( _val ) ( ( _val ) << 5 ) + +#define GRIOMMU_CAP2_TLBENT_SHIFT 0 +#define GRIOMMU_CAP2_TLBENT_MASK 0x1fU +#define GRIOMMU_CAP2_TLBENT_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0x1fU ) +#define GRIOMMU_CAP2_TLBENT( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRIOMMUCTRL Control register (CTRL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRIOMMU_CTRL_PGSZ_SHIFT 18 +#define GRIOMMU_CTRL_PGSZ_MASK 0x1c0000U +#define GRIOMMU_CTRL_PGSZ_GET( _reg ) \ + ( ( ( _reg ) >> 18 ) & 0x7U ) +#define GRIOMMU_CTRL_PGSZ( _val ) ( ( _val ) << 18 ) + +#define GRIOMMU_CTRL_LB 0x20000U + +#define GRIOMMU_CTRL_SP 0x10000U + +#define GRIOMMU_CTRL_ITR_SHIFT 12 +#define GRIOMMU_CTRL_ITR_MASK 0xf000U +#define GRIOMMU_CTRL_ITR_GET( _reg ) \ + ( ( ( _reg ) >> 12 ) & 0xfU ) +#define GRIOMMU_CTRL_ITR( _val ) ( ( _val ) << 12 ) + +#define GRIOMMU_CTRL_DP 0x800U + +#define GRIOMMU_CTRL_SIV 0x400U + +#define GRIOMMU_CTRL_HPROT_SHIFT 8 +#define GRIOMMU_CTRL_HPROT_MASK 0x300U +#define GRIOMMU_CTRL_HPROT_GET( _reg ) \ + ( ( ( _reg ) >> 8 ) & 0x3U ) +#define GRIOMMU_CTRL_HPROT( _val ) ( ( _val ) << 8 ) + +#define GRIOMMU_CTRL_AU 0x80U + +#define GRIOMMU_CTRL_WP 0x40U + +#define GRIOMMU_CTRL_DM 0x20U + +#define GRIOMMU_CTRL_GS 0x10U + +#define GRIOMMU_CTRL_CE 0x8U + +#define GRIOMMU_CTRL_PM_SHIFT 1 +#define GRIOMMU_CTRL_PM_MASK 0x6U +#define GRIOMMU_CTRL_PM_GET( _reg ) \ + ( ( ( _reg ) >> 1 ) & 0x3U ) +#define GRIOMMU_CTRL_PM( _val ) ( ( _val ) << 1 ) + +#define GRIOMMU_CTRL_EN 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRIOMMUFLUSH TLB/cache flush register (FLUSH) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRIOMMU_FLUSH_FGRP_SHIFT 4 +#define GRIOMMU_FLUSH_FGRP_MASK 0xf0U +#define GRIOMMU_FLUSH_FGRP_GET( _reg ) \ + ( ( ( _reg ) >> 4 ) & 0xfU ) +#define GRIOMMU_FLUSH_FGRP( _val ) ( ( _val ) << 4 ) + +#define GRIOMMU_FLUSH_GF 0x2U + +#define GRIOMMU_FLUSH_F 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRIOMMUSTATUS Status register (STATUS) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRIOMMU_STATUS_PE 0x20U + +#define GRIOMMU_STATUS_DE 0x10U + +#define GRIOMMU_STATUS_FC 0x8U + +#define GRIOMMU_STATUS_FL 0x4U + +#define GRIOMMU_STATUS_AD 0x2U + +#define GRIOMMU_STATUS_TE 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRIOMMUIMASK Interrupt mask register (IMASK) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRIOMMU_IMASK_PEI 0x20U + +#define GRIOMMU_IMASK_FCI 0x8U + +#define GRIOMMU_IMASK_FLI 0x4U + +#define GRIOMMU_IMASK_ADI 0x2U + +#define GRIOMMU_IMASK_TEI 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRIOMMUAHBFAS AHB failing access register (AHBFAS) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRIOMMU_AHBFAS_FADDR_31_5_SHIFT 5 +#define GRIOMMU_AHBFAS_FADDR_31_5_MASK 0xffffffe0U +#define GRIOMMU_AHBFAS_FADDR_31_5_GET( _reg ) \ + ( ( ( _reg ) >> 5 ) & 0x7ffffffU ) +#define GRIOMMU_AHBFAS_FADDR_31_5( _val ) ( ( _val ) << 5 ) + +#define GRIOMMU_AHBFAS_FW 0x10U + +#define GRIOMMU_AHBFAS_FMASTER_SHIFT 0 +#define GRIOMMU_AHBFAS_FMASTER_MASK 0xfU +#define GRIOMMU_AHBFAS_FMASTER_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xfU ) +#define GRIOMMU_AHBFAS_FMASTER( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRIOMMUMSTCFG \ + * Master configuration register 0 - 9 (MSTCFG) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRIOMMU_MSTCFG_VENDOR_SHIFT 24 +#define GRIOMMU_MSTCFG_VENDOR_MASK 0xff000000U +#define GRIOMMU_MSTCFG_VENDOR_GET( _reg ) \ + ( ( ( _reg ) >> 24 ) & 0xffU ) +#define GRIOMMU_MSTCFG_VENDOR( _val ) ( ( _val ) << 24 ) + +#define GRIOMMU_MSTCFG_DEVICE_SHIFT 12 +#define GRIOMMU_MSTCFG_DEVICE_MASK 0xfff000U +#define GRIOMMU_MSTCFG_DEVICE_GET( _reg ) \ + ( ( ( _reg ) >> 12 ) & 0xfffU ) +#define GRIOMMU_MSTCFG_DEVICE( _val ) ( ( _val ) << 12 ) + +#define GRIOMMU_MSTCFG_BS 0x10U + +#define GRIOMMU_MSTCFG_GROUP_SHIFT 0 +#define GRIOMMU_MSTCFG_GROUP_MASK 0xfU +#define GRIOMMU_MSTCFG_GROUP_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xfU ) +#define GRIOMMU_MSTCFG_GROUP( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRIOMMUGRPCTRL Group control register 0 - 7 (GRPCTRL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRIOMMU_GRPCTRL_BASE_31_4_SHIFT 4 +#define GRIOMMU_GRPCTRL_BASE_31_4_MASK 0xfffffff0U +#define GRIOMMU_GRPCTRL_BASE_31_4_GET( _reg ) \ + ( ( ( _reg ) >> 4 ) & 0xfffffffU ) +#define GRIOMMU_GRPCTRL_BASE_31_4( _val ) ( ( _val ) << 4 ) + +#define GRIOMMU_GRPCTRL_P 0x2U + +#define GRIOMMU_GRPCTRL_AG 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRIOMMUDIAGCTRL \ + * Diagnostic cache access register (DIAGCTRL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRIOMMU_DIAGCTRL_DA 0x80000000U + +#define GRIOMMU_DIAGCTRL_RW 0x40000000U + +#define GRIOMMU_DIAGCTRL_DP 0x200000U + +#define GRIOMMU_DIAGCTRL_TP 0x100000U + +#define GRIOMMU_DIAGCTRL_SETADDR_SHIFT 0 +#define GRIOMMU_DIAGCTRL_SETADDR_MASK 0x7ffffU +#define GRIOMMU_DIAGCTRL_SETADDR_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0x7ffffU ) +#define GRIOMMU_DIAGCTRL_SETADDR( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRIOMMUDIAGD \ + * Diagnostic cache access data register 0 - 7 (DIAGD) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRIOMMU_DIAGD_CDATAN_SHIFT 0 +#define GRIOMMU_DIAGD_CDATAN_MASK 0xffffffffU +#define GRIOMMU_DIAGD_CDATAN_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define GRIOMMU_DIAGD_CDATAN( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRIOMMUDIAGT \ + * Diagnostic cache access tag register (DIAGT) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRIOMMU_DIAGT_TAG_SHIFT 1 +#define GRIOMMU_DIAGT_TAG_MASK 0xfffffffeU +#define GRIOMMU_DIAGT_TAG_GET( _reg ) \ + ( ( ( _reg ) >> 1 ) & 0x7fffffffU ) +#define GRIOMMU_DIAGT_TAG( _val ) ( ( _val ) << 1 ) + +#define GRIOMMU_DIAGT_V 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRIOMMUDERRI Data RAM error injection register (DERRI) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRIOMMU_DERRI_DPERRINJ_SHIFT 0 +#define GRIOMMU_DERRI_DPERRINJ_MASK 0xffffffffU +#define GRIOMMU_DERRI_DPERRINJ_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define GRIOMMU_DERRI_DPERRINJ( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRIOMMUTERRI Tag RAM error injection register (TERRI) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRIOMMU_TERRI_TPERRINJ_SHIFT 0 +#define GRIOMMU_TERRI_TPERRINJ_MASK 0xffffffffU +#define GRIOMMU_TERRI_TPERRINJ_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define GRIOMMU_TERRI_TPERRINJ( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRIOMMUASMPCTRL \ + * ASMP access control registers 0 - 3 (ASMPCTRL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRIOMMU_ASMPCTRL_FC 0x40000U + +#define GRIOMMU_ASMPCTRL_SC 0x20000U + +#define GRIOMMU_ASMPCTRL_MC 0x10000U + +#define GRIOMMU_ASMPCTRL_GRPACCSZCTRL_SHIFT 0 +#define GRIOMMU_ASMPCTRL_GRPACCSZCTRL_MASK 0xffffU +#define GRIOMMU_ASMPCTRL_GRPACCSZCTRL_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffU ) +#define GRIOMMU_ASMPCTRL_GRPACCSZCTRL( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @brief This structure defines the GRIOMMU register block memory map. + */ +typedef struct griommu { + /** + * @brief See @ref RTEMSDeviceGRIOMMUCAP0. + */ + uint32_t cap0; + + /** + * @brief See @ref RTEMSDeviceGRIOMMUCAP1. + */ + uint32_t cap1; + + /** + * @brief See @ref RTEMSDeviceGRIOMMUCAP2. + */ + uint32_t cap2; + + uint32_t reserved_c_10; + + /** + * @brief See @ref RTEMSDeviceGRIOMMUCTRL. + */ + uint32_t ctrl; + + /** + * @brief See @ref RTEMSDeviceGRIOMMUFLUSH. + */ + uint32_t flush; + + /** + * @brief See @ref RTEMSDeviceGRIOMMUSTATUS. + */ + uint32_t status; + + /** + * @brief See @ref RTEMSDeviceGRIOMMUIMASK. + */ + uint32_t imask; + + /** + * @brief See @ref RTEMSDeviceGRIOMMUAHBFAS. + */ + uint32_t ahbfas; + + uint32_t reserved_24_40[ 7 ]; + + /** + * @brief See @ref RTEMSDeviceGRIOMMUMSTCFG. + */ + uint32_t mstcfg_0; + + uint32_t reserved_44_64[ 8 ]; + + /** + * @brief See @ref RTEMSDeviceGRIOMMUMSTCFG. + */ + uint32_t mstcfg_1; + + uint32_t reserved_68_80[ 6 ]; + + /** + * @brief See @ref RTEMSDeviceGRIOMMUGRPCTRL. + */ + uint32_t grpctrl_0; + + uint32_t reserved_84_9c[ 6 ]; + + /** + * @brief See @ref RTEMSDeviceGRIOMMUGRPCTRL. + */ + uint32_t grpctrl_1; + + uint32_t reserved_a0_c0[ 8 ]; + + /** + * @brief See @ref RTEMSDeviceGRIOMMUDIAGCTRL. + */ + uint32_t diagctrl; + + /** + * @brief See @ref RTEMSDeviceGRIOMMUDIAGD. + */ + uint32_t diagd_0; + + uint32_t reserved_c8_e0[ 6 ]; + + /** + * @brief See @ref RTEMSDeviceGRIOMMUDIAGD. + */ + uint32_t diagd_1; + + /** + * @brief See @ref RTEMSDeviceGRIOMMUDIAGT. + */ + uint32_t diagt; + + /** + * @brief See @ref RTEMSDeviceGRIOMMUDERRI. + */ + uint32_t derri; + + /** + * @brief See @ref RTEMSDeviceGRIOMMUTERRI. + */ + uint32_t terri; + + uint32_t reserved_f0_100[ 4 ]; + + /** + * @brief See @ref RTEMSDeviceGRIOMMUASMPCTRL. + */ + uint32_t asmpctrl_0; + + uint32_t reserved_104_10c[ 2 ]; + + /** + * @brief See @ref RTEMSDeviceGRIOMMUASMPCTRL. + */ + uint32_t asmpctrl_1; +} griommu; + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GRLIB_GRIOMMU_REGS_H */ diff --git a/bsps/include/grlib/grpci2-regs.h b/bsps/include/grlib/grpci2-regs.h new file mode 100644 index 0000000000..daff28689e --- /dev/null +++ b/bsps/include/grlib/grpci2-regs.h @@ -0,0 +1,679 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSDeviceGRPCI2 + * + * @brief This header file defines the GRPCI2 register block interface. + */ + +/* + * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file is part of the RTEMS quality process and was automatically + * generated. If you find something that needs to be fixed or + * worded better please post a report or patch to an RTEMS mailing list + * or raise a bug report: + * + * https://www.rtems.org/bugs.html + * + * For information on updating and regenerating please refer to the How-To + * section in the Software Requirements Engineering chapter of the + * RTEMS Software Engineering manual. The manual is provided as a part of + * a release. For development sources please refer to the online + * documentation at: + * + * https://docs.rtems.org + */ + +/* Generated from spec:/dev/grlib/if/grpci2-header */ + +#ifndef _GRLIB_GRPCI2_REGS_H +#define _GRLIB_GRPCI2_REGS_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Generated from spec:/dev/grlib/if/grpci2 */ + +/** + * @defgroup RTEMSDeviceGRPCI2 GRPCI2 + * + * @ingroup RTEMSDeviceGRLIB + * + * @brief This group contains the GRPCI2 interfaces. + * + * @{ + */ + +/** + * @defgroup RTEMSDeviceGRPCI2CTRL Control register (CTRL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRPCI2_CTRL_RE 0x80000000U + +#define GRPCI2_CTRL_MR 0x40000000U + +#define GRPCI2_CTRL_TR 0x20000000U + +#define GRPCI2_CTRL_SI 0x8000000U + +#define GRPCI2_CTRL_PE 0x4000000U + +#define GRPCI2_CTRL_ER 0x2000000U + +#define GRPCI2_CTRL_EI 0x1000000U + +#define GRPCI2_CTRL_BUS_NUMBER_SHIFT 16 +#define GRPCI2_CTRL_BUS_NUMBER_MASK 0xff0000U +#define GRPCI2_CTRL_BUS_NUMBER_GET( _reg ) \ + ( ( ( _reg ) >> 16 ) & 0xffU ) +#define GRPCI2_CTRL_BUS_NUMBER( _val ) ( ( _val ) << 16 ) + +#define GRPCI2_CTRL_DFA 0x800U + +#define GRPCI2_CTRL_IB 0x400U + +#define GRPCI2_CTRL_CB 0x200U + +#define GRPCI2_CTRL_DIF 0x100U + +#define GRPCI2_CTRL_DEVICE_INT_MASK_SHIFT 4 +#define GRPCI2_CTRL_DEVICE_INT_MASK_MASK 0xf0U +#define GRPCI2_CTRL_DEVICE_INT_MASK_GET( _reg ) \ + ( ( ( _reg ) >> 4 ) & 0xfU ) +#define GRPCI2_CTRL_DEVICE_INT_MASK( _val ) ( ( _val ) << 4 ) + +#define GRPCI2_CTRL_HOST_INT_MASK_SHIFT 0 +#define GRPCI2_CTRL_HOST_INT_MASK_MASK 0xfU +#define GRPCI2_CTRL_HOST_INT_MASK_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xfU ) +#define GRPCI2_CTRL_HOST_INT_MASK( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRPCI2STATCAP Status and Capability register (STATCAP) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRPCI2_STATCAP_HOST 0x80000000U + +#define GRPCI2_STATCAP_MST 0x40000000U + +#define GRPCI2_STATCAP_TAR 0x20000000U + +#define GRPCI2_STATCAP_DMA 0x10000000U + +#define GRPCI2_STATCAP_DI 0x8000000U + +#define GRPCI2_STATCAP_HI 0x4000000U + +#define GRPCI2_STATCAP_IRQ_MODE_SHIFT 24 +#define GRPCI2_STATCAP_IRQ_MODE_MASK 0x3000000U +#define GRPCI2_STATCAP_IRQ_MODE_GET( _reg ) \ + ( ( ( _reg ) >> 24 ) & 0x3U ) +#define GRPCI2_STATCAP_IRQ_MODE( _val ) ( ( _val ) << 24 ) + +#define GRPCI2_STATCAP_TRACE 0x800000U + +#define GRPCI2_STATCAP_CFGDO 0x100000U + +#define GRPCI2_STATCAP_CFGER 0x80000U + +#define GRPCI2_STATCAP_CORE_INT_STATUS_SHIFT 12 +#define GRPCI2_STATCAP_CORE_INT_STATUS_MASK 0x7f000U +#define GRPCI2_STATCAP_CORE_INT_STATUS_GET( _reg ) \ + ( ( ( _reg ) >> 12 ) & 0x7fU ) +#define GRPCI2_STATCAP_CORE_INT_STATUS( _val ) ( ( _val ) << 12 ) + +#define GRPCI2_STATCAP_HOST_INT_STATUS_SHIFT 8 +#define GRPCI2_STATCAP_HOST_INT_STATUS_MASK 0xf00U +#define GRPCI2_STATCAP_HOST_INT_STATUS_GET( _reg ) \ + ( ( ( _reg ) >> 8 ) & 0xfU ) +#define GRPCI2_STATCAP_HOST_INT_STATUS( _val ) ( ( _val ) << 8 ) + +#define GRPCI2_STATCAP_FDEPTH_SHIFT 2 +#define GRPCI2_STATCAP_FDEPTH_MASK 0x1cU +#define GRPCI2_STATCAP_FDEPTH_GET( _reg ) \ + ( ( ( _reg ) >> 2 ) & 0x7U ) +#define GRPCI2_STATCAP_FDEPTH( _val ) ( ( _val ) << 2 ) + +#define GRPCI2_STATCAP_FNUM_SHIFT 0 +#define GRPCI2_STATCAP_FNUM_MASK 0x3U +#define GRPCI2_STATCAP_FNUM_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0x3U ) +#define GRPCI2_STATCAP_FNUM( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRPCI2BCIM PCI master prefetch burst limit (BCIM) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRPCI2_BCIM_AHB_MASTER_UNMASK_SHIFT 16 +#define GRPCI2_BCIM_AHB_MASTER_UNMASK_MASK 0xffff0000U +#define GRPCI2_BCIM_AHB_MASTER_UNMASK_GET( _reg ) \ + ( ( ( _reg ) >> 16 ) & 0xffffU ) +#define GRPCI2_BCIM_AHB_MASTER_UNMASK( _val ) ( ( _val ) << 16 ) + +#define GRPCI2_BCIM_BURST_LENGTH_SHIFT 0 +#define GRPCI2_BCIM_BURST_LENGTH_MASK 0xffU +#define GRPCI2_BCIM_BURST_LENGTH_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffU ) +#define GRPCI2_BCIM_BURST_LENGTH( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRPCI2AHB2PCI AHB to PCI mapping for PCI IO (AHB2PCI) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRPCI2_AHB2PCI_AHB_TO_PCI_IO_SHIFT 16 +#define GRPCI2_AHB2PCI_AHB_TO_PCI_IO_MASK 0xffff0000U +#define GRPCI2_AHB2PCI_AHB_TO_PCI_IO_GET( _reg ) \ + ( ( ( _reg ) >> 16 ) & 0xffffU ) +#define GRPCI2_AHB2PCI_AHB_TO_PCI_IO( _val ) ( ( _val ) << 16 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRPCI2DMACTRL DMA control and status register (DMACTRL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRPCI2_DMACTRL_SAFE 0x80000000U + +#define GRPCI2_DMACTRL_CHIRQ_SHIFT 12 +#define GRPCI2_DMACTRL_CHIRQ_MASK 0xff000U +#define GRPCI2_DMACTRL_CHIRQ_GET( _reg ) \ + ( ( ( _reg ) >> 12 ) & 0xffU ) +#define GRPCI2_DMACTRL_CHIRQ( _val ) ( ( _val ) << 12 ) + +#define GRPCI2_DMACTRL_MA 0x800U + +#define GRPCI2_DMACTRL_TA 0x400U + +#define GRPCI2_DMACTRL_PE 0x200U + +#define GRPCI2_DMACTRL_AE 0x100U + +#define GRPCI2_DMACTRL_DE 0x80U + +#define GRPCI2_DMACTRL_NUMCH_SHIFT 4 +#define GRPCI2_DMACTRL_NUMCH_MASK 0x70U +#define GRPCI2_DMACTRL_NUMCH_GET( _reg ) \ + ( ( ( _reg ) >> 4 ) & 0x7U ) +#define GRPCI2_DMACTRL_NUMCH( _val ) ( ( _val ) << 4 ) + +#define GRPCI2_DMACTRL_ACTIVE 0x8U + +#define GRPCI2_DMACTRL_DIS 0x4U + +#define GRPCI2_DMACTRL_IE 0x2U + +#define GRPCI2_DMACTRL_EN 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRPCI2DMABASE \ + * DMA descriptor base address register (DMABASE) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRPCI2_DMABASE_BASE_SHIFT 0 +#define GRPCI2_DMABASE_BASE_MASK 0xffffffffU +#define GRPCI2_DMABASE_BASE_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define GRPCI2_DMABASE_BASE( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRPCI2DMACHAN DMA channel active register (DMACHAN) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRPCI2_DMACHAN_CHAN_SHIFT 0 +#define GRPCI2_DMACHAN_CHAN_MASK 0xffffffffU +#define GRPCI2_DMACHAN_CHAN_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define GRPCI2_DMACHAN_CHAN( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRPCI2PCI2AHB \ + * PCI BAR to AHB address mapping register (PCI2AHB) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRPCI2_PCI2AHB_ADDR_SHIFT 0 +#define GRPCI2_PCI2AHB_ADDR_MASK 0xffffffffU +#define GRPCI2_PCI2AHB_ADDR_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define GRPCI2_PCI2AHB_ADDR( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRPCI2AHBM2PCI \ + * AHB master to PCI memory address mapping register (AHBM2PCI) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRPCI2_AHBM2PCI_ADDR_SHIFT 0 +#define GRPCI2_AHBM2PCI_ADDR_MASK 0xffffffffU +#define GRPCI2_AHBM2PCI_ADDR_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define GRPCI2_AHBM2PCI_ADDR( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRPCI2TCTRC \ + * PCI trace Control and Status register (TCTRC) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRPCI2_TCTRC_TRIG_INDEX_SHIFT 16 +#define GRPCI2_TCTRC_TRIG_INDEX_MASK 0xffff0000U +#define GRPCI2_TCTRC_TRIG_INDEX_GET( _reg ) \ + ( ( ( _reg ) >> 16 ) & 0xffffU ) +#define GRPCI2_TCTRC_TRIG_INDEX( _val ) ( ( _val ) << 16 ) + +#define GRPCI2_TCTRC_AR 0x8000U + +#define GRPCI2_TCTRC_EN 0x4000U + +#define GRPCI2_TCTRC_DEPTH_SHIFT 4 +#define GRPCI2_TCTRC_DEPTH_MASK 0xff0U +#define GRPCI2_TCTRC_DEPTH_GET( _reg ) \ + ( ( ( _reg ) >> 4 ) & 0xffU ) +#define GRPCI2_TCTRC_DEPTH( _val ) ( ( _val ) << 4 ) + +#define GRPCI2_TCTRC_SO 0x2U + +#define GRPCI2_TCTRC_SA 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRPCI2TMODE PCI trace counter and mode register (TMODE) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRPCI2_TMODE_TRACING_MODE_SHIFT 24 +#define GRPCI2_TMODE_TRACING_MODE_MASK 0xf000000U +#define GRPCI2_TMODE_TRACING_MODE_GET( _reg ) \ + ( ( ( _reg ) >> 24 ) & 0xfU ) +#define GRPCI2_TMODE_TRACING_MODE( _val ) ( ( _val ) << 24 ) + +#define GRPCI2_TMODE_TRIG_COUNT_SHIFT 16 +#define GRPCI2_TMODE_TRIG_COUNT_MASK 0xff0000U +#define GRPCI2_TMODE_TRIG_COUNT_GET( _reg ) \ + ( ( ( _reg ) >> 16 ) & 0xffU ) +#define GRPCI2_TMODE_TRIG_COUNT( _val ) ( ( _val ) << 16 ) + +#define GRPCI2_TMODE_DELAYED_STOP_SHIFT 0 +#define GRPCI2_TMODE_DELAYED_STOP_MASK 0xffffU +#define GRPCI2_TMODE_DELAYED_STOP_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffU ) +#define GRPCI2_TMODE_DELAYED_STOP( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRPCI2TADP PCI trace AD pattern register (TADP) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRPCI2_TADP_PATTERN_SHIFT 0 +#define GRPCI2_TADP_PATTERN_MASK 0xffffffffU +#define GRPCI2_TADP_PATTERN_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define GRPCI2_TADP_PATTERN( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRPCI2TADM PCI trace AD mask register (TADM) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRPCI2_TADM_MASK_SHIFT 0 +#define GRPCI2_TADM_MASK_MASK 0xffffffffU +#define GRPCI2_TADM_MASK_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define GRPCI2_TADM_MASK( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRPCI2TCP PCI trace Ctrl signal pattern register (TCP) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRPCI2_TCP_CBE_3_0_SHIFT 16 +#define GRPCI2_TCP_CBE_3_0_MASK 0xf0000U +#define GRPCI2_TCP_CBE_3_0_GET( _reg ) \ + ( ( ( _reg ) >> 16 ) & 0xfU ) +#define GRPCI2_TCP_CBE_3_0( _val ) ( ( _val ) << 16 ) + +#define GRPCI2_TCP_FRAME 0x8000U + +#define GRPCI2_TCP_IRDY 0x4000U + +#define GRPCI2_TCP_TRDY 0x2000U + +#define GRPCI2_TCP_STOP 0x1000U + +#define GRPCI2_TCP_DEVSEL 0x800U + +#define GRPCI2_TCP_PAR 0x400U + +#define GRPCI2_TCP_PERR 0x200U + +#define GRPCI2_TCP_SERR 0x100U + +#define GRPCI2_TCP_IDSEL 0x80U + +#define GRPCI2_TCP_REQ 0x40U + +#define GRPCI2_TCP_GNT 0x20U + +#define GRPCI2_TCP_LOCK 0x10U + +#define GRPCI2_TCP_RST 0x8U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRPCI2TCM PCI trace Ctrl signal mask register (TCM) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRPCI2_TCM_CBE_3_0_SHIFT 16 +#define GRPCI2_TCM_CBE_3_0_MASK 0xf0000U +#define GRPCI2_TCM_CBE_3_0_GET( _reg ) \ + ( ( ( _reg ) >> 16 ) & 0xfU ) +#define GRPCI2_TCM_CBE_3_0( _val ) ( ( _val ) << 16 ) + +#define GRPCI2_TCM_FRAME 0x8000U + +#define GRPCI2_TCM_IRDY 0x4000U + +#define GRPCI2_TCM_TRDY 0x2000U + +#define GRPCI2_TCM_STOP 0x1000U + +#define GRPCI2_TCM_DEVSEL 0x800U + +#define GRPCI2_TCM_PAR 0x400U + +#define GRPCI2_TCM_PERR 0x200U + +#define GRPCI2_TCM_SERR 0x100U + +#define GRPCI2_TCM_IDSEL 0x80U + +#define GRPCI2_TCM_REQ 0x40U + +#define GRPCI2_TCM_GNT 0x20U + +#define GRPCI2_TCM_LOCK 0x10U + +#define GRPCI2_TCM_RST 0x8U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRPCI2TADS PCI trace PCI AD state register (TADS) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRPCI2_TADS_SIGNAL_SHIFT 0 +#define GRPCI2_TADS_SIGNAL_MASK 0xffffffffU +#define GRPCI2_TADS_SIGNAL_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define GRPCI2_TADS_SIGNAL( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRPCI2TCS \ + * PCI trace PCI Ctrl signal state register (TCS) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRPCI2_TCS_CBE_3_0_SHIFT 16 +#define GRPCI2_TCS_CBE_3_0_MASK 0xf0000U +#define GRPCI2_TCS_CBE_3_0_GET( _reg ) \ + ( ( ( _reg ) >> 16 ) & 0xfU ) +#define GRPCI2_TCS_CBE_3_0( _val ) ( ( _val ) << 16 ) + +#define GRPCI2_TCS_FRAME 0x8000U + +#define GRPCI2_TCS_IRDY 0x4000U + +#define GRPCI2_TCS_TRDY 0x2000U + +#define GRPCI2_TCS_STOP 0x1000U + +#define GRPCI2_TCS_DEVSEL 0x800U + +#define GRPCI2_TCS_PAR 0x400U + +#define GRPCI2_TCS_PERR 0x200U + +#define GRPCI2_TCS_SERR 0x100U + +#define GRPCI2_TCS_IDSEL 0x80U + +#define GRPCI2_TCS_REQ 0x40U + +#define GRPCI2_TCS_GNT 0x20U + +#define GRPCI2_TCS_LOCK 0x10U + +#define GRPCI2_TCS_RST 0x8U + +/** @} */ + +/** + * @brief This structure defines the GRPCI2 register block memory map. + */ +typedef struct grpci2 { + /** + * @brief See @ref RTEMSDeviceGRPCI2CTRL. + */ + uint32_t ctrl; + + /** + * @brief See @ref RTEMSDeviceGRPCI2STATCAP. + */ + uint32_t statcap; + + /** + * @brief See @ref RTEMSDeviceGRPCI2BCIM. + */ + uint32_t bcim; + + /** + * @brief See @ref RTEMSDeviceGRPCI2AHB2PCI. + */ + uint32_t ahb2pci; + + /** + * @brief See @ref RTEMSDeviceGRPCI2DMACTRL. + */ + uint32_t dmactrl; + + /** + * @brief See @ref RTEMSDeviceGRPCI2DMABASE. + */ + uint32_t dmabase; + + /** + * @brief See @ref RTEMSDeviceGRPCI2DMACHAN. + */ + uint32_t dmachan; + + uint32_t reserved_1c_20; + + /** + * @brief See @ref RTEMSDeviceGRPCI2PCI2AHB. + */ + uint32_t pci2ahb_0; + + uint32_t reserved_24_34[ 4 ]; + + /** + * @brief See @ref RTEMSDeviceGRPCI2PCI2AHB. + */ + uint32_t pci2ahb_1; + + uint32_t reserved_38_40[ 2 ]; + + /** + * @brief See @ref RTEMSDeviceGRPCI2AHBM2PCI. + */ + uint32_t ahbm2pci_0; + + uint32_t reserved_44_7c[ 14 ]; + + /** + * @brief See @ref RTEMSDeviceGRPCI2AHBM2PCI. + */ + uint32_t ahbm2pci_1; + + /** + * @brief See @ref RTEMSDeviceGRPCI2TCTRC. + */ + uint32_t tctrc; + + /** + * @brief See @ref RTEMSDeviceGRPCI2TMODE. + */ + uint32_t tmode; + + /** + * @brief See @ref RTEMSDeviceGRPCI2TADP. + */ + uint32_t tadp; + + /** + * @brief See @ref RTEMSDeviceGRPCI2TADM. + */ + uint32_t tadm; + + /** + * @brief See @ref RTEMSDeviceGRPCI2TCP. + */ + uint32_t tcp; + + /** + * @brief See @ref RTEMSDeviceGRPCI2TCM. + */ + uint32_t tcm; + + /** + * @brief See @ref RTEMSDeviceGRPCI2TADS. + */ + uint32_t tads; + + /** + * @brief See @ref RTEMSDeviceGRPCI2TCS. + */ + uint32_t tcs; +} grpci2; + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GRLIB_GRPCI2_REGS_H */ diff --git a/bsps/include/grlib/grspw2-regs.h b/bsps/include/grlib/grspw2-regs.h new file mode 100644 index 0000000000..9c560b42f0 --- /dev/null +++ b/bsps/include/grlib/grspw2-regs.h @@ -0,0 +1,461 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSDeviceGRSPW2 + * + * @brief This header file defines the GRSPW2 register block interface. + */ + +/* + * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file is part of the RTEMS quality process and was automatically + * generated. If you find something that needs to be fixed or + * worded better please post a report or patch to an RTEMS mailing list + * or raise a bug report: + * + * https://www.rtems.org/bugs.html + * + * For information on updating and regenerating please refer to the How-To + * section in the Software Requirements Engineering chapter of the + * RTEMS Software Engineering manual. The manual is provided as a part of + * a release. For development sources please refer to the online + * documentation at: + * + * https://docs.rtems.org + */ + +/* Generated from spec:/dev/grlib/if/grspw2-header */ + +#ifndef _GRLIB_GRSPW2_REGS_H +#define _GRLIB_GRSPW2_REGS_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Generated from spec:/dev/grlib/if/grspw2 */ + +/** + * @defgroup RTEMSDeviceGRSPW2 GRSPW2 + * + * @ingroup RTEMSDeviceGRLIB + * + * @brief This group contains the GRSPW2 interfaces. + * + * @{ + */ + +/** + * @defgroup RTEMSDeviceGRSPW2CTRL Control (CTRL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPW2_CTRL_RA 0x80000000U + +#define GRSPW2_CTRL_RX 0x40000000U + +#define GRSPW2_CTRL_RC 0x20000000U + +#define GRSPW2_CTRL_NCH_SHIFT 27 +#define GRSPW2_CTRL_NCH_MASK 0x18000000U +#define GRSPW2_CTRL_NCH_GET( _reg ) \ + ( ( ( _reg ) >> 27 ) & 0x3U ) +#define GRSPW2_CTRL_NCH( _val ) ( ( _val ) << 27 ) + +#define GRSPW2_CTRL_PO 0x4000000U + +#define GRSPW2_CTRL_RD 0x20000U + +#define GRSPW2_CTRL_RE 0x10000U + +#define GRSPW2_CTRL_TL 0x2000U + +#define GRSPW2_CTRL_TF 0x1000U + +#define GRSPW2_CTRL_TR 0x800U + +#define GRSPW2_CTRL_TT 0x400U + +#define GRSPW2_CTRL_LI 0x200U + +#define GRSPW2_CTRL_TQ 0x100U + +#define GRSPW2_CTRL_RS 0x40U + +#define GRSPW2_CTRL_PM 0x20U + +#define GRSPW2_CTRL_TI 0x10U + +#define GRSPW2_CTRL_IE 0x8U + +#define GRSPW2_CTRL_AS 0x4U + +#define GRSPW2_CTRL_LS 0x2U + +#define GRSPW2_CTRL_LD 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPW2STS Status (STS) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPW2_STS_NRXD_SHIFT 26 +#define GRSPW2_STS_NRXD_MASK 0xc000000U +#define GRSPW2_STS_NRXD_GET( _reg ) \ + ( ( ( _reg ) >> 26 ) & 0x3U ) +#define GRSPW2_STS_NRXD( _val ) ( ( _val ) << 26 ) + +#define GRSPW2_STS_NTXD_SHIFT 24 +#define GRSPW2_STS_NTXD_MASK 0x3000000U +#define GRSPW2_STS_NTXD_GET( _reg ) \ + ( ( ( _reg ) >> 24 ) & 0x3U ) +#define GRSPW2_STS_NTXD( _val ) ( ( _val ) << 24 ) + +#define GRSPW2_STS_LS_SHIFT 21 +#define GRSPW2_STS_LS_MASK 0xe00000U +#define GRSPW2_STS_LS_GET( _reg ) \ + ( ( ( _reg ) >> 21 ) & 0x7U ) +#define GRSPW2_STS_LS( _val ) ( ( _val ) << 21 ) + +#define GRSPW2_STS_EE 0x100U + +#define GRSPW2_STS_IA 0x80U + +#define GRSPW2_STS_PE 0x10U + +#define GRSPW2_STS_DE 0x8U + +#define GRSPW2_STS_ER 0x4U + +#define GRSPW2_STS_CE 0x2U + +#define GRSPW2_STS_TO 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPW2DEFADDR Default address (DEFADDR) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPW2_DEFADDR_DEFMASK_SHIFT 8 +#define GRSPW2_DEFADDR_DEFMASK_MASK 0xff00U +#define GRSPW2_DEFADDR_DEFMASK_GET( _reg ) \ + ( ( ( _reg ) >> 8 ) & 0xffU ) +#define GRSPW2_DEFADDR_DEFMASK( _val ) ( ( _val ) << 8 ) + +#define GRSPW2_DEFADDR_DEFADDR_SHIFT 0 +#define GRSPW2_DEFADDR_DEFADDR_MASK 0xffU +#define GRSPW2_DEFADDR_DEFADDR_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffU ) +#define GRSPW2_DEFADDR_DEFADDR( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPW2CLKDIV Clock divisor (CLKDIV) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPW2_CLKDIV_CLKDIVSTART_SHIFT 8 +#define GRSPW2_CLKDIV_CLKDIVSTART_MASK 0xff00U +#define GRSPW2_CLKDIV_CLKDIVSTART_GET( _reg ) \ + ( ( ( _reg ) >> 8 ) & 0xffU ) +#define GRSPW2_CLKDIV_CLKDIVSTART( _val ) ( ( _val ) << 8 ) + +#define GRSPW2_CLKDIV_CLKDIVRUN_SHIFT 0 +#define GRSPW2_CLKDIV_CLKDIVRUN_MASK 0xffU +#define GRSPW2_CLKDIV_CLKDIVRUN_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffU ) +#define GRSPW2_CLKDIV_CLKDIVRUN( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPW2DKEY Destination key (DKEY) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPW2_DKEY_DESTKEY_SHIFT 0 +#define GRSPW2_DKEY_DESTKEY_MASK 0xffU +#define GRSPW2_DKEY_DESTKEY_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffU ) +#define GRSPW2_DKEY_DESTKEY( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPW2TC Time-code (TC) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPW2_TC_TCTRL_SHIFT 6 +#define GRSPW2_TC_TCTRL_MASK 0xc0U +#define GRSPW2_TC_TCTRL_GET( _reg ) \ + ( ( ( _reg ) >> 6 ) & 0x3U ) +#define GRSPW2_TC_TCTRL( _val ) ( ( _val ) << 6 ) + +#define GRSPW2_TC_TIMECNT_SHIFT 0 +#define GRSPW2_TC_TIMECNT_MASK 0x3fU +#define GRSPW2_TC_TIMECNT_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0x3fU ) +#define GRSPW2_TC_TIMECNT( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPW2DMACTRL DMA control/status, channel 1 (DMACTRL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPW2_DMACTRL_EP 0x800000U + +#define GRSPW2_DMACTRL_TR 0x400000U + +#define GRSPW2_DMACTRL_RP 0x80000U + +#define GRSPW2_DMACTRL_TP 0x40000U + +#define GRSPW2_DMACTRL_TL 0x20000U + +#define GRSPW2_DMACTRL_LE 0x10000U + +#define GRSPW2_DMACTRL_SP 0x8000U + +#define GRSPW2_DMACTRL_SA 0x4000U + +#define GRSPW2_DMACTRL_EN 0x2000U + +#define GRSPW2_DMACTRL_NS 0x1000U + +#define GRSPW2_DMACTRL_RD 0x800U + +#define GRSPW2_DMACTRL_RX 0x400U + +#define GRSPW2_DMACTRL_AT 0x200U + +#define GRSPW2_DMACTRL_RA 0x100U + +#define GRSPW2_DMACTRL_TA 0x80U + +#define GRSPW2_DMACTRL_PR 0x40U + +#define GRSPW2_DMACTRL_PS 0x20U + +#define GRSPW2_DMACTRL_AI 0x10U + +#define GRSPW2_DMACTRL_RI 0x8U + +#define GRSPW2_DMACTRL_TI 0x4U + +#define GRSPW2_DMACTRL_RE 0x2U + +#define GRSPW2_DMACTRL_TE 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPW2DMAMAXLEN \ + * DMA RX maximum length, channel 1 (DMAMAXLEN) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPW2_DMAMAXLEN_RXMAXLEN_SHIFT 2 +#define GRSPW2_DMAMAXLEN_RXMAXLEN_MASK 0x1fffffcU +#define GRSPW2_DMAMAXLEN_RXMAXLEN_GET( _reg ) \ + ( ( ( _reg ) >> 2 ) & 0x7fffffU ) +#define GRSPW2_DMAMAXLEN_RXMAXLEN( _val ) ( ( _val ) << 2 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPW2DMATXDESC \ + * DMA transmitter descriptor table address, channel 1 (DMATXDESC) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPW2_DMATXDESC_DESCBASEADDR_SHIFT 10 +#define GRSPW2_DMATXDESC_DESCBASEADDR_MASK 0xfffffc00U +#define GRSPW2_DMATXDESC_DESCBASEADDR_GET( _reg ) \ + ( ( ( _reg ) >> 10 ) & 0x3fffffU ) +#define GRSPW2_DMATXDESC_DESCBASEADDR( _val ) ( ( _val ) << 10 ) + +#define GRSPW2_DMATXDESC_DESCSEL_SHIFT 4 +#define GRSPW2_DMATXDESC_DESCSEL_MASK 0x3f0U +#define GRSPW2_DMATXDESC_DESCSEL_GET( _reg ) \ + ( ( ( _reg ) >> 4 ) & 0x3fU ) +#define GRSPW2_DMATXDESC_DESCSEL( _val ) ( ( _val ) << 4 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPW2DMARXDESC \ + * DMA receiver descriptor table address, channel 1 (DMARXDESC) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPW2_DMARXDESC_DESCBASEADDR_SHIFT 10 +#define GRSPW2_DMARXDESC_DESCBASEADDR_MASK 0xfffffc00U +#define GRSPW2_DMARXDESC_DESCBASEADDR_GET( _reg ) \ + ( ( ( _reg ) >> 10 ) & 0x3fffffU ) +#define GRSPW2_DMARXDESC_DESCBASEADDR( _val ) ( ( _val ) << 10 ) + +#define GRSPW2_DMARXDESC_DESCSEL_SHIFT 3 +#define GRSPW2_DMARXDESC_DESCSEL_MASK 0x3f8U +#define GRSPW2_DMARXDESC_DESCSEL_GET( _reg ) \ + ( ( ( _reg ) >> 3 ) & 0x7fU ) +#define GRSPW2_DMARXDESC_DESCSEL( _val ) ( ( _val ) << 3 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPW2DMAADDR DMA address, channel 1 (DMAADDR) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPW2_DMAADDR_MASK_SHIFT 8 +#define GRSPW2_DMAADDR_MASK_MASK 0xff00U +#define GRSPW2_DMAADDR_MASK_GET( _reg ) \ + ( ( ( _reg ) >> 8 ) & 0xffU ) +#define GRSPW2_DMAADDR_MASK( _val ) ( ( _val ) << 8 ) + +#define GRSPW2_DMAADDR_ADDR_SHIFT 0 +#define GRSPW2_DMAADDR_ADDR_MASK 0xffU +#define GRSPW2_DMAADDR_ADDR_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffU ) +#define GRSPW2_DMAADDR_ADDR( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @brief This structure defines the GRSPW2 register block memory map. + */ +typedef struct grspw2 { + /** + * @brief See @ref RTEMSDeviceGRSPW2CTRL. + */ + uint32_t ctrl; + + /** + * @brief See @ref RTEMSDeviceGRSPW2STS. + */ + uint32_t sts; + + /** + * @brief See @ref RTEMSDeviceGRSPW2DEFADDR. + */ + uint32_t defaddr; + + /** + * @brief See @ref RTEMSDeviceGRSPW2CLKDIV. + */ + uint32_t clkdiv; + + /** + * @brief See @ref RTEMSDeviceGRSPW2DKEY. + */ + uint32_t dkey; + + /** + * @brief See @ref RTEMSDeviceGRSPW2TC. + */ + uint32_t tc; + + uint32_t reserved_18_20[ 2 ]; + + /** + * @brief See @ref RTEMSDeviceGRSPW2DMACTRL. + */ + uint32_t dmactrl; + + /** + * @brief See @ref RTEMSDeviceGRSPW2DMAMAXLEN. + */ + uint32_t dmamaxlen; + + /** + * @brief See @ref RTEMSDeviceGRSPW2DMATXDESC. + */ + uint32_t dmatxdesc; + + /** + * @brief See @ref RTEMSDeviceGRSPW2DMARXDESC. + */ + uint32_t dmarxdesc; + + /** + * @brief See @ref RTEMSDeviceGRSPW2DMAADDR. + */ + uint32_t dmaaddr; +} grspw2; + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GRLIB_GRSPW2_REGS_H */ diff --git a/bsps/include/grlib/grspwrouter-regs.h b/bsps/include/grlib/grspwrouter-regs.h new file mode 100644 index 0000000000..68061e9f26 --- /dev/null +++ b/bsps/include/grlib/grspwrouter-regs.h @@ -0,0 +1,701 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSDeviceGRSPWROUTER + * + * @brief This header file defines the GRSPWROUTER register block interface. + */ + +/* + * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file is part of the RTEMS quality process and was automatically + * generated. If you find something that needs to be fixed or + * worded better please post a report or patch to an RTEMS mailing list + * or raise a bug report: + * + * https://www.rtems.org/bugs.html + * + * For information on updating and regenerating please refer to the How-To + * section in the Software Requirements Engineering chapter of the + * RTEMS Software Engineering manual. The manual is provided as a part of + * a release. For development sources please refer to the online + * documentation at: + * + * https://docs.rtems.org + */ + +/* Generated from spec:/dev/grlib/if/grspwrouter-header */ + +#ifndef _GRLIB_GRSPWROUTER_REGS_H +#define _GRLIB_GRSPWROUTER_REGS_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Generated from spec:/dev/grlib/if/grspwrouter */ + +/** + * @defgroup RTEMSDeviceGRSPWROUTER GRSPWROUTER + * + * @ingroup RTEMSDeviceGRLIB + * + * @brief This group contains the GRSPWROUTER interfaces. + * + * @{ + */ + +/** + * @defgroup RTEMSDeviceGRSPWROUTERAMBACTRL AMBA port Control (AMBACTRL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPWROUTER_AMBACTRL_RA 0x80000000U + +#define GRSPWROUTER_AMBACTRL_RX 0x40000000U + +#define GRSPWROUTER_AMBACTRL_RC 0x20000000U + +#define GRSPWROUTER_AMBACTRL_NCH_SHIFT 27 +#define GRSPWROUTER_AMBACTRL_NCH_MASK 0x18000000U +#define GRSPWROUTER_AMBACTRL_NCH_GET( _reg ) \ + ( ( ( _reg ) >> 27 ) & 0x3U ) +#define GRSPWROUTER_AMBACTRL_NCH( _val ) ( ( _val ) << 27 ) + +#define GRSPWROUTER_AMBACTRL_DI 0x1000000U + +#define GRSPWROUTER_AMBACTRL_ME 0x800000U + +#define GRSPWROUTER_AMBACTRL_RD 0x20000U + +#define GRSPWROUTER_AMBACTRL_RE 0x10000U + +#define GRSPWROUTER_AMBACTRL_TQ 0x100U + +#define GRSPWROUTER_AMBACTRL_RS 0x40U + +#define GRSPWROUTER_AMBACTRL_PM 0x20U + +#define GRSPWROUTER_AMBACTRL_TI 0x10U + +#define GRSPWROUTER_AMBACTRL_IE 0x8U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPWROUTERAMBASTS AMBA port Status (AMBASTS) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPWROUTER_AMBASTS_NIRQ_SHIFT 28 +#define GRSPWROUTER_AMBASTS_NIRQ_MASK 0x70000000U +#define GRSPWROUTER_AMBASTS_NIRQ_GET( _reg ) \ + ( ( ( _reg ) >> 28 ) & 0x7U ) +#define GRSPWROUTER_AMBASTS_NIRQ( _val ) ( ( _val ) << 28 ) + +#define GRSPWROUTER_AMBASTS_NRXD_SHIFT 26 +#define GRSPWROUTER_AMBASTS_NRXD_MASK 0xc000000U +#define GRSPWROUTER_AMBASTS_NRXD_GET( _reg ) \ + ( ( ( _reg ) >> 26 ) & 0x3U ) +#define GRSPWROUTER_AMBASTS_NRXD( _val ) ( ( _val ) << 26 ) + +#define GRSPWROUTER_AMBASTS_NTXD_SHIFT 24 +#define GRSPWROUTER_AMBASTS_NTXD_MASK 0x3000000U +#define GRSPWROUTER_AMBASTS_NTXD_GET( _reg ) \ + ( ( ( _reg ) >> 24 ) & 0x3U ) +#define GRSPWROUTER_AMBASTS_NTXD( _val ) ( ( _val ) << 24 ) + +#define GRSPWROUTER_AMBASTS_ME 0x1000U + +#define GRSPWROUTER_AMBASTS_EE 0x100U + +#define GRSPWROUTER_AMBASTS_IA 0x80U + +#define GRSPWROUTER_AMBASTS_TO 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPWROUTERAMBADEFADDR \ + * AMBA port Default address (AMBADEFADDR) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPWROUTER_AMBADEFADDR_DEFMASK_SHIFT 8 +#define GRSPWROUTER_AMBADEFADDR_DEFMASK_MASK 0xff00U +#define GRSPWROUTER_AMBADEFADDR_DEFMASK_GET( _reg ) \ + ( ( ( _reg ) >> 8 ) & 0xffU ) +#define GRSPWROUTER_AMBADEFADDR_DEFMASK( _val ) ( ( _val ) << 8 ) + +#define GRSPWROUTER_AMBADEFADDR_DEFADDR_SHIFT 0 +#define GRSPWROUTER_AMBADEFADDR_DEFADDR_MASK 0xffU +#define GRSPWROUTER_AMBADEFADDR_DEFADDR_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffU ) +#define GRSPWROUTER_AMBADEFADDR_DEFADDR( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPWROUTERAMBADKEY \ + * AMBA port Destination key (AMBADKEY) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPWROUTER_AMBADKEY_DESTKEY_SHIFT 0 +#define GRSPWROUTER_AMBADKEY_DESTKEY_MASK 0xffU +#define GRSPWROUTER_AMBADKEY_DESTKEY_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffU ) +#define GRSPWROUTER_AMBADKEY_DESTKEY( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPWROUTERAMBATC AMBA port Time-code (AMBATC) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPWROUTER_AMBATC_TCMSK_SHIFT 24 +#define GRSPWROUTER_AMBATC_TCMSK_MASK 0xff000000U +#define GRSPWROUTER_AMBATC_TCMSK_GET( _reg ) \ + ( ( ( _reg ) >> 24 ) & 0xffU ) +#define GRSPWROUTER_AMBATC_TCMSK( _val ) ( ( _val ) << 24 ) + +#define GRSPWROUTER_AMBATC_TCVAL_SHIFT 16 +#define GRSPWROUTER_AMBATC_TCVAL_MASK 0xff0000U +#define GRSPWROUTER_AMBATC_TCVAL_GET( _reg ) \ + ( ( ( _reg ) >> 16 ) & 0xffU ) +#define GRSPWROUTER_AMBATC_TCVAL( _val ) ( ( _val ) << 16 ) + +#define GRSPWROUTER_AMBATC_TCTRL_SHIFT 6 +#define GRSPWROUTER_AMBATC_TCTRL_MASK 0xc0U +#define GRSPWROUTER_AMBATC_TCTRL_GET( _reg ) \ + ( ( ( _reg ) >> 6 ) & 0x3U ) +#define GRSPWROUTER_AMBATC_TCTRL( _val ) ( ( _val ) << 6 ) + +#define GRSPWROUTER_AMBATC_TIMECNT_SHIFT 0 +#define GRSPWROUTER_AMBATC_TIMECNT_MASK 0x3fU +#define GRSPWROUTER_AMBATC_TIMECNT_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0x3fU ) +#define GRSPWROUTER_AMBATC_TIMECNT( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPWROUTERAMBADMACTRL \ + * AMBA port DMA control/status (AMBADMACTRL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPWROUTER_AMBADMACTRL_INTNUM_SHIFT 26 +#define GRSPWROUTER_AMBADMACTRL_INTNUM_MASK 0xfc000000U +#define GRSPWROUTER_AMBADMACTRL_INTNUM_GET( _reg ) \ + ( ( ( _reg ) >> 26 ) & 0x3fU ) +#define GRSPWROUTER_AMBADMACTRL_INTNUM( _val ) ( ( _val ) << 26 ) + +#define GRSPWROUTER_AMBADMACTRL_EP 0x800000U + +#define GRSPWROUTER_AMBADMACTRL_TR 0x400000U + +#define GRSPWROUTER_AMBADMACTRL_IE 0x200000U + +#define GRSPWROUTER_AMBADMACTRL_IT 0x100000U + +#define GRSPWROUTER_AMBADMACTRL_RP 0x80000U + +#define GRSPWROUTER_AMBADMACTRL_TP 0x40000U + +#define GRSPWROUTER_AMBADMACTRL_SP 0x8000U + +#define GRSPWROUTER_AMBADMACTRL_SA 0x4000U + +#define GRSPWROUTER_AMBADMACTRL_EN 0x2000U + +#define GRSPWROUTER_AMBADMACTRL_NS 0x1000U + +#define GRSPWROUTER_AMBADMACTRL_RD 0x800U + +#define GRSPWROUTER_AMBADMACTRL_RX 0x400U + +#define GRSPWROUTER_AMBADMACTRL_AT 0x200U + +#define GRSPWROUTER_AMBADMACTRL_RA 0x100U + +#define GRSPWROUTER_AMBADMACTRL_TA 0x80U + +#define GRSPWROUTER_AMBADMACTRL_PR 0x40U + +#define GRSPWROUTER_AMBADMACTRL_PS 0x20U + +#define GRSPWROUTER_AMBADMACTRL_AI 0x10U + +#define GRSPWROUTER_AMBADMACTRL_RI 0x8U + +#define GRSPWROUTER_AMBADMACTRL_TI 0x4U + +#define GRSPWROUTER_AMBADMACTRL_RE 0x2U + +#define GRSPWROUTER_AMBADMACTRL_TE 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPWROUTERAMBADMAMAXLEN \ + * AMBA port DMA RX maximum length (AMBADMAMAXLEN) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPWROUTER_AMBADMAMAXLEN_RXMAXLEN_SHIFT 2 +#define GRSPWROUTER_AMBADMAMAXLEN_RXMAXLEN_MASK 0x1fffffcU +#define GRSPWROUTER_AMBADMAMAXLEN_RXMAXLEN_GET( _reg ) \ + ( ( ( _reg ) >> 2 ) & 0x7fffffU ) +#define GRSPWROUTER_AMBADMAMAXLEN_RXMAXLEN( _val ) ( ( _val ) << 2 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPWROUTERAMBADMATXDESC \ + * AMBA port DMA transmit descriptor table address (AMBADMATXDESC) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPWROUTER_AMBADMATXDESC_DESCBASEADDR_SHIFT 10 +#define GRSPWROUTER_AMBADMATXDESC_DESCBASEADDR_MASK 0xfffffc00U +#define GRSPWROUTER_AMBADMATXDESC_DESCBASEADDR_GET( _reg ) \ + ( ( ( _reg ) >> 10 ) & 0x3fffffU ) +#define GRSPWROUTER_AMBADMATXDESC_DESCBASEADDR( _val ) ( ( _val ) << 10 ) + +#define GRSPWROUTER_AMBADMATXDESC_DESCSEL_SHIFT 4 +#define GRSPWROUTER_AMBADMATXDESC_DESCSEL_MASK 0x3f0U +#define GRSPWROUTER_AMBADMATXDESC_DESCSEL_GET( _reg ) \ + ( ( ( _reg ) >> 4 ) & 0x3fU ) +#define GRSPWROUTER_AMBADMATXDESC_DESCSEL( _val ) ( ( _val ) << 4 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPWROUTERAMBADMARXDESC \ + * AMBA port DMA receive descriptor table address (AMBADMARXDESC) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPWROUTER_AMBADMARXDESC_DESCBASEADDR_SHIFT 10 +#define GRSPWROUTER_AMBADMARXDESC_DESCBASEADDR_MASK 0xfffffc00U +#define GRSPWROUTER_AMBADMARXDESC_DESCBASEADDR_GET( _reg ) \ + ( ( ( _reg ) >> 10 ) & 0x3fffffU ) +#define GRSPWROUTER_AMBADMARXDESC_DESCBASEADDR( _val ) ( ( _val ) << 10 ) + +#define GRSPWROUTER_AMBADMARXDESC_DESCSEL_SHIFT 3 +#define GRSPWROUTER_AMBADMARXDESC_DESCSEL_MASK 0x3f8U +#define GRSPWROUTER_AMBADMARXDESC_DESCSEL_GET( _reg ) \ + ( ( ( _reg ) >> 3 ) & 0x7fU ) +#define GRSPWROUTER_AMBADMARXDESC_DESCSEL( _val ) ( ( _val ) << 3 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPWROUTERAMBADMAADDR \ + * AMBA port DMA address (AMBADMAADDR) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPWROUTER_AMBADMAADDR_MASK_SHIFT 8 +#define GRSPWROUTER_AMBADMAADDR_MASK_MASK 0xff00U +#define GRSPWROUTER_AMBADMAADDR_MASK_GET( _reg ) \ + ( ( ( _reg ) >> 8 ) & 0xffU ) +#define GRSPWROUTER_AMBADMAADDR_MASK( _val ) ( ( _val ) << 8 ) + +#define GRSPWROUTER_AMBADMAADDR_ADDR_SHIFT 0 +#define GRSPWROUTER_AMBADMAADDR_ADDR_MASK 0xffU +#define GRSPWROUTER_AMBADMAADDR_ADDR_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffU ) +#define GRSPWROUTER_AMBADMAADDR_ADDR( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPWROUTERAMBAINTCTRL \ + * AMBA port Distributed interrupt control (AMBAINTCTRL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPWROUTER_AMBAINTCTRL_INTNUM_SHIFT 26 +#define GRSPWROUTER_AMBAINTCTRL_INTNUM_MASK 0xfc000000U +#define GRSPWROUTER_AMBAINTCTRL_INTNUM_GET( _reg ) \ + ( ( ( _reg ) >> 26 ) & 0x3fU ) +#define GRSPWROUTER_AMBAINTCTRL_INTNUM( _val ) ( ( _val ) << 26 ) + +#define GRSPWROUTER_AMBAINTCTRL_EE 0x1000000U + +#define GRSPWROUTER_AMBAINTCTRL_IA 0x800000U + +#define GRSPWROUTER_AMBAINTCTRL_TQ 0x100000U + +#define GRSPWROUTER_AMBAINTCTRL_AQ 0x80000U + +#define GRSPWROUTER_AMBAINTCTRL_IQ 0x40000U + +#define GRSPWROUTER_AMBAINTCTRL_AA 0x8000U + +#define GRSPWROUTER_AMBAINTCTRL_AT 0x4000U + +#define GRSPWROUTER_AMBAINTCTRL_IT 0x2000U + +#define GRSPWROUTER_AMBAINTCTRL_ID 0x80U + +#define GRSPWROUTER_AMBAINTCTRL_II 0x40U + +#define GRSPWROUTER_AMBAINTCTRL_TXINT_SHIFT 0 +#define GRSPWROUTER_AMBAINTCTRL_TXINT_MASK 0x3fU +#define GRSPWROUTER_AMBAINTCTRL_TXINT_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0x3fU ) +#define GRSPWROUTER_AMBAINTCTRL_TXINT( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPWROUTERAMBAINTRX \ + * AMBA port Interrupt receive (AMBAINTRX) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPWROUTER_AMBAINTRX_RXIRQ_SHIFT 0 +#define GRSPWROUTER_AMBAINTRX_RXIRQ_MASK 0xffffffffU +#define GRSPWROUTER_AMBAINTRX_RXIRQ_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define GRSPWROUTER_AMBAINTRX_RXIRQ( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPWROUTERAMBAACKRX \ + * AMBA port Interrupt acknowledgement / extended interrupt receive (AMBAACKRX) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPWROUTER_AMBAACKRX_RXACK_SHIFT 0 +#define GRSPWROUTER_AMBAACKRX_RXACK_MASK 0xffffffffU +#define GRSPWROUTER_AMBAACKRX_RXACK_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define GRSPWROUTER_AMBAACKRX_RXACK( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPWROUTERAMBAINTTO0 \ + * AMBA port Interrupt timeout, interrupt 0-31 (AMBAINTTO0) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPWROUTER_AMBAINTTO0_INTTO_SHIFT 0 +#define GRSPWROUTER_AMBAINTTO0_INTTO_MASK 0xffffffffU +#define GRSPWROUTER_AMBAINTTO0_INTTO_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define GRSPWROUTER_AMBAINTTO0_INTTO( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPWROUTERAMBAINTTO1 \ + * AMBA port Interrupt timeout, interrupt 32-63 (AMBAINTTO1) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPWROUTER_AMBAINTTO1_INTTO_SHIFT 0 +#define GRSPWROUTER_AMBAINTTO1_INTTO_MASK 0xffffffffU +#define GRSPWROUTER_AMBAINTTO1_INTTO_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define GRSPWROUTER_AMBAINTTO1_INTTO( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPWROUTERAMBAINTMSK0 \ + * AMBA port Interrupt mask, interrupt 0-31 (AMBAINTMSK0) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPWROUTER_AMBAINTMSK0_MASK_SHIFT 0 +#define GRSPWROUTER_AMBAINTMSK0_MASK_MASK 0xffffffffU +#define GRSPWROUTER_AMBAINTMSK0_MASK_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define GRSPWROUTER_AMBAINTMSK0_MASK( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRSPWROUTERAMBAINTMSK1 \ + * AMBA port Interrupt mask, interrupt 32-63 (AMBAINTMSK1) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GRSPWROUTER_AMBAINTMSK1_MASK_SHIFT 0 +#define GRSPWROUTER_AMBAINTMSK1_MASK_MASK 0xffffffffU +#define GRSPWROUTER_AMBAINTMSK1_MASK_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define GRSPWROUTER_AMBAINTMSK1_MASK( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @brief This structure defines the GRSPWROUTER register block memory map. + */ +typedef struct grspwrouter { + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERAMBACTRL. + */ + uint32_t ambactrl; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERAMBASTS. + */ + uint32_t ambasts; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERAMBADEFADDR. + */ + uint32_t ambadefaddr; + + uint32_t reserved_c_10; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERAMBADKEY. + */ + uint32_t ambadkey; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERAMBATC. + */ + uint32_t ambatc; + + uint32_t reserved_18_20[ 2 ]; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERAMBADMACTRL. + */ + uint32_t ambadmactrl_0; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERAMBADMAMAXLEN. + */ + uint32_t ambadmamaxlen_0; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERAMBADMATXDESC. + */ + uint32_t ambadmatxdesc_0; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERAMBADMARXDESC. + */ + uint32_t ambadmarxdesc_0; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERAMBADMAADDR. + */ + uint32_t ambadmaaddr_0; + + uint32_t reserved_34_40[ 3 ]; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERAMBADMACTRL. + */ + uint32_t ambadmactrl_1; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERAMBADMAMAXLEN. + */ + uint32_t ambadmamaxlen_1; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERAMBADMATXDESC. + */ + uint32_t ambadmatxdesc_1; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERAMBADMARXDESC. + */ + uint32_t ambadmarxdesc_1; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERAMBADMAADDR. + */ + uint32_t ambadmaaddr_1; + + uint32_t reserved_54_60[ 3 ]; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERAMBADMACTRL. + */ + uint32_t ambadmactrl_2; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERAMBADMAMAXLEN. + */ + uint32_t ambadmamaxlen_2; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERAMBADMATXDESC. + */ + uint32_t ambadmatxdesc_2; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERAMBADMARXDESC. + */ + uint32_t ambadmarxdesc_2; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERAMBADMAADDR. + */ + uint32_t ambadmaaddr_2; + + uint32_t reserved_74_80[ 3 ]; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERAMBADMACTRL. + */ + uint32_t ambadmactrl_3; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERAMBADMAMAXLEN. + */ + uint32_t ambadmamaxlen_3; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERAMBADMATXDESC. + */ + uint32_t ambadmatxdesc_3; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERAMBADMARXDESC. + */ + uint32_t ambadmarxdesc_3; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERAMBADMAADDR. + */ + uint32_t ambadmaaddr_3; + + uint32_t reserved_94_a0[ 3 ]; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERAMBAINTCTRL. + */ + uint32_t ambaintctrl; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERAMBAINTRX. + */ + uint32_t ambaintrx; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERAMBAACKRX. + */ + uint32_t ambaackrx; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERAMBAINTTO0. + */ + uint32_t ambaintto0; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERAMBAINTTO1. + */ + uint32_t ambaintto1; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERAMBAINTMSK0. + */ + uint32_t ambaintmsk0; + + /** + * @brief See @ref RTEMSDeviceGRSPWROUTERAMBAINTMSK1. + */ + uint32_t ambaintmsk1; +} grspwrouter; + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GRLIB_GRSPWROUTER_REGS_H */ diff --git a/bsps/include/grlib/irqamp-regs.h b/bsps/include/grlib/irqamp-regs.h new file mode 100644 index 0000000000..082d08a870 --- /dev/null +++ b/bsps/include/grlib/irqamp-regs.h @@ -0,0 +1,636 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSDeviceGRLIBIRQAMP + * + * @brief This header file defines the IRQAMP register block interface. + */ + +/* + * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file is part of the RTEMS quality process and was automatically + * generated. If you find something that needs to be fixed or + * worded better please post a report or patch to an RTEMS mailing list + * or raise a bug report: + * + * https://www.rtems.org/bugs.html + * + * For information on updating and regenerating please refer to the How-To + * section in the Software Requirements Engineering chapter of the + * RTEMS Software Engineering manual. The manual is provided as a part of + * a release. For development sources please refer to the online + * documentation at: + * + * https://docs.rtems.org + */ + +/* Generated from spec:/dev/grlib/if/irqamp-header */ + +#ifndef _GRLIB_IRQAMP_REGS_H +#define _GRLIB_IRQAMP_REGS_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Generated from spec:/dev/grlib/if/irqamp-timestamp */ + +/** + * @defgroup RTEMSDeviceGRLIBIRQAMPTimestamp IRQ(A)MP Timestamp + * + * @ingroup RTEMSDeviceGRLIBIRQAMP + * + * @brief This group contains the IRQ(A)MP Timestamp interfaces. + * + * @{ + */ + +/** + * @defgroup RTEMSDeviceGRLIBIRQAMPTimestampITCNT \ + * Interrupt timestamp counter n register (ITCNT) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define IRQAMP_ITCNT_TCNT_SHIFT 0 +#define IRQAMP_ITCNT_TCNT_MASK 0xffffffffU +#define IRQAMP_ITCNT_TCNT_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define IRQAMP_ITCNT_TCNT( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBIRQAMPTimestampITSTMPC \ + * Interrupt timestamp n control register (ITSTMPC) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define IRQAMP_ITSTMPC_TSTAMP_SHIFT 27 +#define IRQAMP_ITSTMPC_TSTAMP_MASK 0xf8000000U +#define IRQAMP_ITSTMPC_TSTAMP_GET( _reg ) \ + ( ( ( _reg ) >> 27 ) & 0x1fU ) +#define IRQAMP_ITSTMPC_TSTAMP( _val ) ( ( _val ) << 27 ) + +#define IRQAMP_ITSTMPC_S1 0x4000000U + +#define IRQAMP_ITSTMPC_S2 0x2000000U + +#define IRQAMP_ITSTMPC_KS 0x20U + +#define IRQAMP_ITSTMPC_TSISEL_SHIFT 0 +#define IRQAMP_ITSTMPC_TSISEL_MASK 0x1fU +#define IRQAMP_ITSTMPC_TSISEL_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0x1fU ) +#define IRQAMP_ITSTMPC_TSISEL( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBIRQAMPTimestampITSTMPAS \ + * Interrupt Assertion Timestamp n register (ITSTMPAS) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define IRQAMP_ITSTMPAS_TASSERTION_SHIFT 0 +#define IRQAMP_ITSTMPAS_TASSERTION_MASK 0xffffffffU +#define IRQAMP_ITSTMPAS_TASSERTION_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define IRQAMP_ITSTMPAS_TASSERTION( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBIRQAMPTimestampITSTMPAC \ + * Interrupt Acknowledge Timestamp n register (ITSTMPAC) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define IRQAMP_ITSTMPAC_TACKNOWLEDGE_SHIFT 0 +#define IRQAMP_ITSTMPAC_TACKNOWLEDGE_MASK 0xffffffffU +#define IRQAMP_ITSTMPAC_TACKNOWLEDGE_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define IRQAMP_ITSTMPAC_TACKNOWLEDGE( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @brief This structure defines the IRQ(A)MP Timestamp register block memory + * map. + */ +typedef struct irqamp_timestamp { + /** + * @brief See @ref RTEMSDeviceGRLIBIRQAMPTimestampITCNT. + */ + uint32_t itcnt; + + /** + * @brief See @ref RTEMSDeviceGRLIBIRQAMPTimestampITSTMPC. + */ + uint32_t itstmpc; + + /** + * @brief See @ref RTEMSDeviceGRLIBIRQAMPTimestampITSTMPAS. + */ + uint32_t itstmpas; + + /** + * @brief See @ref RTEMSDeviceGRLIBIRQAMPTimestampITSTMPAC. + */ + uint32_t itstmpac; +} irqamp_timestamp; + +/** @} */ + +/* Generated from spec:/dev/grlib/if/irqamp */ + +/** + * @defgroup RTEMSDeviceGRLIBIRQAMP IRQ(A)MP + * + * @ingroup RTEMSDeviceGRLIB + * + * @brief This group contains the IRQ(A)MP interfaces. + * + * @{ + */ + +/** + * @defgroup RTEMSDeviceGRLIBIRQAMPILEVEL Interrupt level register (ILEVEL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define IRQAMP_ILEVEL_IL_15_1_SHIFT 1 +#define IRQAMP_ILEVEL_IL_15_1_MASK 0xfffeU +#define IRQAMP_ILEVEL_IL_15_1_GET( _reg ) \ + ( ( ( _reg ) >> 1 ) & 0x7fffU ) +#define IRQAMP_ILEVEL_IL_15_1( _val ) ( ( _val ) << 1 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBIRQAMPIPEND Interrupt pending register (IPEND) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define IRQAMP_IPEND_EIP_31_16_SHIFT 16 +#define IRQAMP_IPEND_EIP_31_16_MASK 0xffff0000U +#define IRQAMP_IPEND_EIP_31_16_GET( _reg ) \ + ( ( ( _reg ) >> 16 ) & 0xffffU ) +#define IRQAMP_IPEND_EIP_31_16( _val ) ( ( _val ) << 16 ) + +#define IRQAMP_IPEND_IP_15_1_SHIFT 1 +#define IRQAMP_IPEND_IP_15_1_MASK 0xfffeU +#define IRQAMP_IPEND_IP_15_1_GET( _reg ) \ + ( ( ( _reg ) >> 1 ) & 0x7fffU ) +#define IRQAMP_IPEND_IP_15_1( _val ) ( ( _val ) << 1 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBIRQAMPIFORCE0 \ + * Interrupt force register for processor 0 (IFORCE0) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define IRQAMP_IFORCE0_IF_15_1_SHIFT 1 +#define IRQAMP_IFORCE0_IF_15_1_MASK 0xfffeU +#define IRQAMP_IFORCE0_IF_15_1_GET( _reg ) \ + ( ( ( _reg ) >> 1 ) & 0x7fffU ) +#define IRQAMP_IFORCE0_IF_15_1( _val ) ( ( _val ) << 1 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBIRQAMPICLEAR Interrupt clear register (ICLEAR) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define IRQAMP_ICLEAR_EIC_31_16_SHIFT 16 +#define IRQAMP_ICLEAR_EIC_31_16_MASK 0xffff0000U +#define IRQAMP_ICLEAR_EIC_31_16_GET( _reg ) \ + ( ( ( _reg ) >> 16 ) & 0xffffU ) +#define IRQAMP_ICLEAR_EIC_31_16( _val ) ( ( _val ) << 16 ) + +#define IRQAMP_ICLEAR_IC_15_1_SHIFT 1 +#define IRQAMP_ICLEAR_IC_15_1_MASK 0xfffeU +#define IRQAMP_ICLEAR_IC_15_1_GET( _reg ) \ + ( ( ( _reg ) >> 1 ) & 0x7fffU ) +#define IRQAMP_ICLEAR_IC_15_1( _val ) ( ( _val ) << 1 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBIRQAMPMPSTAT \ + * Multiprocessor status register (MPSTAT) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define IRQAMP_MPSTAT_NCPU_SHIFT 28 +#define IRQAMP_MPSTAT_NCPU_MASK 0xf0000000U +#define IRQAMP_MPSTAT_NCPU_GET( _reg ) \ + ( ( ( _reg ) >> 28 ) & 0xfU ) +#define IRQAMP_MPSTAT_NCPU( _val ) ( ( _val ) << 28 ) + +#define IRQAMP_MPSTAT_BA 0x8000000U + +#define IRQAMP_MPSTAT_ER 0x4000000U + +#define IRQAMP_MPSTAT_EIRQ_SHIFT 16 +#define IRQAMP_MPSTAT_EIRQ_MASK 0xf0000U +#define IRQAMP_MPSTAT_EIRQ_GET( _reg ) \ + ( ( ( _reg ) >> 16 ) & 0xfU ) +#define IRQAMP_MPSTAT_EIRQ( _val ) ( ( _val ) << 16 ) + +#define IRQAMP_MPSTAT_STATUS_SHIFT 0 +#define IRQAMP_MPSTAT_STATUS_MASK 0xfU +#define IRQAMP_MPSTAT_STATUS_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xfU ) +#define IRQAMP_MPSTAT_STATUS( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBIRQAMPBRDCST Broadcast register (BRDCST) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define IRQAMP_BRDCST_BM15_1_SHIFT 1 +#define IRQAMP_BRDCST_BM15_1_MASK 0xfffeU +#define IRQAMP_BRDCST_BM15_1_GET( _reg ) \ + ( ( ( _reg ) >> 1 ) & 0x7fffU ) +#define IRQAMP_BRDCST_BM15_1( _val ) ( ( _val ) << 1 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBIRQAMPERRSTAT Error Mode Status Register (ERRSTAT) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define IRQAMP_ERRSTAT_ERRMODE_3_0_SHIFT 0 +#define IRQAMP_ERRSTAT_ERRMODE_3_0_MASK 0xfU +#define IRQAMP_ERRSTAT_ERRMODE_3_0_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xfU ) +#define IRQAMP_ERRSTAT_ERRMODE_3_0( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBIRQAMPWDOGCTRL \ + * Watchdog control register (WDOGCTRL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define IRQAMP_WDOGCTRL_NWDOG_SHIFT 27 +#define IRQAMP_WDOGCTRL_NWDOG_MASK 0xf8000000U +#define IRQAMP_WDOGCTRL_NWDOG_GET( _reg ) \ + ( ( ( _reg ) >> 27 ) & 0x1fU ) +#define IRQAMP_WDOGCTRL_NWDOG( _val ) ( ( _val ) << 27 ) + +#define IRQAMP_WDOGCTRL_WDOGIRQ_SHIFT 16 +#define IRQAMP_WDOGCTRL_WDOGIRQ_MASK 0xf0000U +#define IRQAMP_WDOGCTRL_WDOGIRQ_GET( _reg ) \ + ( ( ( _reg ) >> 16 ) & 0xfU ) +#define IRQAMP_WDOGCTRL_WDOGIRQ( _val ) ( ( _val ) << 16 ) + +#define IRQAMP_WDOGCTRL_WDOGMSK_SHIFT 0 +#define IRQAMP_WDOGCTRL_WDOGMSK_MASK 0xfU +#define IRQAMP_WDOGCTRL_WDOGMSK_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xfU ) +#define IRQAMP_WDOGCTRL_WDOGMSK( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBIRQAMPASMPCTRL \ + * Asymmetric multiprocessing control register (ASMPCTRL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define IRQAMP_ASMPCTRL_NCTRL_SHIFT 28 +#define IRQAMP_ASMPCTRL_NCTRL_MASK 0xf0000000U +#define IRQAMP_ASMPCTRL_NCTRL_GET( _reg ) \ + ( ( ( _reg ) >> 28 ) & 0xfU ) +#define IRQAMP_ASMPCTRL_NCTRL( _val ) ( ( _val ) << 28 ) + +#define IRQAMP_ASMPCTRL_ICF 0x2U + +#define IRQAMP_ASMPCTRL_L 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBIRQAMPICSELR \ + * Interrupt controller select register (ICSELR) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define IRQAMP_ICSELR_ICSEL0_SHIFT 28 +#define IRQAMP_ICSELR_ICSEL0_MASK 0xf0000000U +#define IRQAMP_ICSELR_ICSEL0_GET( _reg ) \ + ( ( ( _reg ) >> 28 ) & 0xfU ) +#define IRQAMP_ICSELR_ICSEL0( _val ) ( ( _val ) << 28 ) + +#define IRQAMP_ICSELR_ICSEL1_SHIFT 24 +#define IRQAMP_ICSELR_ICSEL1_MASK 0xf000000U +#define IRQAMP_ICSELR_ICSEL1_GET( _reg ) \ + ( ( ( _reg ) >> 24 ) & 0xfU ) +#define IRQAMP_ICSELR_ICSEL1( _val ) ( ( _val ) << 24 ) + +#define IRQAMP_ICSELR_ICSEL2_SHIFT 20 +#define IRQAMP_ICSELR_ICSEL2_MASK 0xf00000U +#define IRQAMP_ICSELR_ICSEL2_GET( _reg ) \ + ( ( ( _reg ) >> 20 ) & 0xfU ) +#define IRQAMP_ICSELR_ICSEL2( _val ) ( ( _val ) << 20 ) + +#define IRQAMP_ICSELR_ICSEL3_SHIFT 16 +#define IRQAMP_ICSELR_ICSEL3_MASK 0xf0000U +#define IRQAMP_ICSELR_ICSEL3_GET( _reg ) \ + ( ( ( _reg ) >> 16 ) & 0xfU ) +#define IRQAMP_ICSELR_ICSEL3( _val ) ( ( _val ) << 16 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBIRQAMPPIMASK \ + * Processor n interrupt mask register (PIMASK) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define IRQAMP_PIMASK_EIM_31_16_SHIFT 16 +#define IRQAMP_PIMASK_EIM_31_16_MASK 0xffff0000U +#define IRQAMP_PIMASK_EIM_31_16_GET( _reg ) \ + ( ( ( _reg ) >> 16 ) & 0xffffU ) +#define IRQAMP_PIMASK_EIM_31_16( _val ) ( ( _val ) << 16 ) + +#define IRQAMP_PIMASK_IM15_1_SHIFT 1 +#define IRQAMP_PIMASK_IM15_1_MASK 0xfffeU +#define IRQAMP_PIMASK_IM15_1_GET( _reg ) \ + ( ( ( _reg ) >> 1 ) & 0x7fffU ) +#define IRQAMP_PIMASK_IM15_1( _val ) ( ( _val ) << 1 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBIRQAMPPIFORCE \ + * Processor n interrupt force register (PIFORCE) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define IRQAMP_PIFORCE_FC_15_1_SHIFT 17 +#define IRQAMP_PIFORCE_FC_15_1_MASK 0xfffe0000U +#define IRQAMP_PIFORCE_FC_15_1_GET( _reg ) \ + ( ( ( _reg ) >> 17 ) & 0x7fffU ) +#define IRQAMP_PIFORCE_FC_15_1( _val ) ( ( _val ) << 17 ) + +#define IRQAMP_PIFORCE_IF15_1_SHIFT 1 +#define IRQAMP_PIFORCE_IF15_1_MASK 0xfffeU +#define IRQAMP_PIFORCE_IF15_1_GET( _reg ) \ + ( ( ( _reg ) >> 1 ) & 0x7fffU ) +#define IRQAMP_PIFORCE_IF15_1( _val ) ( ( _val ) << 1 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBIRQAMPPEXTACK \ + * Processor n extended interrupt acknowledge register (PEXTACK) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define IRQAMP_PEXTACK_EID_4_0_SHIFT 0 +#define IRQAMP_PEXTACK_EID_4_0_MASK 0x1fU +#define IRQAMP_PEXTACK_EID_4_0_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0x1fU ) +#define IRQAMP_PEXTACK_EID_4_0( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBIRQAMPBADDR \ + * Processor n Boot Address register (BADDR) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define IRQAMP_BADDR_BOOTADDR_31_3_SHIFT 3 +#define IRQAMP_BADDR_BOOTADDR_31_3_MASK 0xfffffff8U +#define IRQAMP_BADDR_BOOTADDR_31_3_GET( _reg ) \ + ( ( ( _reg ) >> 3 ) & 0x1fffffffU ) +#define IRQAMP_BADDR_BOOTADDR_31_3( _val ) ( ( _val ) << 3 ) + +#define IRQAMP_BADDR_AS 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBIRQAMPIRQMAP Interrupt map register n (IRQMAP) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define IRQAMP_IRQMAP_IRQMAP_4_N_0_SHIFT 24 +#define IRQAMP_IRQMAP_IRQMAP_4_N_0_MASK 0xff000000U +#define IRQAMP_IRQMAP_IRQMAP_4_N_0_GET( _reg ) \ + ( ( ( _reg ) >> 24 ) & 0xffU ) +#define IRQAMP_IRQMAP_IRQMAP_4_N_0( _val ) ( ( _val ) << 24 ) + +#define IRQAMP_IRQMAP_IRQMAP_4_N_1_SHIFT 16 +#define IRQAMP_IRQMAP_IRQMAP_4_N_1_MASK 0xff0000U +#define IRQAMP_IRQMAP_IRQMAP_4_N_1_GET( _reg ) \ + ( ( ( _reg ) >> 16 ) & 0xffU ) +#define IRQAMP_IRQMAP_IRQMAP_4_N_1( _val ) ( ( _val ) << 16 ) + +#define IRQAMP_IRQMAP_IRQMAP_4_N_2_SHIFT 8 +#define IRQAMP_IRQMAP_IRQMAP_4_N_2_MASK 0xff00U +#define IRQAMP_IRQMAP_IRQMAP_4_N_2_GET( _reg ) \ + ( ( ( _reg ) >> 8 ) & 0xffU ) +#define IRQAMP_IRQMAP_IRQMAP_4_N_2( _val ) ( ( _val ) << 8 ) + +#define IRQAMP_IRQMAP_IRQMAP_4_N_3_SHIFT 0 +#define IRQAMP_IRQMAP_IRQMAP_4_N_3_MASK 0xffU +#define IRQAMP_IRQMAP_IRQMAP_4_N_3_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffU ) +#define IRQAMP_IRQMAP_IRQMAP_4_N_3( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @brief This structure defines the IRQ(A)MP register block memory map. + */ +typedef struct irqamp { + /** + * @brief See @ref RTEMSDeviceGRLIBIRQAMPILEVEL. + */ + uint32_t ilevel; + + /** + * @brief See @ref RTEMSDeviceGRLIBIRQAMPIPEND. + */ + uint32_t ipend; + + /** + * @brief See @ref RTEMSDeviceGRLIBIRQAMPIFORCE0. + */ + uint32_t iforce0; + + /** + * @brief See @ref RTEMSDeviceGRLIBIRQAMPICLEAR. + */ + uint32_t iclear; + + /** + * @brief See @ref RTEMSDeviceGRLIBIRQAMPMPSTAT. + */ + uint32_t mpstat; + + /** + * @brief See @ref RTEMSDeviceGRLIBIRQAMPBRDCST. + */ + uint32_t brdcst; + + /** + * @brief See @ref RTEMSDeviceGRLIBIRQAMPERRSTAT. + */ + uint32_t errstat; + + /** + * @brief See @ref RTEMSDeviceGRLIBIRQAMPWDOGCTRL. + */ + uint32_t wdogctrl; + + /** + * @brief See @ref RTEMSDeviceGRLIBIRQAMPASMPCTRL. + */ + uint32_t asmpctrl; + + /** + * @brief See @ref RTEMSDeviceGRLIBIRQAMPICSELR. + */ + uint32_t icselr[ 2 ]; + + uint32_t reserved_2c_40[ 5 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBIRQAMPPIMASK. + */ + uint32_t pimask[ 16 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBIRQAMPPIFORCE. + */ + uint32_t piforce[ 16 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBIRQAMPPEXTACK. + */ + uint32_t pextack[ 16 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBIRQAMPTimestamp. + */ + irqamp_timestamp itstmp[ 16 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBIRQAMPBADDR. + */ + uint32_t baddr[ 16 ]; + + uint32_t reserved_240_300[ 48 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBIRQAMPIRQMAP. + */ + uint32_t irqmap[ 16 ]; + + uint32_t reserved_340_400[ 48 ]; +} irqamp; + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GRLIB_IRQAMP_REGS_H */ diff --git a/bsps/include/grlib/l2cache-regs.h b/bsps/include/grlib/l2cache-regs.h new file mode 100644 index 0000000000..604bde2a3e --- /dev/null +++ b/bsps/include/grlib/l2cache-regs.h @@ -0,0 +1,590 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSDeviceGRLIBL2CACHE + * + * @brief This header file defines the L2CACHE register block interface. + */ + +/* + * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file is part of the RTEMS quality process and was automatically + * generated. If you find something that needs to be fixed or + * worded better please post a report or patch to an RTEMS mailing list + * or raise a bug report: + * + * https://www.rtems.org/bugs.html + * + * For information on updating and regenerating please refer to the How-To + * section in the Software Requirements Engineering chapter of the + * RTEMS Software Engineering manual. The manual is provided as a part of + * a release. For development sources please refer to the online + * documentation at: + * + * https://docs.rtems.org + */ + +/* Generated from spec:/dev/grlib/if/l2cache-header */ + +#ifndef _GRLIB_L2CACHE_REGS_H +#define _GRLIB_L2CACHE_REGS_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Generated from spec:/dev/grlib/if/l2cache */ + +/** + * @defgroup RTEMSDeviceGRLIBL2CACHE L2CACHE + * + * @ingroup RTEMSDeviceGRLIB + * + * @brief This group contains the L2CACHE interfaces. + * + * @{ + */ + +/** + * @defgroup RTEMSDeviceGRLIBL2CACHEL2CC L2C Control register (L2CC) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define L2CACHE_L2CC_EN 0x80000000U + +#define L2CACHE_L2CC_EDAC 0x40000000U + +#define L2CACHE_L2CC_REPL_SHIFT 28 +#define L2CACHE_L2CC_REPL_MASK 0x30000000U +#define L2CACHE_L2CC_REPL_GET( _reg ) \ + ( ( ( _reg ) >> 28 ) & 0x3U ) +#define L2CACHE_L2CC_REPL( _val ) ( ( _val ) << 28 ) + +#define L2CACHE_L2CC_BBS_SHIFT 16 +#define L2CACHE_L2CC_BBS_MASK 0x70000U +#define L2CACHE_L2CC_BBS_GET( _reg ) \ + ( ( ( _reg ) >> 16 ) & 0x7U ) +#define L2CACHE_L2CC_BBS( _val ) ( ( _val ) << 16 ) + +#define L2CACHE_L2CC_INDEX_WAY_SHIFT 12 +#define L2CACHE_L2CC_INDEX_WAY_MASK 0xf000U +#define L2CACHE_L2CC_INDEX_WAY_GET( _reg ) \ + ( ( ( _reg ) >> 12 ) & 0xfU ) +#define L2CACHE_L2CC_INDEX_WAY( _val ) ( ( _val ) << 12 ) + +#define L2CACHE_L2CC_LOCK_SHIFT 8 +#define L2CACHE_L2CC_LOCK_MASK 0xf00U +#define L2CACHE_L2CC_LOCK_GET( _reg ) \ + ( ( ( _reg ) >> 8 ) & 0xfU ) +#define L2CACHE_L2CC_LOCK( _val ) ( ( _val ) << 8 ) + +#define L2CACHE_L2CC_HPRHB 0x20U + +#define L2CACHE_L2CC_HPB 0x10U + +#define L2CACHE_L2CC_UC 0x8U + +#define L2CACHE_L2CC_HC 0x4U + +#define L2CACHE_L2CC_WP 0x2U + +#define L2CACHE_L2CC_HP 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBL2CACHEL2CS L2C Status register (L2CS) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define L2CACHE_L2CS_LS 0x1000000U + +#define L2CACHE_L2CS_AT 0x800000U + +#define L2CACHE_L2CS_MP 0x400000U + +#define L2CACHE_L2CS_MTRR_SHIFT 16 +#define L2CACHE_L2CS_MTRR_MASK 0x3f0000U +#define L2CACHE_L2CS_MTRR_GET( _reg ) \ + ( ( ( _reg ) >> 16 ) & 0x3fU ) +#define L2CACHE_L2CS_MTRR( _val ) ( ( _val ) << 16 ) + +#define L2CACHE_L2CS_BBUS_W_SHIFT 13 +#define L2CACHE_L2CS_BBUS_W_MASK 0xe000U +#define L2CACHE_L2CS_BBUS_W_GET( _reg ) \ + ( ( ( _reg ) >> 13 ) & 0x7U ) +#define L2CACHE_L2CS_BBUS_W( _val ) ( ( _val ) << 13 ) + +#define L2CACHE_L2CS_WAY_SIZE_SHIFT 2 +#define L2CACHE_L2CS_WAY_SIZE_MASK 0x1ffcU +#define L2CACHE_L2CS_WAY_SIZE_GET( _reg ) \ + ( ( ( _reg ) >> 2 ) & 0x7ffU ) +#define L2CACHE_L2CS_WAY_SIZE( _val ) ( ( _val ) << 2 ) + +#define L2CACHE_L2CS_WAY_SHIFT 0 +#define L2CACHE_L2CS_WAY_MASK 0x3U +#define L2CACHE_L2CS_WAY_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0x3U ) +#define L2CACHE_L2CS_WAY( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBL2CACHEL2CFMA \ + * L2C Flush (Memory address) register (L2CFMA) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define L2CACHE_L2CFMA_ADDR_SHIFT 5 +#define L2CACHE_L2CFMA_ADDR_MASK 0xffffffe0U +#define L2CACHE_L2CFMA_ADDR_GET( _reg ) \ + ( ( ( _reg ) >> 5 ) & 0x7ffffffU ) +#define L2CACHE_L2CFMA_ADDR( _val ) ( ( _val ) << 5 ) + +#define L2CACHE_L2CFMA_DI 0x8U + +#define L2CACHE_L2CFMA_FMODE_SHIFT 0 +#define L2CACHE_L2CFMA_FMODE_MASK 0x7U +#define L2CACHE_L2CFMA_FMODE_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0x7U ) +#define L2CACHE_L2CFMA_FMODE( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBL2CACHEL2CFSI \ + * L2C Flush (Set, Index) register (L2CFSI) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define L2CACHE_L2CFSI_INDEX_SHIFT 16 +#define L2CACHE_L2CFSI_INDEX_MASK 0xffff0000U +#define L2CACHE_L2CFSI_INDEX_GET( _reg ) \ + ( ( ( _reg ) >> 16 ) & 0xffffU ) +#define L2CACHE_L2CFSI_INDEX( _val ) ( ( _val ) << 16 ) + +#define L2CACHE_L2CFSI_TAG_SHIFT 10 +#define L2CACHE_L2CFSI_TAG_MASK 0xfffffc00U +#define L2CACHE_L2CFSI_TAG_GET( _reg ) \ + ( ( ( _reg ) >> 10 ) & 0x3fffffU ) +#define L2CACHE_L2CFSI_TAG( _val ) ( ( _val ) << 10 ) + +#define L2CACHE_L2CFSI_FL 0x200U + +#define L2CACHE_L2CFSI_VB 0x100U + +#define L2CACHE_L2CFSI_DB 0x80U + +#define L2CACHE_L2CFSI_WAY_SHIFT 4 +#define L2CACHE_L2CFSI_WAY_MASK 0x30U +#define L2CACHE_L2CFSI_WAY_GET( _reg ) \ + ( ( ( _reg ) >> 4 ) & 0x3U ) +#define L2CACHE_L2CFSI_WAY( _val ) ( ( _val ) << 4 ) + +#define L2CACHE_L2CFSI_DI 0x8U + +#define L2CACHE_L2CFSI_WF 0x4U + +#define L2CACHE_L2CFSI_FMODE_SHIFT 0 +#define L2CACHE_L2CFSI_FMODE_MASK 0x3U +#define L2CACHE_L2CFSI_FMODE_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0x3U ) +#define L2CACHE_L2CFSI_FMODE( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBL2CACHEL2CERR \ + * L2CError status/control register (L2CERR) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define L2CACHE_L2CERR_AHB_MASTER_INDEX_SHIFT 28 +#define L2CACHE_L2CERR_AHB_MASTER_INDEX_MASK 0xf0000000U +#define L2CACHE_L2CERR_AHB_MASTER_INDEX_GET( _reg ) \ + ( ( ( _reg ) >> 28 ) & 0xfU ) +#define L2CACHE_L2CERR_AHB_MASTER_INDEX( _val ) ( ( _val ) << 28 ) + +#define L2CACHE_L2CERR_SCRUB 0x8000000U + +#define L2CACHE_L2CERR_TYPE_SHIFT 24 +#define L2CACHE_L2CERR_TYPE_MASK 0x7000000U +#define L2CACHE_L2CERR_TYPE_GET( _reg ) \ + ( ( ( _reg ) >> 24 ) & 0x7U ) +#define L2CACHE_L2CERR_TYPE( _val ) ( ( _val ) << 24 ) + +#define L2CACHE_L2CERR_TAG_DATA 0x800000U + +#define L2CACHE_L2CERR_COR_UCOR 0x400000U + +#define L2CACHE_L2CERR_MULTI 0x200000U + +#define L2CACHE_L2CERR_VALID 0x100000U + +#define L2CACHE_L2CERR_DISERESP 0x80000U + +#define L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER_SHIFT 16 +#define L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER_MASK 0x70000U +#define L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER_GET( _reg ) \ + ( ( ( _reg ) >> 16 ) & 0x7U ) +#define L2CACHE_L2CERR_CORRECTABLE_ERROR_COUNTER( _val ) ( ( _val ) << 16 ) + +#define L2CACHE_L2CERR_IRQ_PENDING_SHIFT 12 +#define L2CACHE_L2CERR_IRQ_PENDING_MASK 0xf000U +#define L2CACHE_L2CERR_IRQ_PENDING_GET( _reg ) \ + ( ( ( _reg ) >> 12 ) & 0xfU ) +#define L2CACHE_L2CERR_IRQ_PENDING( _val ) ( ( _val ) << 12 ) + +#define L2CACHE_L2CERR_IRQ_MASK_SHIFT 8 +#define L2CACHE_L2CERR_IRQ_MASK_MASK 0xf00U +#define L2CACHE_L2CERR_IRQ_MASK_GET( _reg ) \ + ( ( ( _reg ) >> 8 ) & 0xfU ) +#define L2CACHE_L2CERR_IRQ_MASK( _val ) ( ( _val ) << 8 ) + +#define L2CACHE_L2CERR_SELECT_CB_SHIFT 6 +#define L2CACHE_L2CERR_SELECT_CB_MASK 0xc0U +#define L2CACHE_L2CERR_SELECT_CB_GET( _reg ) \ + ( ( ( _reg ) >> 6 ) & 0x3U ) +#define L2CACHE_L2CERR_SELECT_CB( _val ) ( ( _val ) << 6 ) + +#define L2CACHE_L2CERR_SELECT_TCB_SHIFT 4 +#define L2CACHE_L2CERR_SELECT_TCB_MASK 0x30U +#define L2CACHE_L2CERR_SELECT_TCB_GET( _reg ) \ + ( ( ( _reg ) >> 4 ) & 0x3U ) +#define L2CACHE_L2CERR_SELECT_TCB( _val ) ( ( _val ) << 4 ) + +#define L2CACHE_L2CERR_XCB 0x8U + +#define L2CACHE_L2CERR_RCB 0x4U + +#define L2CACHE_L2CERR_COMP 0x2U + +#define L2CACHE_L2CERR_RST 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBL2CACHEL2CERRA \ + * L2C Error address register (L2CERRA) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define L2CACHE_L2CERRA_EADDR_SHIFT 0 +#define L2CACHE_L2CERRA_EADDR_MASK 0xffffffffU +#define L2CACHE_L2CERRA_EADDR_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define L2CACHE_L2CERRA_EADDR( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBL2CACHEL2CTCB L2C TAG-Check-Bits register (L2CTCB) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define L2CACHE_L2CTCB_TCB_SHIFT 0 +#define L2CACHE_L2CTCB_TCB_MASK 0x7fU +#define L2CACHE_L2CTCB_TCB_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0x7fU ) +#define L2CACHE_L2CTCB_TCB( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBL2CACHEL2CCB L2C Data-Check-Bits register (L2CCB) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define L2CACHE_L2CCB_CB_SHIFT 0 +#define L2CACHE_L2CCB_CB_MASK 0xfffffffU +#define L2CACHE_L2CCB_CB_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xfffffffU ) +#define L2CACHE_L2CCB_CB( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBL2CACHEL2CSCRUB \ + * L2C Scrub control/status register (L2CSCRUB) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define L2CACHE_L2CSCRUB_INDEX_SHIFT 16 +#define L2CACHE_L2CSCRUB_INDEX_MASK 0xffff0000U +#define L2CACHE_L2CSCRUB_INDEX_GET( _reg ) \ + ( ( ( _reg ) >> 16 ) & 0xffffU ) +#define L2CACHE_L2CSCRUB_INDEX( _val ) ( ( _val ) << 16 ) + +#define L2CACHE_L2CSCRUB_WAY_SHIFT 2 +#define L2CACHE_L2CSCRUB_WAY_MASK 0xcU +#define L2CACHE_L2CSCRUB_WAY_GET( _reg ) \ + ( ( ( _reg ) >> 2 ) & 0x3U ) +#define L2CACHE_L2CSCRUB_WAY( _val ) ( ( _val ) << 2 ) + +#define L2CACHE_L2CSCRUB_PEN 0x2U + +#define L2CACHE_L2CSCRUB_EN 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBL2CACHEL2CSDEL L2C Scrub delay register (L2CSDEL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define L2CACHE_L2CSDEL_DEL_SHIFT 0 +#define L2CACHE_L2CSDEL_DEL_MASK 0xffffU +#define L2CACHE_L2CSDEL_DEL_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffU ) +#define L2CACHE_L2CSDEL_DEL( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBL2CACHEL2CEINJ \ + * L2C Error injection register (L2CEINJ) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define L2CACHE_L2CEINJ_ADDR_SHIFT 2 +#define L2CACHE_L2CEINJ_ADDR_MASK 0xfffffffcU +#define L2CACHE_L2CEINJ_ADDR_GET( _reg ) \ + ( ( ( _reg ) >> 2 ) & 0x3fffffffU ) +#define L2CACHE_L2CEINJ_ADDR( _val ) ( ( _val ) << 2 ) + +#define L2CACHE_L2CEINJ_INJ 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBL2CACHEL2CACCC \ + * L2C Access control register (L2CACCC) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define L2CACHE_L2CACCC_DSC 0x4000U + +#define L2CACHE_L2CACCC_SH 0x2000U + +#define L2CACHE_L2CACCC_SPLITQ 0x400U + +#define L2CACHE_L2CACCC_NHM 0x200U + +#define L2CACHE_L2CACCC_BERR 0x100U + +#define L2CACHE_L2CACCC_OAPM 0x80U + +#define L2CACHE_L2CACCC_FLINE 0x40U + +#define L2CACHE_L2CACCC_DBPF 0x20U + +#define L2CACHE_L2CACCC_128WF 0x10U + +#define L2CACHE_L2CACCC_DBPWS 0x4U + +#define L2CACHE_L2CACCC_SPLIT 0x2U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBL2CACHEL2CEINJCFG \ + * L2C injection configuration register (L2CEINJCFG) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define L2CACHE_L2CEINJCFG_EDI 0x400U + +#define L2CACHE_L2CEINJCFG_TER 0x200U + +#define L2CACHE_L2CEINJCFG_IMD 0x100U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBL2CACHEL2CMTRR \ + * L2C Memory type range register (L2CMTRR) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define L2CACHE_L2CMTRR_ADDR_SHIFT 18 +#define L2CACHE_L2CMTRR_ADDR_MASK 0xfffc0000U +#define L2CACHE_L2CMTRR_ADDR_GET( _reg ) \ + ( ( ( _reg ) >> 18 ) & 0x3fffU ) +#define L2CACHE_L2CMTRR_ADDR( _val ) ( ( _val ) << 18 ) + +#define L2CACHE_L2CMTRR_ACC_SHIFT 16 +#define L2CACHE_L2CMTRR_ACC_MASK 0x30000U +#define L2CACHE_L2CMTRR_ACC_GET( _reg ) \ + ( ( ( _reg ) >> 16 ) & 0x3U ) +#define L2CACHE_L2CMTRR_ACC( _val ) ( ( _val ) << 16 ) + +#define L2CACHE_L2CMTRR_MASK_SHIFT 2 +#define L2CACHE_L2CMTRR_MASK_MASK 0xfffcU +#define L2CACHE_L2CMTRR_MASK_GET( _reg ) \ + ( ( ( _reg ) >> 2 ) & 0x3fffU ) +#define L2CACHE_L2CMTRR_MASK( _val ) ( ( _val ) << 2 ) + +#define L2CACHE_L2CMTRR_WP 0x2U + +#define L2CACHE_L2CMTRR_AC 0x1U + +/** @} */ + +/** + * @brief This structure defines the L2CACHE register block memory map. + */ +typedef struct l2cache { + /** + * @brief See @ref RTEMSDeviceGRLIBL2CACHEL2CC. + */ + uint32_t l2cc; + + /** + * @brief See @ref RTEMSDeviceGRLIBL2CACHEL2CS. + */ + uint32_t l2cs; + + /** + * @brief See @ref RTEMSDeviceGRLIBL2CACHEL2CFMA. + */ + uint32_t l2cfma; + + /** + * @brief See @ref RTEMSDeviceGRLIBL2CACHEL2CFSI. + */ + uint32_t l2cfsi; + + uint32_t reserved_10_20[ 4 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBL2CACHEL2CERR. + */ + uint32_t l2cerr; + + /** + * @brief See @ref RTEMSDeviceGRLIBL2CACHEL2CERRA. + */ + uint32_t l2cerra; + + /** + * @brief See @ref RTEMSDeviceGRLIBL2CACHEL2CTCB. + */ + uint32_t l2ctcb; + + /** + * @brief See @ref RTEMSDeviceGRLIBL2CACHEL2CCB. + */ + uint32_t l2ccb; + + /** + * @brief See @ref RTEMSDeviceGRLIBL2CACHEL2CSCRUB. + */ + uint32_t l2cscrub; + + /** + * @brief See @ref RTEMSDeviceGRLIBL2CACHEL2CSDEL. + */ + uint32_t l2csdel; + + /** + * @brief See @ref RTEMSDeviceGRLIBL2CACHEL2CEINJ. + */ + uint32_t l2ceinj; + + /** + * @brief See @ref RTEMSDeviceGRLIBL2CACHEL2CACCC. + */ + uint32_t l2caccc; + + uint32_t reserved_40_4c[ 3 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBL2CACHEL2CEINJCFG. + */ + uint32_t l2ceinjcfg; + + uint32_t reserved_50_80[ 12 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBL2CACHEL2CMTRR. + */ + uint32_t l2cmtrr; +} l2cache; + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GRLIB_L2CACHE_REGS_H */ diff --git a/bsps/include/grlib/l4stat-regs.h b/bsps/include/grlib/l4stat-regs.h new file mode 100644 index 0000000000..b2a47e7dec --- /dev/null +++ b/bsps/include/grlib/l4stat-regs.h @@ -0,0 +1,241 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSDeviceGRLIBL4STAT + * + * @brief This header file defines the L4STAT register block interface. + */ + +/* + * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file is part of the RTEMS quality process and was automatically + * generated. If you find something that needs to be fixed or + * worded better please post a report or patch to an RTEMS mailing list + * or raise a bug report: + * + * https://www.rtems.org/bugs.html + * + * For information on updating and regenerating please refer to the How-To + * section in the Software Requirements Engineering chapter of the + * RTEMS Software Engineering manual. The manual is provided as a part of + * a release. For development sources please refer to the online + * documentation at: + * + * https://docs.rtems.org + */ + +/* Generated from spec:/dev/grlib/if/l4stat-header */ + +#ifndef _GRLIB_L4STAT_REGS_H +#define _GRLIB_L4STAT_REGS_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Generated from spec:/dev/grlib/if/l4stat */ + +/** + * @defgroup RTEMSDeviceGRLIBL4STAT L4STAT + * + * @ingroup RTEMSDeviceGRLIB + * + * @brief This group contains the L4STAT interfaces. + * + * @{ + */ + +/** + * @defgroup RTEMSDeviceGRLIBL4STATCVAL Counter 0-15 value register (CVAL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define L4STAT_CVAL_CVAL_SHIFT 0 +#define L4STAT_CVAL_CVAL_MASK 0xffffffffU +#define L4STAT_CVAL_CVAL_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define L4STAT_CVAL_CVAL( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBL4STATCCTRL Counter 0-15 control register (CCTRL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define L4STAT_CCTRL_NCPU_SHIFT 28 +#define L4STAT_CCTRL_NCPU_MASK 0xf0000000U +#define L4STAT_CCTRL_NCPU_GET( _reg ) \ + ( ( ( _reg ) >> 28 ) & 0xfU ) +#define L4STAT_CCTRL_NCPU( _val ) ( ( _val ) << 28 ) + +#define L4STAT_CCTRL_NCNT_SHIFT 23 +#define L4STAT_CCTRL_NCNT_MASK 0xf800000U +#define L4STAT_CCTRL_NCNT_GET( _reg ) \ + ( ( ( _reg ) >> 23 ) & 0x1fU ) +#define L4STAT_CCTRL_NCNT( _val ) ( ( _val ) << 23 ) + +#define L4STAT_CCTRL_MC 0x400000U + +#define L4STAT_CCTRL_IA 0x200000U + +#define L4STAT_CCTRL_DS 0x100000U + +#define L4STAT_CCTRL_EE 0x80000U + +#define L4STAT_CCTRL_AE 0x40000U + +#define L4STAT_CCTRL_EL 0x20000U + +#define L4STAT_CCTRL_CD 0x10000U + +#define L4STAT_CCTRL_SU_SHIFT 14 +#define L4STAT_CCTRL_SU_MASK 0xc000U +#define L4STAT_CCTRL_SU_GET( _reg ) \ + ( ( ( _reg ) >> 14 ) & 0x3U ) +#define L4STAT_CCTRL_SU( _val ) ( ( _val ) << 14 ) + +#define L4STAT_CCTRL_CL 0x2000U + +#define L4STAT_CCTRL_EN 0x1000U + +#define L4STAT_CCTRL_EVENT_ID_SHIFT 4 +#define L4STAT_CCTRL_EVENT_ID_MASK 0xff0U +#define L4STAT_CCTRL_EVENT_ID_GET( _reg ) \ + ( ( ( _reg ) >> 4 ) & 0xffU ) +#define L4STAT_CCTRL_EVENT_ID( _val ) ( ( _val ) << 4 ) + +#define L4STAT_CCTRL_CPU_AHBM_SHIFT 0 +#define L4STAT_CCTRL_CPU_AHBM_MASK 0xfU +#define L4STAT_CCTRL_CPU_AHBM_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xfU ) +#define L4STAT_CCTRL_CPU_AHBM( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBL4STATCSVAL \ + * Counter 0-15 max/latch register (CSVAL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define L4STAT_CSVAL_CSVAL_SHIFT 0 +#define L4STAT_CSVAL_CSVAL_MASK 0xffffffffU +#define L4STAT_CSVAL_CSVAL_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define L4STAT_CSVAL_CSVAL( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBL4STATTSTAMP Timestamp register (TSTAMP) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define L4STAT_TSTAMP_TSTAMP_SHIFT 0 +#define L4STAT_TSTAMP_TSTAMP_MASK 0xffffffffU +#define L4STAT_TSTAMP_TSTAMP_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define L4STAT_TSTAMP_TSTAMP( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @brief This structure defines the L4STAT register block memory map. + */ +typedef struct l4stat { + /** + * @brief See @ref RTEMSDeviceGRLIBL4STATCVAL. + */ + uint32_t cval_0; + + uint32_t reserved_4_3c[ 14 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBL4STATCVAL. + */ + uint32_t cval_1; + + uint32_t reserved_40_80[ 16 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBL4STATCCTRL. + */ + uint32_t cctrl_0; + + uint32_t reserved_84_cc[ 18 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBL4STATCCTRL. + */ + uint32_t cctrl_1; + + uint32_t reserved_d0_100[ 12 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBL4STATCSVAL. + */ + uint32_t csval_0; + + uint32_t reserved_104_13c[ 14 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBL4STATCSVAL. + */ + uint32_t csval_1; + + uint32_t reserved_140_180[ 16 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBL4STATTSTAMP. + */ + uint32_t tstamp; +} l4stat; + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GRLIB_L4STAT_REGS_H */ diff --git a/bsps/include/grlib/memscrub-regs.h b/bsps/include/grlib/memscrub-regs.h new file mode 100644 index 0000000000..8c326795a5 --- /dev/null +++ b/bsps/include/grlib/memscrub-regs.h @@ -0,0 +1,428 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSDeviceGRLIBMEMSCRUB + * + * @brief This header file defines the MEMSCRUB register block interface. + */ + +/* + * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file is part of the RTEMS quality process and was automatically + * generated. If you find something that needs to be fixed or + * worded better please post a report or patch to an RTEMS mailing list + * or raise a bug report: + * + * https://www.rtems.org/bugs.html + * + * For information on updating and regenerating please refer to the How-To + * section in the Software Requirements Engineering chapter of the + * RTEMS Software Engineering manual. The manual is provided as a part of + * a release. For development sources please refer to the online + * documentation at: + * + * https://docs.rtems.org + */ + +/* Generated from spec:/dev/grlib/if/memscrub-header */ + +#ifndef _GRLIB_MEMSCRUB_REGS_H +#define _GRLIB_MEMSCRUB_REGS_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Generated from spec:/dev/grlib/if/memscrub */ + +/** + * @defgroup RTEMSDeviceGRLIBMEMSCRUB MEMSCRUB + * + * @ingroup RTEMSDeviceGRLIB + * + * @brief This group contains the MEMSCRUB interfaces. + * + * @{ + */ + +/** + * @defgroup RTEMSDeviceGRLIBMEMSCRUBAHBS AHB Status register (AHBS) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define MEMSCRUB_AHBS_CECNT_SHIFT 22 +#define MEMSCRUB_AHBS_CECNT_MASK 0xffc00000U +#define MEMSCRUB_AHBS_CECNT_GET( _reg ) \ + ( ( ( _reg ) >> 22 ) & 0x3ffU ) +#define MEMSCRUB_AHBS_CECNT( _val ) ( ( _val ) << 22 ) + +#define MEMSCRUB_AHBS_UECNT_SHIFT 14 +#define MEMSCRUB_AHBS_UECNT_MASK 0x3fc000U +#define MEMSCRUB_AHBS_UECNT_GET( _reg ) \ + ( ( ( _reg ) >> 14 ) & 0xffU ) +#define MEMSCRUB_AHBS_UECNT( _val ) ( ( _val ) << 14 ) + +#define MEMSCRUB_AHBS_DONE 0x2000U + +#define MEMSCRUB_AHBS_SEC 0x800U + +#define MEMSCRUB_AHBS_SBC 0x400U + +#define MEMSCRUB_AHBS_CE 0x200U + +#define MEMSCRUB_AHBS_NE 0x100U + +#define MEMSCRUB_AHBS_HWRITE 0x80U + +#define MEMSCRUB_AHBS_HMASTER_SHIFT 3 +#define MEMSCRUB_AHBS_HMASTER_MASK 0x78U +#define MEMSCRUB_AHBS_HMASTER_GET( _reg ) \ + ( ( ( _reg ) >> 3 ) & 0xfU ) +#define MEMSCRUB_AHBS_HMASTER( _val ) ( ( _val ) << 3 ) + +#define MEMSCRUB_AHBS_HSIZE_SHIFT 0 +#define MEMSCRUB_AHBS_HSIZE_MASK 0x7U +#define MEMSCRUB_AHBS_HSIZE_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0x7U ) +#define MEMSCRUB_AHBS_HSIZE( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBMEMSCRUBAHBFAR \ + * AHB Failing Address Register (AHBFAR) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define MEMSCRUB_AHBFAR_AHB_FAILING_ADDRESS_SHIFT 0 +#define MEMSCRUB_AHBFAR_AHB_FAILING_ADDRESS_MASK 0xffffffffU +#define MEMSCRUB_AHBFAR_AHB_FAILING_ADDRESS_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define MEMSCRUB_AHBFAR_AHB_FAILING_ADDRESS( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBMEMSCRUBAHBERC \ + * AHB Error configuration register (AHBERC) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define MEMSCRUB_AHBERC_CECNTT_SHIFT 22 +#define MEMSCRUB_AHBERC_CECNTT_MASK 0xffc00000U +#define MEMSCRUB_AHBERC_CECNTT_GET( _reg ) \ + ( ( ( _reg ) >> 22 ) & 0x3ffU ) +#define MEMSCRUB_AHBERC_CECNTT( _val ) ( ( _val ) << 22 ) + +#define MEMSCRUB_AHBERC_UECNTT_SHIFT 14 +#define MEMSCRUB_AHBERC_UECNTT_MASK 0x3fc000U +#define MEMSCRUB_AHBERC_UECNTT_GET( _reg ) \ + ( ( ( _reg ) >> 14 ) & 0xffU ) +#define MEMSCRUB_AHBERC_UECNTT( _val ) ( ( _val ) << 14 ) + +#define MEMSCRUB_AHBERC_CECTE 0x2U + +#define MEMSCRUB_AHBERC_UECTE 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBMEMSCRUBSTAT Status register (STAT) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define MEMSCRUB_STAT_RUNCOUNT_SHIFT 22 +#define MEMSCRUB_STAT_RUNCOUNT_MASK 0xffc00000U +#define MEMSCRUB_STAT_RUNCOUNT_GET( _reg ) \ + ( ( ( _reg ) >> 22 ) & 0x3ffU ) +#define MEMSCRUB_STAT_RUNCOUNT( _val ) ( ( _val ) << 22 ) + +#define MEMSCRUB_STAT_BLKCOUNT_SHIFT 14 +#define MEMSCRUB_STAT_BLKCOUNT_MASK 0x3fc000U +#define MEMSCRUB_STAT_BLKCOUNT_GET( _reg ) \ + ( ( ( _reg ) >> 14 ) & 0xffU ) +#define MEMSCRUB_STAT_BLKCOUNT( _val ) ( ( _val ) << 14 ) + +#define MEMSCRUB_STAT_DONE 0x2000U + +#define MEMSCRUB_STAT_BURSTLEN_SHIFT 1 +#define MEMSCRUB_STAT_BURSTLEN_MASK 0x1eU +#define MEMSCRUB_STAT_BURSTLEN_GET( _reg ) \ + ( ( ( _reg ) >> 1 ) & 0xfU ) +#define MEMSCRUB_STAT_BURSTLEN( _val ) ( ( _val ) << 1 ) + +#define MEMSCRUB_STAT_ACTIVE 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBMEMSCRUBCONFIG Configuration register (CONFIG) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define MEMSCRUB_CONFIG_DELAY_SHIFT 8 +#define MEMSCRUB_CONFIG_DELAY_MASK 0xff00U +#define MEMSCRUB_CONFIG_DELAY_GET( _reg ) \ + ( ( ( _reg ) >> 8 ) & 0xffU ) +#define MEMSCRUB_CONFIG_DELAY( _val ) ( ( _val ) << 8 ) + +#define MEMSCRUB_CONFIG_IRQD 0x80U + +#define MEMSCRUB_CONFIG_SERA 0x20U + +#define MEMSCRUB_CONFIG_LOOP 0x10U + +#define MEMSCRUB_CONFIG_MODE_SHIFT 2 +#define MEMSCRUB_CONFIG_MODE_MASK 0xcU +#define MEMSCRUB_CONFIG_MODE_GET( _reg ) \ + ( ( ( _reg ) >> 2 ) & 0x3U ) +#define MEMSCRUB_CONFIG_MODE( _val ) ( ( _val ) << 2 ) + +#define MEMSCRUB_CONFIG_ES 0x2U + +#define MEMSCRUB_CONFIG_SCEN 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBMEMSCRUBRANGEL Range low address register (RANGEL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define MEMSCRUB_RANGEL_RLADDR_SHIFT 0 +#define MEMSCRUB_RANGEL_RLADDR_MASK 0xffffffffU +#define MEMSCRUB_RANGEL_RLADDR_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define MEMSCRUB_RANGEL_RLADDR( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBMEMSCRUBRANGEH \ + * Range high address register (RANGEH) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define MEMSCRUB_RANGEH_RHADDR_SHIFT 0 +#define MEMSCRUB_RANGEH_RHADDR_MASK 0xffffffffU +#define MEMSCRUB_RANGEH_RHADDR_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define MEMSCRUB_RANGEH_RHADDR( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBMEMSCRUBPOS Position register (POS) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define MEMSCRUB_POS_POSITION_SHIFT 0 +#define MEMSCRUB_POS_POSITION_MASK 0xffffffffU +#define MEMSCRUB_POS_POSITION_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define MEMSCRUB_POS_POSITION( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBMEMSCRUBETHRES Error threshold register (ETHRES) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define MEMSCRUB_ETHRES_RECT_SHIFT 22 +#define MEMSCRUB_ETHRES_RECT_MASK 0xffc00000U +#define MEMSCRUB_ETHRES_RECT_GET( _reg ) \ + ( ( ( _reg ) >> 22 ) & 0x3ffU ) +#define MEMSCRUB_ETHRES_RECT( _val ) ( ( _val ) << 22 ) + +#define MEMSCRUB_ETHRES_BECT_SHIFT 14 +#define MEMSCRUB_ETHRES_BECT_MASK 0x3fc000U +#define MEMSCRUB_ETHRES_BECT_GET( _reg ) \ + ( ( ( _reg ) >> 14 ) & 0xffU ) +#define MEMSCRUB_ETHRES_BECT( _val ) ( ( _val ) << 14 ) + +#define MEMSCRUB_ETHRES_RECTE 0x2U + +#define MEMSCRUB_ETHRES_BECTE 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBMEMSCRUBINIT Initialisation data register (INIT) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define MEMSCRUB_INIT_DATA_SHIFT 0 +#define MEMSCRUB_INIT_DATA_MASK 0xffffffffU +#define MEMSCRUB_INIT_DATA_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define MEMSCRUB_INIT_DATA( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBMEMSCRUBRANGEL2 \ + * Second range low address register (RANGEL2) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define MEMSCRUB_RANGEL2_RLADDR_SHIFT 0 +#define MEMSCRUB_RANGEL2_RLADDR_MASK 0xffffffffU +#define MEMSCRUB_RANGEL2_RLADDR_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define MEMSCRUB_RANGEL2_RLADDR( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBMEMSCRUBRANGEH2 \ + * Second range high address register (RANGEH2) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define MEMSCRUB_RANGEH2_RHADDR_SHIFT 0 +#define MEMSCRUB_RANGEH2_RHADDR_MASK 0xffffffffU +#define MEMSCRUB_RANGEH2_RHADDR_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define MEMSCRUB_RANGEH2_RHADDR( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @brief This structure defines the MEMSCRUB register block memory map. + */ +typedef struct memscrub { + /** + * @brief See @ref RTEMSDeviceGRLIBMEMSCRUBAHBS. + */ + uint32_t ahbs; + + /** + * @brief See @ref RTEMSDeviceGRLIBMEMSCRUBAHBFAR. + */ + uint32_t ahbfar; + + /** + * @brief See @ref RTEMSDeviceGRLIBMEMSCRUBAHBERC. + */ + uint32_t ahberc; + + uint32_t reserved_c_10; + + /** + * @brief See @ref RTEMSDeviceGRLIBMEMSCRUBSTAT. + */ + uint32_t stat; + + /** + * @brief See @ref RTEMSDeviceGRLIBMEMSCRUBCONFIG. + */ + uint32_t config; + + /** + * @brief See @ref RTEMSDeviceGRLIBMEMSCRUBRANGEL. + */ + uint32_t rangel; + + /** + * @brief See @ref RTEMSDeviceGRLIBMEMSCRUBRANGEH. + */ + uint32_t rangeh; + + /** + * @brief See @ref RTEMSDeviceGRLIBMEMSCRUBPOS. + */ + uint32_t pos; + + /** + * @brief See @ref RTEMSDeviceGRLIBMEMSCRUBETHRES. + */ + uint32_t ethres; + + /** + * @brief See @ref RTEMSDeviceGRLIBMEMSCRUBINIT. + */ + uint32_t init; + + /** + * @brief See @ref RTEMSDeviceGRLIBMEMSCRUBRANGEL2. + */ + uint32_t rangel2; + + /** + * @brief See @ref RTEMSDeviceGRLIBMEMSCRUBRANGEH2. + */ + uint32_t rangeh2; +} memscrub; + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GRLIB_MEMSCRUB_REGS_H */ diff --git a/bsps/include/grlib/mmctrl-regs.h b/bsps/include/grlib/mmctrl-regs.h new file mode 100644 index 0000000000..a08f559bb9 --- /dev/null +++ b/bsps/include/grlib/mmctrl-regs.h @@ -0,0 +1,322 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSDeviceGRLIBMMCTRL + * + * @brief This header file defines the MMCTRL register block interface. + */ + +/* + * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file is part of the RTEMS quality process and was automatically + * generated. If you find something that needs to be fixed or + * worded better please post a report or patch to an RTEMS mailing list + * or raise a bug report: + * + * https://www.rtems.org/bugs.html + * + * For information on updating and regenerating please refer to the How-To + * section in the Software Requirements Engineering chapter of the + * RTEMS Software Engineering manual. The manual is provided as a part of + * a release. For development sources please refer to the online + * documentation at: + * + * https://docs.rtems.org + */ + +/* Generated from spec:/dev/grlib/if/mmctrl-header */ + +#ifndef _GRLIB_MMCTRL_REGS_H +#define _GRLIB_MMCTRL_REGS_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Generated from spec:/dev/grlib/if/mmctrl */ + +/** + * @defgroup RTEMSDeviceGRLIBMMCTRL MMCTRL + * + * @ingroup RTEMSDeviceGRLIB + * + * @brief This group contains the MMCTRL interfaces. + * + * @{ + */ + +/** + * @defgroup RTEMSDeviceGRLIBMMCTRLSDCFG1 \ + * SDRAM configuration register 1 (SDCFG1) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define MMCTRL_SDCFG1_RF 0x80000000U + +#define MMCTRL_SDCFG1_TRP 0x40000000U + +#define MMCTRL_SDCFG1_TRFC_SHIFT 27 +#define MMCTRL_SDCFG1_TRFC_MASK 0x38000000U +#define MMCTRL_SDCFG1_TRFC_GET( _reg ) \ + ( ( ( _reg ) >> 27 ) & 0x7U ) +#define MMCTRL_SDCFG1_TRFC( _val ) ( ( _val ) << 27 ) + +#define MMCTRL_SDCFG1_TC 0x4000000U + +#define MMCTRL_SDCFG1_BANKSZ_SHIFT 23 +#define MMCTRL_SDCFG1_BANKSZ_MASK 0x3800000U +#define MMCTRL_SDCFG1_BANKSZ_GET( _reg ) \ + ( ( ( _reg ) >> 23 ) & 0x7U ) +#define MMCTRL_SDCFG1_BANKSZ( _val ) ( ( _val ) << 23 ) + +#define MMCTRL_SDCFG1_COLSZ_SHIFT 21 +#define MMCTRL_SDCFG1_COLSZ_MASK 0x600000U +#define MMCTRL_SDCFG1_COLSZ_GET( _reg ) \ + ( ( ( _reg ) >> 21 ) & 0x3U ) +#define MMCTRL_SDCFG1_COLSZ( _val ) ( ( _val ) << 21 ) + +#define MMCTRL_SDCFG1_COMMAND_SHIFT 18 +#define MMCTRL_SDCFG1_COMMAND_MASK 0x1c0000U +#define MMCTRL_SDCFG1_COMMAND_GET( _reg ) \ + ( ( ( _reg ) >> 18 ) & 0x7U ) +#define MMCTRL_SDCFG1_COMMAND( _val ) ( ( _val ) << 18 ) + +#define MMCTRL_SDCFG1_MS 0x10000U + +#define MMCTRL_SDCFG1_64 0x8000U + +#define MMCTRL_SDCFG1_RFLOAD_SHIFT 0 +#define MMCTRL_SDCFG1_RFLOAD_MASK 0x7fffU +#define MMCTRL_SDCFG1_RFLOAD_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0x7fffU ) +#define MMCTRL_SDCFG1_RFLOAD( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBMMCTRLSDCFG2 \ + * SDRAM configuration register 2 (SDCFG2) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define MMCTRL_SDCFG2_CE 0x40000000U + +#define MMCTRL_SDCFG2_EN2T 0x8000U + +#define MMCTRL_SDCFG2_DCS 0x4000U + +#define MMCTRL_SDCFG2_BPARK 0x2000U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBMMCTRLMUXCFG Mux configuration register (MUXCFG) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define MMCTRL_MUXCFG_ERRLOC_SHIFT 20 +#define MMCTRL_MUXCFG_ERRLOC_MASK 0xfff00000U +#define MMCTRL_MUXCFG_ERRLOC_GET( _reg ) \ + ( ( ( _reg ) >> 20 ) & 0xfffU ) +#define MMCTRL_MUXCFG_ERRLOC( _val ) ( ( _val ) << 20 ) + +#define MMCTRL_MUXCFG_DDERR 0x80000U + +#define MMCTRL_MUXCFG_DWIDTH_SHIFT 16 +#define MMCTRL_MUXCFG_DWIDTH_MASK 0x70000U +#define MMCTRL_MUXCFG_DWIDTH_GET( _reg ) \ + ( ( ( _reg ) >> 16 ) & 0x7U ) +#define MMCTRL_MUXCFG_DWIDTH( _val ) ( ( _val ) << 16 ) + +#define MMCTRL_MUXCFG_BEID_SHIFT 12 +#define MMCTRL_MUXCFG_BEID_MASK 0xf000U +#define MMCTRL_MUXCFG_BEID_GET( _reg ) \ + ( ( ( _reg ) >> 12 ) & 0xfU ) +#define MMCTRL_MUXCFG_BEID( _val ) ( ( _val ) << 12 ) + +#define MMCTRL_MUXCFG_DATAMUX_SHIFT 5 +#define MMCTRL_MUXCFG_DATAMUX_MASK 0xe0U +#define MMCTRL_MUXCFG_DATAMUX_GET( _reg ) \ + ( ( ( _reg ) >> 5 ) & 0x7U ) +#define MMCTRL_MUXCFG_DATAMUX( _val ) ( ( _val ) << 5 ) + +#define MMCTRL_MUXCFG_CEN 0x10U + +#define MMCTRL_MUXCFG_BAUPD 0x8U + +#define MMCTRL_MUXCFG_BAEN 0x4U + +#define MMCTRL_MUXCFG_CODE 0x2U + +#define MMCTRL_MUXCFG_EDEN 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBMMCTRLFTDA FT diagnostic address register (FTDA) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define MMCTRL_FTDA_FTDA_SHIFT 2 +#define MMCTRL_FTDA_FTDA_MASK 0xfffffffcU +#define MMCTRL_FTDA_FTDA_GET( _reg ) \ + ( ( ( _reg ) >> 2 ) & 0x3fffffffU ) +#define MMCTRL_FTDA_FTDA( _val ) ( ( _val ) << 2 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBMMCTRLFTDC FT diagnostic checkbits register (FTDC) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define MMCTRL_FTDC_CBD_SHIFT 24 +#define MMCTRL_FTDC_CBD_MASK 0xff000000U +#define MMCTRL_FTDC_CBD_GET( _reg ) \ + ( ( ( _reg ) >> 24 ) & 0xffU ) +#define MMCTRL_FTDC_CBD( _val ) ( ( _val ) << 24 ) + +#define MMCTRL_FTDC_CBC_SHIFT 16 +#define MMCTRL_FTDC_CBC_MASK 0xff0000U +#define MMCTRL_FTDC_CBC_GET( _reg ) \ + ( ( ( _reg ) >> 16 ) & 0xffU ) +#define MMCTRL_FTDC_CBC( _val ) ( ( _val ) << 16 ) + +#define MMCTRL_FTDC_CBB_SHIFT 8 +#define MMCTRL_FTDC_CBB_MASK 0xff00U +#define MMCTRL_FTDC_CBB_GET( _reg ) \ + ( ( ( _reg ) >> 8 ) & 0xffU ) +#define MMCTRL_FTDC_CBB( _val ) ( ( _val ) << 8 ) + +#define MMCTRL_FTDC_CBA_SHIFT 0 +#define MMCTRL_FTDC_CBA_MASK 0xffU +#define MMCTRL_FTDC_CBA_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffU ) +#define MMCTRL_FTDC_CBA( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBMMCTRLFTDD FT diagnostic data register (FTDD) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define MMCTRL_FTDD_DATA_SHIFT 0 +#define MMCTRL_FTDD_DATA_MASK 0xffffffffU +#define MMCTRL_FTDD_DATA_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define MMCTRL_FTDD_DATA( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBMMCTRLFTBND FT boundary address register (FTBND) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define MMCTRL_FTBND_FTBND_31_3_SHIFT 3 +#define MMCTRL_FTBND_FTBND_31_3_MASK 0xfffffff8U +#define MMCTRL_FTBND_FTBND_31_3_GET( _reg ) \ + ( ( ( _reg ) >> 3 ) & 0x1fffffffU ) +#define MMCTRL_FTBND_FTBND_31_3( _val ) ( ( _val ) << 3 ) + +/** @} */ + +/** + * @brief This structure defines the MMCTRL register block memory map. + */ +typedef struct mmctrl { + /** + * @brief See @ref RTEMSDeviceGRLIBMMCTRLSDCFG1. + */ + uint32_t sdcfg1; + + /** + * @brief See @ref RTEMSDeviceGRLIBMMCTRLSDCFG2. + */ + uint32_t sdcfg2; + + uint32_t reserved_8_20[ 6 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBMMCTRLMUXCFG. + */ + uint32_t muxcfg; + + /** + * @brief See @ref RTEMSDeviceGRLIBMMCTRLFTDA. + */ + uint32_t ftda; + + /** + * @brief See @ref RTEMSDeviceGRLIBMMCTRLFTDC. + */ + uint32_t ftdc; + + /** + * @brief See @ref RTEMSDeviceGRLIBMMCTRLFTDD. + */ + uint32_t ftdd; + + /** + * @brief See @ref RTEMSDeviceGRLIBMMCTRLFTBND. + */ + uint32_t ftbnd; +} mmctrl; + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GRLIB_MMCTRL_REGS_H */ diff --git a/bsps/include/grlib/spictrl-regs.h b/bsps/include/grlib/spictrl-regs.h new file mode 100644 index 0000000000..0bd2db1528 --- /dev/null +++ b/bsps/include/grlib/spictrl-regs.h @@ -0,0 +1,373 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSDeviceGRLIBSPICTRL + * + * @brief This header file defines the SPICTRL register block interface. + */ + +/* + * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file is part of the RTEMS quality process and was automatically + * generated. If you find something that needs to be fixed or + * worded better please post a report or patch to an RTEMS mailing list + * or raise a bug report: + * + * https://www.rtems.org/bugs.html + * + * For information on updating and regenerating please refer to the How-To + * section in the Software Requirements Engineering chapter of the + * RTEMS Software Engineering manual. The manual is provided as a part of + * a release. For development sources please refer to the online + * documentation at: + * + * https://docs.rtems.org + */ + +/* Generated from spec:/dev/grlib/if/spictrl-header */ + +#ifndef _GRLIB_SPICTRL_REGS_H +#define _GRLIB_SPICTRL_REGS_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Generated from spec:/dev/grlib/if/spictrl */ + +/** + * @defgroup RTEMSDeviceGRLIBSPICTRL SPICTRL + * + * @ingroup RTEMSDeviceGRLIB + * + * @brief This group contains the SPICTRL interfaces. + * + * @{ + */ + +/** + * @defgroup RTEMSDeviceGRLIBSPICTRLCAP Capability register (CAP) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPICTRL_CAP_SSSZ_SHIFT 24 +#define SPICTRL_CAP_SSSZ_MASK 0xff000000U +#define SPICTRL_CAP_SSSZ_GET( _reg ) \ + ( ( ( _reg ) >> 24 ) & 0xffU ) +#define SPICTRL_CAP_SSSZ( _val ) ( ( _val ) << 24 ) + +#define SPICTRL_CAP_MAXWLEN_SHIFT 20 +#define SPICTRL_CAP_MAXWLEN_MASK 0xf00000U +#define SPICTRL_CAP_MAXWLEN_GET( _reg ) \ + ( ( ( _reg ) >> 20 ) & 0xfU ) +#define SPICTRL_CAP_MAXWLEN( _val ) ( ( _val ) << 20 ) + +#define SPICTRL_CAP_TWEN 0x80000U + +#define SPICTRL_CAP_AMODE 0x40000U + +#define SPICTRL_CAP_ASELA 0x20000U + +#define SPICTRL_CAP_SSEN 0x10000U + +#define SPICTRL_CAP_FDEPTH_SHIFT 8 +#define SPICTRL_CAP_FDEPTH_MASK 0xff00U +#define SPICTRL_CAP_FDEPTH_GET( _reg ) \ + ( ( ( _reg ) >> 8 ) & 0xffU ) +#define SPICTRL_CAP_FDEPTH( _val ) ( ( _val ) << 8 ) + +#define SPICTRL_CAP_SR 0x80U + +#define SPICTRL_CAP_FT_SHIFT 5 +#define SPICTRL_CAP_FT_MASK 0x60U +#define SPICTRL_CAP_FT_GET( _reg ) \ + ( ( ( _reg ) >> 5 ) & 0x3U ) +#define SPICTRL_CAP_FT( _val ) ( ( _val ) << 5 ) + +#define SPICTRL_CAP_REV_SHIFT 0 +#define SPICTRL_CAP_REV_MASK 0x1fU +#define SPICTRL_CAP_REV_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0x1fU ) +#define SPICTRL_CAP_REV( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPICTRLMODE Mode register (MODE) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPICTRL_MODE_LOOP 0x40000000U + +#define SPICTRL_MODE_CPOL 0x20000000U + +#define SPICTRL_MODE_CPHA 0x10000000U + +#define SPICTRL_MODE_DIV_16 0x8000000U + +#define SPICTRL_MODE_REV 0x4000000U + +#define SPICTRL_MODE_MX 0x2000000U + +#define SPICTRL_MODE_EN 0x1000000U + +#define SPICTRL_MODE_LEN_SHIFT 20 +#define SPICTRL_MODE_LEN_MASK 0xf00000U +#define SPICTRL_MODE_LEN_GET( _reg ) \ + ( ( ( _reg ) >> 20 ) & 0xfU ) +#define SPICTRL_MODE_LEN( _val ) ( ( _val ) << 20 ) + +#define SPICTRL_MODE_PM_SHIFT 16 +#define SPICTRL_MODE_PM_MASK 0xf0000U +#define SPICTRL_MODE_PM_GET( _reg ) \ + ( ( ( _reg ) >> 16 ) & 0xfU ) +#define SPICTRL_MODE_PM( _val ) ( ( _val ) << 16 ) + +#define SPICTRL_MODE_TWEN 0x8000U + +#define SPICTRL_MODE_ASEL 0x4000U + +#define SPICTRL_MODE_FACT 0x2000U + +#define SPICTRL_MODE_OD 0x1000U + +#define SPICTRL_MODE_CG_SHIFT 7 +#define SPICTRL_MODE_CG_MASK 0xf80U +#define SPICTRL_MODE_CG_GET( _reg ) \ + ( ( ( _reg ) >> 7 ) & 0x1fU ) +#define SPICTRL_MODE_CG( _val ) ( ( _val ) << 7 ) + +#define SPICTRL_MODE_ASELDEL_SHIFT 5 +#define SPICTRL_MODE_ASELDEL_MASK 0x60U +#define SPICTRL_MODE_ASELDEL_GET( _reg ) \ + ( ( ( _reg ) >> 5 ) & 0x3U ) +#define SPICTRL_MODE_ASELDEL( _val ) ( ( _val ) << 5 ) + +#define SPICTRL_MODE_TAC 0x10U + +#define SPICTRL_MODE_TTO 0x8U + +#define SPICTRL_MODE_IGSEL 0x4U + +#define SPICTRL_MODE_CITE 0x2U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPICTRLEVENT Event register (EVENT) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPICTRL_EVENT_TIP 0x80000000U + +#define SPICTRL_EVENT_LT 0x4000U + +#define SPICTRL_EVENT_OV 0x1000U + +#define SPICTRL_EVENT_UN 0x800U + +#define SPICTRL_EVENT_MME 0x400U + +#define SPICTRL_EVENT_NE 0x200U + +#define SPICTRL_EVENT_NF 0x100U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPICTRLMASK Mask register (MASK) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPICTRL_MASK_TIPE 0x80000000U + +#define SPICTRL_MASK_LTE 0x4000U + +#define SPICTRL_MASK_OVE 0x1000U + +#define SPICTRL_MASK_UNE 0x800U + +#define SPICTRL_MASK_MMEE 0x400U + +#define SPICTRL_MASK_NEEE 0x200U + +#define SPICTRL_MASK_NFE 0x100U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPICTRLCMD Command register (CMD) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPICTRL_CMD_LST 0x400000U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPICTRLTX Transmit register (TX) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPICTRL_TX_TDATA_SHIFT 0 +#define SPICTRL_TX_TDATA_MASK 0xffffffffU +#define SPICTRL_TX_TDATA_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define SPICTRL_TX_TDATA( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPICTRLRX Receive register (RX) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPICTRL_RX_RDATA_SHIFT 0 +#define SPICTRL_RX_RDATA_MASK 0xffffffffU +#define SPICTRL_RX_RDATA_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define SPICTRL_RX_RDATA( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPICTRLSLVSEL Slave select register (SLVSEL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPICTRL_SLVSEL_SLVSEL_SHIFT 0 +#define SPICTRL_SLVSEL_SLVSEL_MASK 0x3U +#define SPICTRL_SLVSEL_SLVSEL_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0x3U ) +#define SPICTRL_SLVSEL_SLVSEL( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPICTRLASLVSEL \ + * Automatic slave select register (ASLVSEL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPICTRL_ASLVSEL_ASLVSEL_SHIFT 0 +#define SPICTRL_ASLVSEL_ASLVSEL_MASK 0x3U +#define SPICTRL_ASLVSEL_ASLVSEL_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0x3U ) +#define SPICTRL_ASLVSEL_ASLVSEL( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @brief This structure defines the SPICTRL register block memory map. + */ +typedef struct spictrl { + /** + * @brief See @ref RTEMSDeviceGRLIBSPICTRLCAP. + */ + uint32_t cap; + + uint32_t reserved_4_20[ 7 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPICTRLMODE. + */ + uint32_t mode; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPICTRLEVENT. + */ + uint32_t event; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPICTRLMASK. + */ + uint32_t mask; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPICTRLCMD. + */ + uint32_t cmd; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPICTRLTX. + */ + uint32_t tx; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPICTRLRX. + */ + uint32_t rx; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPICTRLSLVSEL. + */ + uint32_t slvsel; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPICTRLASLVSEL. + */ + uint32_t aslvsel; +} spictrl; + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GRLIB_SPICTRL_REGS_H */ diff --git a/bsps/include/grlib/spwpnp-regs.h b/bsps/include/grlib/spwpnp-regs.h new file mode 100644 index 0000000000..1e81b6d092 --- /dev/null +++ b/bsps/include/grlib/spwpnp-regs.h @@ -0,0 +1,427 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSDeviceGRLIBSPWPNP + * + * @brief This header file defines the SPWPNP register block interface. + */ + +/* + * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file is part of the RTEMS quality process and was automatically + * generated. If you find something that needs to be fixed or + * worded better please post a report or patch to an RTEMS mailing list + * or raise a bug report: + * + * https://www.rtems.org/bugs.html + * + * For information on updating and regenerating please refer to the How-To + * section in the Software Requirements Engineering chapter of the + * RTEMS Software Engineering manual. The manual is provided as a part of + * a release. For development sources please refer to the online + * documentation at: + * + * https://docs.rtems.org + */ + +/* Generated from spec:/dev/grlib/if/spwpnp-header */ + +#ifndef _GRLIB_SPWPNP_REGS_H +#define _GRLIB_SPWPNP_REGS_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Generated from spec:/dev/grlib/if/spwpnp */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWPNP SpaceWire Plug-and-Play + * + * @ingroup RTEMSDeviceGRLIB + * + * @brief This group contains the SpaceWire Plug-and-Play interfaces. + * + * @{ + */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWPNPPNPVEND \ + * SpaceWire Plug-and-Play - Device Vendor and Product ID (PNPVEND) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWPNP_PNPVEND_VEND_SHIFT 16 +#define SPWPNP_PNPVEND_VEND_MASK 0xffff0000U +#define SPWPNP_PNPVEND_VEND_GET( _reg ) \ + ( ( ( _reg ) >> 16 ) & 0xffffU ) +#define SPWPNP_PNPVEND_VEND( _val ) ( ( _val ) << 16 ) + +#define SPWPNP_PNPVEND_PROD_SHIFT 0 +#define SPWPNP_PNPVEND_PROD_MASK 0xffffU +#define SPWPNP_PNPVEND_PROD_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffU ) +#define SPWPNP_PNPVEND_PROD( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWPNPPNPVER \ + * SpaceWire Plug-and-Play - Version (PNPVER) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWPNP_PNPVER_MAJOR_SHIFT 24 +#define SPWPNP_PNPVER_MAJOR_MASK 0xff000000U +#define SPWPNP_PNPVER_MAJOR_GET( _reg ) \ + ( ( ( _reg ) >> 24 ) & 0xffU ) +#define SPWPNP_PNPVER_MAJOR( _val ) ( ( _val ) << 24 ) + +#define SPWPNP_PNPVER_MINOR_SHIFT 16 +#define SPWPNP_PNPVER_MINOR_MASK 0xff0000U +#define SPWPNP_PNPVER_MINOR_GET( _reg ) \ + ( ( ( _reg ) >> 16 ) & 0xffU ) +#define SPWPNP_PNPVER_MINOR( _val ) ( ( _val ) << 16 ) + +#define SPWPNP_PNPVER_PATCH_SHIFT 8 +#define SPWPNP_PNPVER_PATCH_MASK 0xff00U +#define SPWPNP_PNPVER_PATCH_GET( _reg ) \ + ( ( ( _reg ) >> 8 ) & 0xffU ) +#define SPWPNP_PNPVER_PATCH( _val ) ( ( _val ) << 8 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWPNPPNPDEVSTS \ + * SpaceWire Plug-and-Play - Device Status (PNPDEVSTS) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWPNP_PNPDEVSTS_STATUS_SHIFT 0 +#define SPWPNP_PNPDEVSTS_STATUS_MASK 0xffU +#define SPWPNP_PNPDEVSTS_STATUS_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffU ) +#define SPWPNP_PNPDEVSTS_STATUS( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWPNPPNPACTLNK \ + * SpaceWire Plug-and-Play - Active Links (PNPACTLNK) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWPNP_PNPACTLNK_ACTIVE_SHIFT 1 +#define SPWPNP_PNPACTLNK_ACTIVE_MASK 0x1ffeU +#define SPWPNP_PNPACTLNK_ACTIVE_GET( _reg ) \ + ( ( ( _reg ) >> 1 ) & 0xfffU ) +#define SPWPNP_PNPACTLNK_ACTIVE( _val ) ( ( _val ) << 1 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWPNPPNPOA0 \ + * SpaceWire Plug-and-Play - Owner Address 0 (PNPOA0) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWPNP_PNPOA0_RA_SHIFT 0 +#define SPWPNP_PNPOA0_RA_MASK 0xffffffffU +#define SPWPNP_PNPOA0_RA_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define SPWPNP_PNPOA0_RA( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWPNPPNPOA1 \ + * SpaceWire Plug-and-Play - Owner Address 1 (PNPOA1) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWPNP_PNPOA1_RA_SHIFT 0 +#define SPWPNP_PNPOA1_RA_MASK 0xffffffffU +#define SPWPNP_PNPOA1_RA_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define SPWPNP_PNPOA1_RA( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWPNPPNPOA2 \ + * SpaceWire Plug-and-Play - Owner Address 2 (PNPOA2) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWPNP_PNPOA2_RA_SHIFT 0 +#define SPWPNP_PNPOA2_RA_MASK 0xffffffffU +#define SPWPNP_PNPOA2_RA_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define SPWPNP_PNPOA2_RA( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWPNPPNPDEVID \ + * SpaceWire Plug-and-Play - Device ID (PNPDEVID) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWPNP_PNPDEVID_DID_SHIFT 0 +#define SPWPNP_PNPDEVID_DID_MASK 0xffffffffU +#define SPWPNP_PNPDEVID_DID_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define SPWPNP_PNPDEVID_DID( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWPNPPNPUVEND \ + * SpaceWire Plug-and-Play - Unit Vendor and Product ID (PNPUVEND) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWPNP_PNPUVEND_VEND_SHIFT 16 +#define SPWPNP_PNPUVEND_VEND_MASK 0xffff0000U +#define SPWPNP_PNPUVEND_VEND_GET( _reg ) \ + ( ( ( _reg ) >> 16 ) & 0xffffU ) +#define SPWPNP_PNPUVEND_VEND( _val ) ( ( _val ) << 16 ) + +#define SPWPNP_PNPUVEND_PROD_SHIFT 0 +#define SPWPNP_PNPUVEND_PROD_MASK 0xffffU +#define SPWPNP_PNPUVEND_PROD_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffU ) +#define SPWPNP_PNPUVEND_PROD( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWPNPPNPUSN \ + * SpaceWire Plug-and-Play - Unit Serial Number (PNPUSN) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWPNP_PNPUSN_USN_SHIFT 0 +#define SPWPNP_PNPUSN_USN_MASK 0xffffffffU +#define SPWPNP_PNPUSN_USN_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define SPWPNP_PNPUSN_USN( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWPNPPNPVSTRL \ + * SpaceWire Plug-and-Play - Vendor String Length (PNPVSTRL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWPNP_PNPVSTRL_LEN_SHIFT 0 +#define SPWPNP_PNPVSTRL_LEN_MASK 0x7fffU +#define SPWPNP_PNPVSTRL_LEN_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0x7fffU ) +#define SPWPNP_PNPVSTRL_LEN( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWPNPPNPPSTRL \ + * SpaceWire Plug-and-Play - Product String Length (PNPPSTRL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWPNP_PNPPSTRL_LEN_SHIFT 0 +#define SPWPNP_PNPPSTRL_LEN_MASK 0x7fffU +#define SPWPNP_PNPPSTRL_LEN_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0x7fffU ) +#define SPWPNP_PNPPSTRL_LEN( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWPNPPNPPCNT \ + * SpaceWire Plug-and-Play - Protocol Count (PNPPCNT) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWPNP_PNPPCNT_PC_SHIFT 0 +#define SPWPNP_PNPPCNT_PC_MASK 0x1fU +#define SPWPNP_PNPPCNT_PC_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0x1fU ) +#define SPWPNP_PNPPCNT_PC( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWPNPPNPACNT \ + * SpaceWire Plug-and-Play - Application Count (PNPACNT) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWPNP_PNPACNT_AC_SHIFT 0 +#define SPWPNP_PNPACNT_AC_MASK 0xffU +#define SPWPNP_PNPACNT_AC_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffU ) +#define SPWPNP_PNPACNT_AC( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @brief This set of defines the SpaceWire Plug-and-Play address map. + */ +typedef struct spwpnp { + /** + * @brief See @ref RTEMSDeviceGRLIBSPWPNPPNPVEND. + */ + uint32_t pnpvend; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWPNPPNPVER. + */ + uint32_t pnpver; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWPNPPNPDEVSTS. + */ + uint32_t pnpdevsts; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWPNPPNPACTLNK. + */ + uint32_t pnpactlnk; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWPNPPNPOA0. + */ + uint32_t pnpoa0; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWPNPPNPOA1. + */ + uint32_t pnpoa1; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWPNPPNPOA2. + */ + uint32_t pnpoa2; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWPNPPNPDEVID. + */ + uint32_t pnpdevid; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWPNPPNPUVEND. + */ + uint32_t pnpuvend; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWPNPPNPUSN. + */ + uint32_t pnpusn; + + uint16_t reserved_e_4000[ 8185 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWPNPPNPVSTRL. + */ + uint32_t pnpvstrl; + + uint32_t reserved_4004_6000[ 2047 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWPNPPNPPSTRL. + */ + uint32_t pnppstrl; + + uint32_t reserved_6004_8000[ 2047 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWPNPPNPPCNT. + */ + uint32_t pnppcnt; + + uint32_t reserved_8004_c000[ 4095 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWPNPPNPACNT. + */ + uint32_t pnpacnt; +} spwpnp; + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GRLIB_SPWPNP_REGS_H */ diff --git a/bsps/include/grlib/spwrmap-regs.h b/bsps/include/grlib/spwrmap-regs.h new file mode 100644 index 0000000000..8f6d4b5282 --- /dev/null +++ b/bsps/include/grlib/spwrmap-regs.h @@ -0,0 +1,1114 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSDeviceGRLIBSPWMAP + * + * @brief This header file defines the SPWRMAP register block interface. + */ + +/* + * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file is part of the RTEMS quality process and was automatically + * generated. If you find something that needs to be fixed or + * worded better please post a report or patch to an RTEMS mailing list + * or raise a bug report: + * + * https://www.rtems.org/bugs.html + * + * For information on updating and regenerating please refer to the How-To + * section in the Software Requirements Engineering chapter of the + * RTEMS Software Engineering manual. The manual is provided as a part of + * a release. For development sources please refer to the online + * documentation at: + * + * https://docs.rtems.org + */ + +/* Generated from spec:/dev/grlib/if/spwrmap-header */ + +#ifndef _GRLIB_SPWRMAP_REGS_H +#define _GRLIB_SPWRMAP_REGS_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Generated from spec:/dev/grlib/if/spwrmap */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWMAP \ + * SpaceWire Remote Memory Access Protocol (RMAP) + * + * @ingroup RTEMSDeviceGRLIB + * + * @brief This group contains the SpaceWire Remote Memory Access Protocol + * (RMAP) interfaces. + * + * @{ + */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWMAPRTPMAP \ + * Routing table port mapping, addresses 1-12 and 32-255 (RTPMAP) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWRMAP_RTPMAP_PE_SHIFT 1 +#define SPWRMAP_RTPMAP_PE_MASK 0x1ffeU +#define SPWRMAP_RTPMAP_PE_GET( _reg ) \ + ( ( ( _reg ) >> 1 ) & 0xfffU ) +#define SPWRMAP_RTPMAP_PE( _val ) ( ( _val ) << 1 ) + +#define SPWRMAP_RTPMAP_PD 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWMAPRTACTRL \ + * Routing table address control, addresses 1-12 and 32-255 (RTACTRL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWRMAP_RTACTRL_SR 0x8U + +#define SPWRMAP_RTACTRL_EN 0x4U + +#define SPWRMAP_RTACTRL_PR 0x2U + +#define SPWRMAP_RTACTRL_HD 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWMAPPCTRLCFG \ + * Port control, port 0 (configuration port) (PCTRLCFG) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWRMAP_PCTRLCFG_PL 0x20000U + +#define SPWRMAP_PCTRLCFG_TS 0x10000U + +#define SPWRMAP_PCTRLCFG_TR 0x200U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWMAPPCTRL \ + * Port control, ports 1-12 (SpaceWire ports and AMBA ports) (PCTRL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWRMAP_PCTRL_RD_SHIFT 24 +#define SPWRMAP_PCTRL_RD_MASK 0xff000000U +#define SPWRMAP_PCTRL_RD_GET( _reg ) \ + ( ( ( _reg ) >> 24 ) & 0xffU ) +#define SPWRMAP_PCTRL_RD( _val ) ( ( _val ) << 24 ) + +#define SPWRMAP_PCTRL_ST 0x200000U + +#define SPWRMAP_PCTRL_SR 0x100000U + +#define SPWRMAP_PCTRL_AD 0x80000U + +#define SPWRMAP_PCTRL_LR 0x40000U + +#define SPWRMAP_PCTRL_PL 0x20000U + +#define SPWRMAP_PCTRL_TS 0x10000U + +#define SPWRMAP_PCTRL_IC 0x8000U + +#define SPWRMAP_PCTRL_ET 0x4000U + +#define SPWRMAP_PCTRL_DI 0x400U + +#define SPWRMAP_PCTRL_TR 0x200U + +#define SPWRMAP_PCTRL_PR 0x100U + +#define SPWRMAP_PCTRL_TF 0x80U + +#define SPWRMAP_PCTRL_RS 0x40U + +#define SPWRMAP_PCTRL_TE 0x20U + +#define SPWRMAP_PCTRL_CE 0x8U + +#define SPWRMAP_PCTRL_AS 0x4U + +#define SPWRMAP_PCTRL_LS 0x2U + +#define SPWRMAP_PCTRL_LD 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWMAPPSTSCFG \ + * Port status, port 0 (configuration port) (PSTSCFG) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWRMAP_PSTSCFG_EO 0x80000000U + +#define SPWRMAP_PSTSCFG_EE 0x40000000U + +#define SPWRMAP_PSTSCFG_PL 0x20000000U + +#define SPWRMAP_PSTSCFG_TT 0x10000000U + +#define SPWRMAP_PSTSCFG_PT 0x8000000U + +#define SPWRMAP_PSTSCFG_HC 0x4000000U + +#define SPWRMAP_PSTSCFG_PI 0x2000000U + +#define SPWRMAP_PSTSCFG_CE 0x1000000U + +#define SPWRMAP_PSTSCFG_EC_SHIFT 20 +#define SPWRMAP_PSTSCFG_EC_MASK 0xf00000U +#define SPWRMAP_PSTSCFG_EC_GET( _reg ) \ + ( ( ( _reg ) >> 20 ) & 0xfU ) +#define SPWRMAP_PSTSCFG_EC( _val ) ( ( _val ) << 20 ) + +#define SPWRMAP_PSTSCFG_TS 0x40000U + +#define SPWRMAP_PSTSCFG_ME 0x20000U + +#define SPWRMAP_PSTSCFG_IP_SHIFT 7 +#define SPWRMAP_PSTSCFG_IP_MASK 0xf80U +#define SPWRMAP_PSTSCFG_IP_GET( _reg ) \ + ( ( ( _reg ) >> 7 ) & 0x1fU ) +#define SPWRMAP_PSTSCFG_IP( _val ) ( ( _val ) << 7 ) + +#define SPWRMAP_PSTSCFG_CP 0x10U + +#define SPWRMAP_PSTSCFG_PC_SHIFT 0 +#define SPWRMAP_PSTSCFG_PC_MASK 0xfU +#define SPWRMAP_PSTSCFG_PC_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xfU ) +#define SPWRMAP_PSTSCFG_PC( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWMAPPSTS \ + * Port status, ports 1-12 (SpaceWire ports and AMBA ports) (PSTS) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWRMAP_PSTS_PT_SHIFT 30 +#define SPWRMAP_PSTS_PT_MASK 0xc0000000U +#define SPWRMAP_PSTS_PT_GET( _reg ) \ + ( ( ( _reg ) >> 30 ) & 0x3U ) +#define SPWRMAP_PSTS_PT( _val ) ( ( _val ) << 30 ) + +#define SPWRMAP_PSTS_PL 0x20000000U + +#define SPWRMAP_PSTS_TT 0x10000000U + +#define SPWRMAP_PSTS_RS 0x8000000U + +#define SPWRMAP_PSTS_SR 0x4000000U + +#define SPWRMAP_PSTS_LR 0x400000U + +#define SPWRMAP_PSTS_SP 0x200000U + +#define SPWRMAP_PSTS_AC 0x100000U + +#define SPWRMAP_PSTS_TS 0x40000U + +#define SPWRMAP_PSTS_ME 0x20000U + +#define SPWRMAP_PSTS_TF 0x10000U + +#define SPWRMAP_PSTS_RE 0x8000U + +#define SPWRMAP_PSTS_LS_SHIFT 12 +#define SPWRMAP_PSTS_LS_MASK 0x7000U +#define SPWRMAP_PSTS_LS_GET( _reg ) \ + ( ( ( _reg ) >> 12 ) & 0x7U ) +#define SPWRMAP_PSTS_LS( _val ) ( ( _val ) << 12 ) + +#define SPWRMAP_PSTS_IP_SHIFT 7 +#define SPWRMAP_PSTS_IP_MASK 0xf80U +#define SPWRMAP_PSTS_IP_GET( _reg ) \ + ( ( ( _reg ) >> 7 ) & 0x1fU ) +#define SPWRMAP_PSTS_IP( _val ) ( ( _val ) << 7 ) + +#define SPWRMAP_PSTS_PR 0x40U + +#define SPWRMAP_PSTS_PB 0x20U + +#define SPWRMAP_PSTS_IA 0x10U + +#define SPWRMAP_PSTS_CE 0x8U + +#define SPWRMAP_PSTS_ER 0x4U + +#define SPWRMAP_PSTS_DE 0x2U + +#define SPWRMAP_PSTS_PE 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWMAPPTIMER \ + * Port timer reload, ports 0-12 (PTIMER) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWRMAP_PTIMER_RL_SHIFT 0 +#define SPWRMAP_PTIMER_RL_MASK 0xffffU +#define SPWRMAP_PTIMER_RL_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffU ) +#define SPWRMAP_PTIMER_RL( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWMAPPCTRL2CFG \ + * Port control 2, port 0 (configuration port) (PCTRL2CFG) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWRMAP_PCTRL2CFG_SM_SHIFT 24 +#define SPWRMAP_PCTRL2CFG_SM_MASK 0xff000000U +#define SPWRMAP_PCTRL2CFG_SM_GET( _reg ) \ + ( ( ( _reg ) >> 24 ) & 0xffU ) +#define SPWRMAP_PCTRL2CFG_SM( _val ) ( ( _val ) << 24 ) + +#define SPWRMAP_PCTRL2CFG_SV_SHIFT 16 +#define SPWRMAP_PCTRL2CFG_SV_MASK 0xff0000U +#define SPWRMAP_PCTRL2CFG_SV_GET( _reg ) \ + ( ( ( _reg ) >> 16 ) & 0xffU ) +#define SPWRMAP_PCTRL2CFG_SV( _val ) ( ( _val ) << 16 ) + +#define SPWRMAP_PCTRL2CFG_OR 0x8000U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWMAPPCTRL2 \ + * Port control 2, ports 1-12 (SpaceWire ports and AMBA ports) (PCTRL2) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWRMAP_PCTRL2_SM_SHIFT 24 +#define SPWRMAP_PCTRL2_SM_MASK 0xff000000U +#define SPWRMAP_PCTRL2_SM_GET( _reg ) \ + ( ( ( _reg ) >> 24 ) & 0xffU ) +#define SPWRMAP_PCTRL2_SM( _val ) ( ( _val ) << 24 ) + +#define SPWRMAP_PCTRL2_SV_SHIFT 16 +#define SPWRMAP_PCTRL2_SV_MASK 0xff0000U +#define SPWRMAP_PCTRL2_SV_GET( _reg ) \ + ( ( ( _reg ) >> 16 ) & 0xffU ) +#define SPWRMAP_PCTRL2_SV( _val ) ( ( _val ) << 16 ) + +#define SPWRMAP_PCTRL2_OR 0x8000U + +#define SPWRMAP_PCTRL2_UR 0x4000U + +#define SPWRMAP_PCTRL2_AT 0x1000U + +#define SPWRMAP_PCTRL2_AR 0x800U + +#define SPWRMAP_PCTRL2_IT 0x400U + +#define SPWRMAP_PCTRL2_IR 0x200U + +#define SPWRMAP_PCTRL2_SD_SHIFT 1 +#define SPWRMAP_PCTRL2_SD_MASK 0x3eU +#define SPWRMAP_PCTRL2_SD_GET( _reg ) \ + ( ( ( _reg ) >> 1 ) & 0x1fU ) +#define SPWRMAP_PCTRL2_SD( _val ) ( ( _val ) << 1 ) + +#define SPWRMAP_PCTRL2_SC 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWMAPRTRCFG \ + * Router configuration / status (RTRCFG) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWRMAP_RTRCFG_SP_SHIFT 27 +#define SPWRMAP_RTRCFG_SP_MASK 0xf8000000U +#define SPWRMAP_RTRCFG_SP_GET( _reg ) \ + ( ( ( _reg ) >> 27 ) & 0x1fU ) +#define SPWRMAP_RTRCFG_SP( _val ) ( ( _val ) << 27 ) + +#define SPWRMAP_RTRCFG_AP_SHIFT 22 +#define SPWRMAP_RTRCFG_AP_MASK 0x7c00000U +#define SPWRMAP_RTRCFG_AP_GET( _reg ) \ + ( ( ( _reg ) >> 22 ) & 0x1fU ) +#define SPWRMAP_RTRCFG_AP( _val ) ( ( _val ) << 22 ) + +#define SPWRMAP_RTRCFG_SR 0x8000U + +#define SPWRMAP_RTRCFG_PE 0x4000U + +#define SPWRMAP_RTRCFG_IC 0x2000U + +#define SPWRMAP_RTRCFG_IS 0x1000U + +#define SPWRMAP_RTRCFG_IP 0x800U + +#define SPWRMAP_RTRCFG_AI 0x400U + +#define SPWRMAP_RTRCFG_AT 0x200U + +#define SPWRMAP_RTRCFG_IE 0x100U + +#define SPWRMAP_RTRCFG_RE 0x80U + +#define SPWRMAP_RTRCFG_EE 0x40U + +#define SPWRMAP_RTRCFG_SA 0x10U + +#define SPWRMAP_RTRCFG_TF 0x8U + +#define SPWRMAP_RTRCFG_ME 0x4U + +#define SPWRMAP_RTRCFG_TA 0x2U + +#define SPWRMAP_RTRCFG_PP 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWMAPTC Time-code (TC) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWRMAP_TC_RE 0x200U + +#define SPWRMAP_TC_EN 0x100U + +#define SPWRMAP_TC_CF_SHIFT 6 +#define SPWRMAP_TC_CF_MASK 0xc0U +#define SPWRMAP_TC_CF_GET( _reg ) \ + ( ( ( _reg ) >> 6 ) & 0x3U ) +#define SPWRMAP_TC_CF( _val ) ( ( _val ) << 6 ) + +#define SPWRMAP_TC_TC_SHIFT 0 +#define SPWRMAP_TC_TC_MASK 0x3fU +#define SPWRMAP_TC_TC_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0x3fU ) +#define SPWRMAP_TC_TC( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWMAPVER Version / instance ID (VER) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWRMAP_VER_MA_SHIFT 24 +#define SPWRMAP_VER_MA_MASK 0xff000000U +#define SPWRMAP_VER_MA_GET( _reg ) \ + ( ( ( _reg ) >> 24 ) & 0xffU ) +#define SPWRMAP_VER_MA( _val ) ( ( _val ) << 24 ) + +#define SPWRMAP_VER_MI_SHIFT 16 +#define SPWRMAP_VER_MI_MASK 0xff0000U +#define SPWRMAP_VER_MI_GET( _reg ) \ + ( ( ( _reg ) >> 16 ) & 0xffU ) +#define SPWRMAP_VER_MI( _val ) ( ( _val ) << 16 ) + +#define SPWRMAP_VER_PA_SHIFT 8 +#define SPWRMAP_VER_PA_MASK 0xff00U +#define SPWRMAP_VER_PA_GET( _reg ) \ + ( ( ( _reg ) >> 8 ) & 0xffU ) +#define SPWRMAP_VER_PA( _val ) ( ( _val ) << 8 ) + +#define SPWRMAP_VER_ID_SHIFT 0 +#define SPWRMAP_VER_ID_MASK 0xffU +#define SPWRMAP_VER_ID_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffU ) +#define SPWRMAP_VER_ID( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWMAPIDIV Initialization divisor (IDIV) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWRMAP_IDIV_ID_SHIFT 0 +#define SPWRMAP_IDIV_ID_MASK 0xffU +#define SPWRMAP_IDIV_ID_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffU ) +#define SPWRMAP_IDIV_ID( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWMAPCFGWE \ + * Configuration port write enable (CFGWE) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWRMAP_CFGWE_WE 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWMAPPRESCALER Timer prescaler reload (PRESCALER) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWRMAP_PRESCALER_RL_SHIFT 0 +#define SPWRMAP_PRESCALER_RL_MASK 0xffffU +#define SPWRMAP_PRESCALER_RL_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffU ) +#define SPWRMAP_PRESCALER_RL( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWMAPIMASK Interrupt mask (IMASK) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWRMAP_IMASK_PE 0x400U + +#define SPWRMAP_IMASK_SR 0x200U + +#define SPWRMAP_IMASK_RS 0x100U + +#define SPWRMAP_IMASK_TT 0x80U + +#define SPWRMAP_IMASK_PL 0x40U + +#define SPWRMAP_IMASK_TS 0x20U + +#define SPWRMAP_IMASK_AC 0x10U + +#define SPWRMAP_IMASK_RE 0x8U + +#define SPWRMAP_IMASK_IA 0x4U + +#define SPWRMAP_IMASK_LE 0x2U + +#define SPWRMAP_IMASK_ME 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWMAPIPMASK Interrupt port mask (IPMASK) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWRMAP_IPMASK_IE_SHIFT 0 +#define SPWRMAP_IPMASK_IE_MASK 0xfffffU +#define SPWRMAP_IPMASK_IE_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xfffffU ) +#define SPWRMAP_IPMASK_IE( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWMAPPIP Port interrupt pending (PIP) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWRMAP_PIP_IP_SHIFT 0 +#define SPWRMAP_PIP_IP_MASK 0xfffffU +#define SPWRMAP_PIP_IP_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xfffffU ) +#define SPWRMAP_PIP_IP( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWMAPICODEGEN \ + * Interrupt code generation (ICODEGEN) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWRMAP_ICODEGEN_HI 0x200000U + +#define SPWRMAP_ICODEGEN_UA 0x100000U + +#define SPWRMAP_ICODEGEN_AH 0x80000U + +#define SPWRMAP_ICODEGEN_IT 0x40000U + +#define SPWRMAP_ICODEGEN_TE 0x20000U + +#define SPWRMAP_ICODEGEN_EN 0x10000U + +#define SPWRMAP_ICODEGEN_IN_SHIFT 0 +#define SPWRMAP_ICODEGEN_IN_MASK 0x3fU +#define SPWRMAP_ICODEGEN_IN_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0x3fU ) +#define SPWRMAP_ICODEGEN_IN( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWMAPISR0 \ + * Interrupt code distribution ISR register, interrupt 0-31 (ISR0) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWRMAP_ISR0_IB_SHIFT 0 +#define SPWRMAP_ISR0_IB_MASK 0xffffffffU +#define SPWRMAP_ISR0_IB_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define SPWRMAP_ISR0_IB( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWMAPISR1 \ + * Interrupt code distribution ISR register, interrupt 32-63 (ISR1) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWRMAP_ISR1_IB_SHIFT 0 +#define SPWRMAP_ISR1_IB_MASK 0xffffffffU +#define SPWRMAP_ISR1_IB_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define SPWRMAP_ISR1_IB( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWMAPISRTIMER \ + * Interrupt code distribution ISR timer reload (ISRTIMER) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWRMAP_ISRTIMER_RL_SHIFT 0 +#define SPWRMAP_ISRTIMER_RL_MASK 0xffffU +#define SPWRMAP_ISRTIMER_RL_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffU ) +#define SPWRMAP_ISRTIMER_RL( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWMAPAITIMER \ + * Interrupt code distribution ACK-to-INT timer reload (AITIMER) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWRMAP_AITIMER_RL_SHIFT 0 +#define SPWRMAP_AITIMER_RL_MASK 0xffffU +#define SPWRMAP_AITIMER_RL_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffU ) +#define SPWRMAP_AITIMER_RL( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWMAPISRCTIMER \ + * Interrupt code distribution ISR change timer reload (ISRCTIMER) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWRMAP_ISRCTIMER_RL_SHIFT 0 +#define SPWRMAP_ISRCTIMER_RL_MASK 0x1fU +#define SPWRMAP_ISRCTIMER_RL_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0x1fU ) +#define SPWRMAP_ISRCTIMER_RL( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWMAPLRUNSTAT Link running status (LRUNSTAT) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWRMAP_LRUNSTAT_LR_SHIFT 1 +#define SPWRMAP_LRUNSTAT_LR_MASK 0x7fffeU +#define SPWRMAP_LRUNSTAT_LR_GET( _reg ) \ + ( ( ( _reg ) >> 1 ) & 0x3ffffU ) +#define SPWRMAP_LRUNSTAT_LR( _val ) ( ( _val ) << 1 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWMAPCAP Capability (CAP) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWRMAP_CAP_AF_SHIFT 24 +#define SPWRMAP_CAP_AF_MASK 0x3000000U +#define SPWRMAP_CAP_AF_GET( _reg ) \ + ( ( ( _reg ) >> 24 ) & 0x3U ) +#define SPWRMAP_CAP_AF( _val ) ( ( _val ) << 24 ) + +#define SPWRMAP_CAP_PF_SHIFT 20 +#define SPWRMAP_CAP_PF_MASK 0x700000U +#define SPWRMAP_CAP_PF_GET( _reg ) \ + ( ( ( _reg ) >> 20 ) & 0x7U ) +#define SPWRMAP_CAP_PF( _val ) ( ( _val ) << 20 ) + +#define SPWRMAP_CAP_RM_SHIFT 16 +#define SPWRMAP_CAP_RM_MASK 0x70000U +#define SPWRMAP_CAP_RM_GET( _reg ) \ + ( ( ( _reg ) >> 16 ) & 0x7U ) +#define SPWRMAP_CAP_RM( _val ) ( ( _val ) << 16 ) + +#define SPWRMAP_CAP_AS 0x4000U + +#define SPWRMAP_CAP_AX 0x2000U + +#define SPWRMAP_CAP_DP 0x1000U + +#define SPWRMAP_CAP_ID 0x800U + +#define SPWRMAP_CAP_SD 0x400U + +#define SPWRMAP_CAP_PC_SHIFT 5 +#define SPWRMAP_CAP_PC_MASK 0x3e0U +#define SPWRMAP_CAP_PC_GET( _reg ) \ + ( ( ( _reg ) >> 5 ) & 0x1fU ) +#define SPWRMAP_CAP_PC( _val ) ( ( _val ) << 5 ) + +#define SPWRMAP_CAP_CC_SHIFT 0 +#define SPWRMAP_CAP_CC_MASK 0x1fU +#define SPWRMAP_CAP_CC_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0x1fU ) +#define SPWRMAP_CAP_CC( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWMAPPNPVEND \ + * SpaceWire Plug-and-Play - Device Vendor and Product ID (PNPVEND) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWRMAP_PNPVEND_VI_SHIFT 16 +#define SPWRMAP_PNPVEND_VI_MASK 0xffff0000U +#define SPWRMAP_PNPVEND_VI_GET( _reg ) \ + ( ( ( _reg ) >> 16 ) & 0xffffU ) +#define SPWRMAP_PNPVEND_VI( _val ) ( ( _val ) << 16 ) + +#define SPWRMAP_PNPVEND_PI_SHIFT 0 +#define SPWRMAP_PNPVEND_PI_MASK 0x3ffffffU +#define SPWRMAP_PNPVEND_PI_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0x3ffffffU ) +#define SPWRMAP_PNPVEND_PI( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWMAPPNPUVEND \ + * SpaceWire Plug-and-Play - Unit Vendor and Product ID (PNPUVEND) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWRMAP_PNPUVEND_VI_SHIFT 16 +#define SPWRMAP_PNPUVEND_VI_MASK 0xffff0000U +#define SPWRMAP_PNPUVEND_VI_GET( _reg ) \ + ( ( ( _reg ) >> 16 ) & 0xffffU ) +#define SPWRMAP_PNPUVEND_VI( _val ) ( ( _val ) << 16 ) + +#define SPWRMAP_PNPUVEND_PI_SHIFT 0 +#define SPWRMAP_PNPUVEND_PI_MASK 0x3ffffffU +#define SPWRMAP_PNPUVEND_PI_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0x3ffffffU ) +#define SPWRMAP_PNPUVEND_PI( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWMAPPNPUSN \ + * SpaceWire Plug-and-Play - Unit Serial Number (PNPUSN) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWRMAP_PNPUSN_SN_SHIFT 0 +#define SPWRMAP_PNPUSN_SN_MASK 0xffffffffU +#define SPWRMAP_PNPUSN_SN_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define SPWRMAP_PNPUSN_SN( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWMAPMAXPLEN \ + * Maximum packet length, ports 0-12 (MAXPLEN) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWRMAP_MAXPLEN_ML_SHIFT 0 +#define SPWRMAP_MAXPLEN_ML_MASK 0x1ffffffU +#define SPWRMAP_MAXPLEN_ML_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0x1ffffffU ) +#define SPWRMAP_MAXPLEN_ML( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWMAPCREDCNT Credit counter, ports 1-8 (CREDCNT) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWRMAP_CREDCNT_OC_SHIFT 6 +#define SPWRMAP_CREDCNT_OC_MASK 0xfc0U +#define SPWRMAP_CREDCNT_OC_GET( _reg ) \ + ( ( ( _reg ) >> 6 ) & 0x3fU ) +#define SPWRMAP_CREDCNT_OC( _val ) ( ( _val ) << 6 ) + +#define SPWRMAP_CREDCNT_IC_SHIFT 0 +#define SPWRMAP_CREDCNT_IC_MASK 0x3fU +#define SPWRMAP_CREDCNT_IC_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0x3fU ) +#define SPWRMAP_CREDCNT_IC( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWMAPRTCOMB \ + * Routing table, combined port mapping and address control, addresses 1-255 (RTCOMB) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWRMAP_RTCOMB_SR 0x80000000U + +#define SPWRMAP_RTCOMB_EN 0x40000000U + +#define SPWRMAP_RTCOMB_PR 0x20000000U + +#define SPWRMAP_RTCOMB_HD 0x10000000U + +#define SPWRMAP_RTCOMB_PE_SHIFT 1 +#define SPWRMAP_RTCOMB_PE_MASK 0xffffeU +#define SPWRMAP_RTCOMB_PE_GET( _reg ) \ + ( ( ( _reg ) >> 1 ) & 0x7ffffU ) +#define SPWRMAP_RTCOMB_PE( _val ) ( ( _val ) << 1 ) + +#define SPWRMAP_RTCOMB_PD 0x1U + +/** @} */ + +/** + * @brief This set of defines the SpaceWire Remote Memory Access Protocol + * (RMAP) address map. + */ +typedef struct spwrmap { + uint32_t reserved_0_4; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWMAPRTPMAP. + */ + uint32_t rtpmap; + + uint32_t reserved_8_404[ 255 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWMAPRTACTRL. + */ + uint32_t rtactrl; + + uint32_t reserved_408_800[ 254 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWMAPPCTRLCFG. + */ + uint32_t pctrlcfg; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWMAPPCTRL. + */ + uint32_t pctrl; + + uint32_t reserved_808_880[ 30 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWMAPPSTSCFG. + */ + uint32_t pstscfg; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWMAPPSTS. + */ + uint32_t psts; + + uint32_t reserved_888_900[ 30 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWMAPPTIMER. + */ + uint32_t ptimer; + + uint32_t reserved_904_980[ 31 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWMAPPCTRL2CFG. + */ + uint32_t pctrl2cfg; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWMAPPCTRL2. + */ + uint32_t pctrl2; + + uint32_t reserved_988_a00[ 30 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWMAPRTRCFG. + */ + uint32_t rtrcfg; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWMAPTC. + */ + uint32_t tc; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWMAPVER. + */ + uint32_t ver; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWMAPIDIV. + */ + uint32_t idiv; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWMAPCFGWE. + */ + uint32_t cfgwe; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWMAPPRESCALER. + */ + uint32_t prescaler; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWMAPIMASK. + */ + uint32_t imask; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWMAPIPMASK. + */ + uint32_t ipmask; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWMAPPIP. + */ + uint32_t pip; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWMAPICODEGEN. + */ + uint32_t icodegen; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWMAPISR0. + */ + uint32_t isr0; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWMAPISR1. + */ + uint32_t isr1; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWMAPISRTIMER. + */ + uint32_t isrtimer; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWMAPAITIMER. + */ + uint32_t aitimer; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWMAPISRCTIMER. + */ + uint32_t isrctimer; + + uint32_t reserved_a3c_a40; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWMAPLRUNSTAT. + */ + uint32_t lrunstat; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWMAPCAP. + */ + uint32_t cap; + + uint32_t reserved_a48_a50[ 2 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWMAPPNPVEND. + */ + uint32_t pnpvend; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWMAPPNPUVEND. + */ + uint32_t pnpuvend; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWMAPPNPUSN. + */ + uint32_t pnpusn; + + uint32_t reserved_a5c_e00[ 233 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWMAPMAXPLEN. + */ + uint32_t maxplen; + + uint32_t reserved_e04_e84[ 32 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWMAPCREDCNT. + */ + uint32_t credcnt; + + uint32_t reserved_e88_1004[ 95 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWMAPRTCOMB. + */ + uint32_t rtcomb; +} spwrmap; + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GRLIB_SPWRMAP_REGS_H */ diff --git a/bsps/include/grlib/spwtdp-regs.h b/bsps/include/grlib/spwtdp-regs.h new file mode 100644 index 0000000000..f06a459a5d --- /dev/null +++ b/bsps/include/grlib/spwtdp-regs.h @@ -0,0 +1,981 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSDeviceGRLIBSPWTDP + * + * @brief This header file defines the SPWTDP register block interface. + */ + +/* + * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file is part of the RTEMS quality process and was automatically + * generated. If you find something that needs to be fixed or + * worded better please post a report or patch to an RTEMS mailing list + * or raise a bug report: + * + * https://www.rtems.org/bugs.html + * + * For information on updating and regenerating please refer to the How-To + * section in the Software Requirements Engineering chapter of the + * RTEMS Software Engineering manual. The manual is provided as a part of + * a release. For development sources please refer to the online + * documentation at: + * + * https://docs.rtems.org + */ + +/* Generated from spec:/dev/grlib/if/spwtdp-header */ + +#ifndef _GRLIB_SPWTDP_REGS_H +#define _GRLIB_SPWTDP_REGS_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Generated from spec:/dev/grlib/if/spwtdp */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDP SPWTDP + * + * @ingroup RTEMSDeviceGRLIB + * + * @brief This group contains the SPWTDP interfaces. + * + * @{ + */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPCONF0 Configuration 0 (CONF0) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_CONF0_JE 0x1000000U + +#define SPWTDP_CONF0_ST 0x200000U + +#define SPWTDP_CONF0_EP 0x100000U + +#define SPWTDP_CONF0_ET 0x80000U + +#define SPWTDP_CONF0_SP 0x40000U + +#define SPWTDP_CONF0_SE 0x20000U + +#define SPWTDP_CONF0_LE 0x10000U + +#define SPWTDP_CONF0_AE 0x8000U + +#define SPWTDP_CONF0_MAPPING_SHIFT 8 +#define SPWTDP_CONF0_MAPPING_MASK 0x1f00U +#define SPWTDP_CONF0_MAPPING_GET( _reg ) \ + ( ( ( _reg ) >> 8 ) & 0x1fU ) +#define SPWTDP_CONF0_MAPPING( _val ) ( ( _val ) << 8 ) + +#define SPWTDP_CONF0_TD 0x80U + +#define SPWTDP_CONF0_MU 0x40U + +#define SPWTDP_CONF0_SEL_SHIFT 4 +#define SPWTDP_CONF0_SEL_MASK 0x30U +#define SPWTDP_CONF0_SEL_GET( _reg ) \ + ( ( ( _reg ) >> 4 ) & 0x3U ) +#define SPWTDP_CONF0_SEL( _val ) ( ( _val ) << 4 ) + +#define SPWTDP_CONF0_ME 0x8U + +#define SPWTDP_CONF0_RE 0x4U + +#define SPWTDP_CONF0_TE 0x2U + +#define SPWTDP_CONF0_RS 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPCONF3 Configuration 3 (CONF3) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_CONF3_STM_SHIFT 16 +#define SPWTDP_CONF3_STM_MASK 0x3f0000U +#define SPWTDP_CONF3_STM_GET( _reg ) \ + ( ( ( _reg ) >> 16 ) & 0x3fU ) +#define SPWTDP_CONF3_STM( _val ) ( ( _val ) << 16 ) + +#define SPWTDP_CONF3_DI64R 0x2000U + +#define SPWTDP_CONF3_DI64T 0x1000U + +#define SPWTDP_CONF3_DI64 0x800U + +#define SPWTDP_CONF3_DI 0x400U + +#define SPWTDP_CONF3_INRX_SHIFT 5 +#define SPWTDP_CONF3_INRX_MASK 0x3e0U +#define SPWTDP_CONF3_INRX_GET( _reg ) \ + ( ( ( _reg ) >> 5 ) & 0x1fU ) +#define SPWTDP_CONF3_INRX( _val ) ( ( _val ) << 5 ) + +#define SPWTDP_CONF3_INTX_SHIFT 0 +#define SPWTDP_CONF3_INTX_MASK 0x1fU +#define SPWTDP_CONF3_INTX_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0x1fU ) +#define SPWTDP_CONF3_INTX( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPCTRL Control (CTRL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_CTRL_NC 0x80000000U + +#define SPWTDP_CTRL_IS 0x40000000U + +#define SPWTDP_CTRL_SPWTC_SHIFT 16 +#define SPWTDP_CTRL_SPWTC_MASK 0xff0000U +#define SPWTDP_CTRL_SPWTC_GET( _reg ) \ + ( ( ( _reg ) >> 16 ) & 0xffU ) +#define SPWTDP_CTRL_SPWTC( _val ) ( ( _val ) << 16 ) + +#define SPWTDP_CTRL_CPF_SHIFT 0 +#define SPWTDP_CTRL_CPF_MASK 0xffffU +#define SPWTDP_CTRL_CPF_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffU ) +#define SPWTDP_CTRL_CPF( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPCET0 Command Elapsed Time 0 (CET0) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_CET0_CET0_SHIFT 0 +#define SPWTDP_CET0_CET0_MASK 0xffffffffU +#define SPWTDP_CET0_CET0_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define SPWTDP_CET0_CET0( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPCET1 Command Elapsed Time 1 (CET1) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_CET1_CET1_SHIFT 0 +#define SPWTDP_CET1_CET1_MASK 0xffffffffU +#define SPWTDP_CET1_CET1_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define SPWTDP_CET1_CET1( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPCET2 Command Elapsed Time 2 (CET2) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_CET2_CET2_SHIFT 0 +#define SPWTDP_CET2_CET2_MASK 0xffffffffU +#define SPWTDP_CET2_CET2_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define SPWTDP_CET2_CET2( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPCET0 Command Elapsed Time 3 (CET0) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_CET0_CET3_SHIFT 0 +#define SPWTDP_CET0_CET3_MASK 0xffffffffU +#define SPWTDP_CET0_CET3_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define SPWTDP_CET0_CET3( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPCET4 Command Elapsed Time 4 (CET4) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_CET4_CET4_SHIFT 24 +#define SPWTDP_CET4_CET4_MASK 0xff000000U +#define SPWTDP_CET4_CET4_GET( _reg ) \ + ( ( ( _reg ) >> 24 ) & 0xffU ) +#define SPWTDP_CET4_CET4( _val ) ( ( _val ) << 24 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPDPF Datation Preamble Field (DPF) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_DPF_DPF_SHIFT 0 +#define SPWTDP_DPF_DPF_MASK 0xffffU +#define SPWTDP_DPF_DPF_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffU ) +#define SPWTDP_DPF_DPF( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPDET0 Datation Elapsed Time 0 (DET0) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_DET0_DET0_SHIFT 0 +#define SPWTDP_DET0_DET0_MASK 0xffffffffU +#define SPWTDP_DET0_DET0_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define SPWTDP_DET0_DET0( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPDET1 Datation Elapsed Time 1 (DET1) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_DET1_DET1_SHIFT 0 +#define SPWTDP_DET1_DET1_MASK 0xffffffffU +#define SPWTDP_DET1_DET1_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define SPWTDP_DET1_DET1( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPDET2 Datation Elapsed Time 2 (DET2) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_DET2_DET2_SHIFT 0 +#define SPWTDP_DET2_DET2_MASK 0xffffffffU +#define SPWTDP_DET2_DET2_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define SPWTDP_DET2_DET2( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPDET3 Datation Elapsed Time 3 (DET3) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_DET3_DET3_SHIFT 0 +#define SPWTDP_DET3_DET3_MASK 0xffffffffU +#define SPWTDP_DET3_DET3_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define SPWTDP_DET3_DET3( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPDET4 Datation Elapsed Time 4 (DET4) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_DET4_DET4_SHIFT 24 +#define SPWTDP_DET4_DET4_MASK 0xff000000U +#define SPWTDP_DET4_DET4_GET( _reg ) \ + ( ( ( _reg ) >> 24 ) & 0xffU ) +#define SPWTDP_DET4_DET4( _val ) ( ( _val ) << 24 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPTRPFRX Time-Stamp Preamble Field Rx (TRPFRX) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_TRPFRX_TRPF_SHIFT 0 +#define SPWTDP_TRPFRX_TRPF_MASK 0xffffU +#define SPWTDP_TRPFRX_TRPF_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffU ) +#define SPWTDP_TRPFRX_TRPF( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPTR0 Time Stamp Elapsed Time 0 Rx (TR0) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_TR0_TR0_SHIFT 0 +#define SPWTDP_TR0_TR0_MASK 0xffffffffU +#define SPWTDP_TR0_TR0_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define SPWTDP_TR0_TR0( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPTR1 Time Stamp Elapsed Time 1 Rx (TR1) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_TR1_TR1_SHIFT 0 +#define SPWTDP_TR1_TR1_MASK 0xffffffffU +#define SPWTDP_TR1_TR1_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define SPWTDP_TR1_TR1( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPTR2 Time Stamp Elapsed Time 2 Rx (TR2) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_TR2_TR2_SHIFT 0 +#define SPWTDP_TR2_TR2_MASK 0xffffffffU +#define SPWTDP_TR2_TR2_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define SPWTDP_TR2_TR2( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPTR3 Time Stamp Elapsed Time 3 Rx (TR3) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_TR3_TR3_SHIFT 0 +#define SPWTDP_TR3_TR3_MASK 0xffffffffU +#define SPWTDP_TR3_TR3_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define SPWTDP_TR3_TR3( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPTR4 Time Stamp Elapsed Time 4 Rx (TR4) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_TR4_TR4_SHIFT 24 +#define SPWTDP_TR4_TR4_MASK 0xff000000U +#define SPWTDP_TR4_TR4_GET( _reg ) \ + ( ( ( _reg ) >> 24 ) & 0xffU ) +#define SPWTDP_TR4_TR4( _val ) ( ( _val ) << 24 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPTTPFTX \ + * Time-Stamp SpaceWire Time-Code and Preamble Field Tx (TTPFTX) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_TTPFTX_TSTC_SHIFT 24 +#define SPWTDP_TTPFTX_TSTC_MASK 0xff000000U +#define SPWTDP_TTPFTX_TSTC_GET( _reg ) \ + ( ( ( _reg ) >> 24 ) & 0xffU ) +#define SPWTDP_TTPFTX_TSTC( _val ) ( ( _val ) << 24 ) + +#define SPWTDP_TTPFTX_TTPF_SHIFT 0 +#define SPWTDP_TTPFTX_TTPF_MASK 0xffffU +#define SPWTDP_TTPFTX_TTPF_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffU ) +#define SPWTDP_TTPFTX_TTPF( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPTT0 Time Stamp Elapsed Time 0 Tx (TT0) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_TT0_TT0_SHIFT 0 +#define SPWTDP_TT0_TT0_MASK 0xffffffffU +#define SPWTDP_TT0_TT0_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define SPWTDP_TT0_TT0( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPTT1 Time Stamp Elapsed Time 1 Tx (TT1) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_TT1_TT1_SHIFT 0 +#define SPWTDP_TT1_TT1_MASK 0xffffffffU +#define SPWTDP_TT1_TT1_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define SPWTDP_TT1_TT1( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPTT2 Time Stamp Elapsed Time 2 Tx (TT2) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_TT2_TT2_SHIFT 0 +#define SPWTDP_TT2_TT2_MASK 0xffffffffU +#define SPWTDP_TT2_TT2_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define SPWTDP_TT2_TT2( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPTT3 Time Stamp Elapsed Time 3 Tx (TT3) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_TT3_TT3_SHIFT 0 +#define SPWTDP_TT3_TT3_MASK 0xffffffffU +#define SPWTDP_TT3_TT3_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define SPWTDP_TT3_TT3( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPTT4 Time Stamp Elapsed Time 4 Tx (TT4) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_TT4_TT4_SHIFT 24 +#define SPWTDP_TT4_TT4_MASK 0xff000000U +#define SPWTDP_TT4_TT4_GET( _reg ) \ + ( ( ( _reg ) >> 24 ) & 0xffU ) +#define SPWTDP_TT4_TT4( _val ) ( ( _val ) << 24 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPLPF Latency Preamble Field (LPF) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_LPF_LPF_SHIFT 0 +#define SPWTDP_LPF_LPF_MASK 0xffffU +#define SPWTDP_LPF_LPF_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffU ) +#define SPWTDP_LPF_LPF( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPIE Interrupt Enable (IE) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_IE_NCTCE 0x80000U + +#define SPWTDP_IE_SETE 0x400U + +#define SPWTDP_IE_EDIE3 0x200U + +#define SPWTDP_IE_EDIE2 0x100U + +#define SPWTDP_IE_EDIE1 0x80U + +#define SPWTDP_IE_EDIE0 0x40U + +#define SPWTDP_IE_DITE 0x20U + +#define SPWTDP_IE_DIRE 0x10U + +#define SPWTDP_IE_TTE 0x8U + +#define SPWTDP_IE_TME 0x4U + +#define SPWTDP_IE_TRE 0x2U + +#define SPWTDP_IE_SE 0x1U + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPDC Delay Count (DC) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_DC_DC_SHIFT 0 +#define SPWTDP_DC_DC_MASK 0x7fffU +#define SPWTDP_DC_DC_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0x7fffU ) +#define SPWTDP_DC_DC( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPDS Disable Sync (DS) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_DS_EN 0x80000000U + +#define SPWTDP_DS_CD_SHIFT 0 +#define SPWTDP_DS_CD_MASK 0xffffffU +#define SPWTDP_DS_CD_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffU ) +#define SPWTDP_DS_CD( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPEDM0 External Datation 0 Mask (EDM0) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_EDM0_EDM0_SHIFT 0 +#define SPWTDP_EDM0_EDM0_MASK 0xffffffffU +#define SPWTDP_EDM0_EDM0_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define SPWTDP_EDM0_EDM0( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPEDPF0 \ + * External Datation 0 Preamble Field (EDPF0) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_EDPF0_EDPF0_SHIFT 0 +#define SPWTDP_EDPF0_EDPF0_MASK 0xffffU +#define SPWTDP_EDPF0_EDPF0_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffU ) +#define SPWTDP_EDPF0_EDPF0( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPED0ET0 \ + * External Datation 0 Elapsed Time 0 (ED0ET0) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_ED0ET0_ED0ET0_SHIFT 0 +#define SPWTDP_ED0ET0_ED0ET0_MASK 0xffffffffU +#define SPWTDP_ED0ET0_ED0ET0_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define SPWTDP_ED0ET0_ED0ET0( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPED0ET1 \ + * External Datation 0 Elapsed Time 1 (ED0ET1) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_ED0ET1_ED0ET1_SHIFT 0 +#define SPWTDP_ED0ET1_ED0ET1_MASK 0xffffffffU +#define SPWTDP_ED0ET1_ED0ET1_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define SPWTDP_ED0ET1_ED0ET1( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPED0ET2 \ + * External Datation 0 Elapsed Time 2 (ED0ET2) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_ED0ET2_ED0ET2_SHIFT 0 +#define SPWTDP_ED0ET2_ED0ET2_MASK 0xffffffffU +#define SPWTDP_ED0ET2_ED0ET2_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define SPWTDP_ED0ET2_ED0ET2( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPED0ET3 \ + * External Datation 0 Elapsed Time 3 (ED0ET3) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_ED0ET3_ED0ET3_SHIFT 0 +#define SPWTDP_ED0ET3_ED0ET3_MASK 0xffffffffU +#define SPWTDP_ED0ET3_ED0ET3_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define SPWTDP_ED0ET3_ED0ET3( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup RTEMSDeviceGRLIBSPWTDPED0ET4 \ + * External Datation 0 Elapsed Time 4 (ED0ET4) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define SPWTDP_ED0ET4_ED0ET4_SHIFT 24 +#define SPWTDP_ED0ET4_ED0ET4_MASK 0xff000000U +#define SPWTDP_ED0ET4_ED0ET4_GET( _reg ) \ + ( ( ( _reg ) >> 24 ) & 0xffU ) +#define SPWTDP_ED0ET4_ED0ET4( _val ) ( ( _val ) << 24 ) + +/** @} */ + +/** + * @brief This structure defines the SPWTDP register block memory map. + */ +typedef struct spwtdp { + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPCONF0. + */ + uint32_t conf0; + + uint32_t reserved_4_c[ 2 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPCONF3. + */ + uint32_t conf3; + + uint32_t reserved_10_20[ 4 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPCTRL. + */ + uint32_t ctrl; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPCET0. + */ + uint32_t cet0_0; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPCET1. + */ + uint32_t cet1; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPCET2. + */ + uint32_t cet2; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPCET0. + */ + uint32_t cet0_1; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPCET4. + */ + uint32_t cet4; + + uint32_t reserved_38_40[ 2 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPDPF. + */ + uint32_t dpf; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPDET0. + */ + uint32_t det0; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPDET1. + */ + uint32_t det1; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPDET2. + */ + uint32_t det2; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPDET3. + */ + uint32_t det3; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPDET4. + */ + uint32_t det4; + + uint32_t reserved_58_60[ 2 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPTRPFRX. + */ + uint32_t trpfrx; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPTR0. + */ + uint32_t tr0; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPTR1. + */ + uint32_t tr1; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPTR2. + */ + uint32_t tr2; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPTR3. + */ + uint32_t tr3; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPTR4. + */ + uint32_t tr4; + + uint32_t reserved_78_80[ 2 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPTTPFTX. + */ + uint32_t ttpftx; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPTT0. + */ + uint32_t tt0; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPTT1. + */ + uint32_t tt1; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPTT2. + */ + uint32_t tt2; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPTT3. + */ + uint32_t tt3; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPTT4. + */ + uint32_t tt4; + + uint32_t reserved_98_a0[ 2 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPLPF. + */ + uint32_t lpf; + + uint32_t reserved_a4_c0[ 7 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPIE. + */ + uint32_t ie; + + uint32_t reserved_c4_c8; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPDC. + */ + uint32_t dc; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPDS. + */ + uint32_t ds; + + uint32_t reserved_d0_100[ 12 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPEDM0. + */ + uint32_t edm0; + + uint32_t reserved_104_110[ 3 ]; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPEDPF0. + */ + uint32_t edpf0; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPED0ET0. + */ + uint32_t ed0et0; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPED0ET1. + */ + uint32_t ed0et1; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPED0ET2. + */ + uint32_t ed0et2; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPED0ET3. + */ + uint32_t ed0et3; + + /** + * @brief See @ref RTEMSDeviceGRLIBSPWTDPED0ET4. + */ + uint32_t ed0et4; +} spwtdp; + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GRLIB_SPWTDP_REGS_H */ diff --git a/bsps/sparc/include/grlib/io.h b/bsps/sparc/include/grlib/io.h new file mode 100644 index 0000000000..49fed6f682 --- /dev/null +++ b/bsps/sparc/include/grlib/io.h @@ -0,0 +1,210 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSDeviceGRLIBIO + * + * @brief This header file defines the register load/store interface. + */ + +/* + * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file is part of the RTEMS quality process and was automatically + * generated. If you find something that needs to be fixed or + * worded better please post a report or patch to an RTEMS mailing list + * or raise a bug report: + * + * https://www.rtems.org/bugs.html + * + * For information on updating and regenerating please refer to the How-To + * section in the Software Requirements Engineering chapter of the + * RTEMS Software Engineering manual. The manual is provided as a part of + * a release. For development sources please refer to the online + * documentation at: + * + * https://docs.rtems.org + */ + +/* Generated from spec:/bsp/sparc/if/grlib-io-header */ + +#ifndef _GRLIB_IO_H +#define _GRLIB_IO_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Generated from spec:/bsp/sparc/if/grlib-io-group */ + +/** + * @defgroup RTEMSDeviceGRLIBIO Register Load/Store + * + * @ingroup RTEMSDeviceGRLIB + * + * @brief This group contains the GRLIB register load/store API. + */ + +/* Generated from spec:/bsp/sparc/if/grlib-load-08 */ + +/** + * @ingroup RTEMSDeviceGRLIBIO + * + * @brief Loads the memory-mapped unsigned 8-bit register. + * + * @param address is the address of the memory-mapped unsigned 8-bit register + * to load. + * + * @return Returns the loaded register value. + */ +static inline uint8_t grlib_load_8( const volatile uint8_t *address ) +{ + return *address; +} + +/* Generated from spec:/bsp/sparc/if/grlib-load-16 */ + +/** + * @ingroup RTEMSDeviceGRLIBIO + * + * @brief Loads the memory-mapped unsigned 16-bit register. + * + * @param address is the address of the memory-mapped unsigned 16-bit register + * to load. + * + * @return Returns the loaded register value. + */ +static inline uint16_t grlib_load_16( const volatile uint16_t *address ) +{ + return *address; +} + +/* Generated from spec:/bsp/sparc/if/grlib-load-32 */ + +/** + * @ingroup RTEMSDeviceGRLIBIO + * + * @brief Loads the memory-mapped unsigned 32-bit register. + * + * @param address is the address of the memory-mapped unsigned 32-bit register + * to load. + * + * @return Returns the loaded register value. + */ +static inline uint32_t grlib_load_32( const volatile uint32_t *address ) +{ + return *address; +} + +/* Generated from spec:/bsp/sparc/if/grlib-load-64 */ + +/** + * @ingroup RTEMSDeviceGRLIBIO + * + * @brief Loads the memory-mapped unsigned 64-bit register. + * + * @param address is the address of the memory-mapped unsigned 64-bit register + * to load. + * + * @return Returns the loaded register value. + */ +static inline uint64_t grlib_load_64( const volatile uint64_t *address ) +{ + return *address; +} + +/* Generated from spec:/bsp/sparc/if/grlib-store-08 */ + +/** + * @ingroup RTEMSDeviceGRLIBIO + * + * @brief Stores the value to the memory-mapped unsigned 8-bit register. + * + * @param address is the address of the memory-mapped unsigned 8-bit register. + * + * @param value is the value to store. + */ +static inline void grlib_store_8( volatile uint8_t *address, uint8_t value ) +{ + *address = value; +} + +/* Generated from spec:/bsp/sparc/if/grlib-store-16 */ + +/** + * @ingroup RTEMSDeviceGRLIBIO + * + * @brief Stores the value to the memory-mapped unsigned 16-bit register. + * + * @param address is the address of the memory-mapped unsigned 16-bit register. + * + * @param value is the value to store. + */ +static inline void grlib_store_16( volatile uint16_t *address, uint16_t value ) +{ + *address = value; +} + +/* Generated from spec:/bsp/sparc/if/grlib-store-32 */ + +/** + * @ingroup RTEMSDeviceGRLIBIO + * + * @brief Stores the value to the memory-mapped unsigned 32-bit register. + * + * @param address is the address of the memory-mapped unsigned 32-bit register. + * + * @param value is the value to store. + */ +static inline void grlib_store_32( volatile uint32_t *address, uint32_t value ) +{ + *address = value; +} + +/* Generated from spec:/bsp/sparc/if/grlib-store-64 */ + +/** + * @ingroup RTEMSDeviceGRLIBIO + * + * @brief Stores the value to the memory-mapped unsigned 64-bit register. + * + * @param address is the address of the memory-mapped unsigned 64-bit register. + * + * @param value is the value to store. + */ +static inline void grlib_store_64( volatile uint64_t *address, uint64_t value ) +{ + *address = value; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _GRLIB_IO_H */ -- cgit v1.2.3