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Provide RTEMS_NO_RETURN also in case RTEMS_DEBUG is defined to prevent errors
like this:
error: no return statement in function returning non-void [-Werror=return-type]
Use C11 and C++11 standard means to declare a no-return function.
Close #4122.
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This adds a CPU port for AArch64(ARMv8) with support for exceptions and
interrupts.
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Before this patch RTEMS_Malloc_Initialize() had a fixed dependency on
_Workspace_Area. Introduce _Workspace_Malloc_initializer to have this
dependency only if CONFIGURE_UNIFIED_WORK_AREAS is defined by the
application configuration.
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In contrast to message queues created by rtems_message_queue_create(), the
message queues constructed by this directive use a user-provided message buffer
storage area.
Add RTEMS_MESSAGE_QUEUE_BUFFER() to define a message buffer type for message
buffer storage areas.
Update #4007.
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Merge CORE_message_queue_Buffer structure into
CORE_message_queue_Buffer_control.
Use a zero-length array for the actual message buffer. This reduces the
structure size on all targets.
Update #4007.
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Return a status code and differentiate between error conditions.
Update #4007.
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Initialize the structure in a single code block after the error checks and
calculations.
Update #4007.
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The previous multiplication error check is broken on 64-bit machines. Use the
recommended check from SEI CERT C Coding Standard, "INT30-C. Ensure that
unsigned integer operations do not wrap".
Make sure the message size computation does not overflow.
Update #4007.
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Update #4007.
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Debug output can be added to user-defined fatal error handlers.
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Including <stdio.h> in <rtems/score/cpu.h> breaks libbsd.
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Add this application configuration option. This configuration option can be
used to reserve space for the dynamic linking of modules with thread-local
storage objects.
Add RTEMS_TASK_STORAGE_ALIGNMENT to define the minium alignment of a
thread-local storage size.
Update #4074.
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In a multi-processor system we must broadcast the TLB maintenance operation to
the Inner Shareable domain to ensure that the other processors update their TLB
caches accordingly.
Close #4068.
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Closes #4076.
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Fix an error cleanup path in SMP configurations to avoid a NULL pointer access.
Update #3959.
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This avoids a dependency to the stack free function in the thread
destruction.
Update #3959.
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This decouples the task stack allocation from the deallocation.
Update #3959.
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Do the stack allocator initialization and sanity check only if a
user-provided stack allocator was configured. This avoids a dependency
of _Thread_Handler_initialization() on the stack allocator.
Update #3959.
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The nodes are never NULL.
Update #3959.
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Hide implementation details.
Update #3959.
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Update #3959.
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Do not access executing->current_state outside the protection of the
thread state lock. Add missing state with a comment.
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Remove the superfluous invalid name check since the object creation
directives ensure that objects with such a name cannot exist. Also
finding an object with such a name would be no catastrophy if it really
exists.
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Simplify object name to identifier directives. Using
_RTEMS_Name_to_id() to implement the directives enables a tail call
optimization.
Change license to BSD-2-Clause according to file history.
Update #3053.
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Prefer macros with a proper namespace.
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Make sure that the esp is restored before the eflags register.
When the init task is initially restored, system interrupts are activated when the
eflags register is loaded.
If the esp register still points to an address in the interrupt stack
area (from early system initlization) the ISR might overwrite its own
stack.
Closes #4031
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Due to an unmaintained toolchain (internal errors in GCC, no FSF GDB
integration) the Epiphany architecture was obsoleted in RTEMS 5.1.
Update #3941.
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Update #3943.
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Update #4018.
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This introduces the CPU_USE_LIBC_INIT_FINI_ARRAY define for use by CPU
ports to determine which global constructor and destructor methods are
used instead of placing architecture defines where they shouldn't be.
Close #4018
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- Defines CPU_Interrupt_frame in cpu_impl.h
- Updates isq_asm.S to save/restore registers in matching order to
interrupt frame
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Uses similar flow in cpu_asm.S for i386 as for arm.
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Create a GS segment in the GDT for each processor for storing TLS.
This makes the GDT in startAP.S obsolete as all processors now share the
same GDT, which is passed to each AP at startup.
The correct segment for each processor is calculated in cpu_asm.S.
Update #3335
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Store the stack pointer of the exception context to the exception frame.
Close #3987.
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This order change fixes the Latex documentation build via Doxygen.
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Use the following variant which was already used by most source files:
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
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Close #3949.
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Update #3949.
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This reverts commit 8e80876bdd54e36fb668eee655eec1dd588daf13
which broke several architectures.
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The _ISR_Stack_area_begin and _ISR_Stack_area_end symbols are in
different sections. They must have the same alignment, otherwise the
following linker directive could separate them:
*(SORT_BY_ALIGNMENT (SORT_BY_NAME (.rtemsstack*)))
Update #3799.
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Statically initialize the ARMv7-M vector table to allow a placement in
ROM with read-only MPU settings.
Change licence to BSD-2-Clause in some files.
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Update #3904.
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In uniprocessor and SMP configurations, the context switch extensions
were called during _Thread_Do_dispatch():
void _Thread_Do_dispatch( Per_CPU_Control *cpu_self, ISR_Level level )
{
Thread_Control *executing;
executing = cpu_self->executing;
...
do {
Thread_Control *heir;
heir = _Thread_Get_heir_and_make_it_executing( cpu_self );
...
_User_extensions_Thread_switch( executing, heir );
...
_Context_Switch( &executing->Registers, &heir->Registers );
...
} while ( cpu_self->dispatch_necessary );
...
}
In uniprocessor configurations, this is fine and the context switch
extensions are called for all thread switches except the very first
thread switch to the initialization thread. However, in SMP
configurations, the context switch may be invalidated and updated in the
low-level _Context_Switch() routine. See:
https://docs.rtems.org/branches/master/c-user/symmetric_multiprocessing_services.html#thread-dispatch-details
In case such an update happens, a thread will execute on the processor
which was not seen in the previous call of the context switch
extensions. This can confuse for example event record consumers which
use events generated by a context switch extension.
Fixing this is not straight forward. The context switch extensions call
must move after the low-level context switch. The problem here is that
we may end up in _Thread_Handler(). Adding the context switch
extensions call to _Thread_Handler() covers now also the thread switch
to the initialization thread. We also have to save the last executing
thread (ancestor) of the processor. Registers or the stack cannot be
used for this purpose. We have to add it to the per-processor
information. Existing extensions may be affected, since now context
switch extensions use the stack of the heir thread. The stack checker
is affected by this.
Calling the thread switch extensions in the low-level context switch is
difficult since at this point an intermediate stack is used which is
only large enough to enable servicing of interrupts.
Update #3885.
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Update #3835.
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If the non-preempt mode for threads is supported depends on the
scheduler implementation. Add
_Scheduler_Is_non_preempt_mode_supported() to indicate this.
Update #3876.
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Test for the proper system condition instead of using the
rtems_configuration_is_smp_enabled() workaround.
Update #3876.
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Move the unified workspace configuration constant out of the
configuration table.
Provide a default definition of the unified workspace constant.
Update #3875.
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Move the idle thread body configuration constant out of the
configuration table.
Provide a default definition of the idle thread body constant.
Update #3875.
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