1 files changed, 672 insertions, 0 deletions
diff --git a/bsps/include/dev/grlib/grpci2.h b/bsps/include/dev/grlib/grpci2.h
new file mode 100644
index 0000000000..0aa4cd3ef4
--- /dev/null
+++ b/bsps/include/dev/grlib/grpci2.h
@@ -0,0 +1,672 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSDeviceGRLIB
+ *
+ * @brief This header file defines the GRPCI2 register block interface.
+ */
+
+/*
+ * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * This file is part of the RTEMS quality process and was automatically
+ * generated.  If you find something that needs to be fixed or
+ * worded better please post a report or patch to an RTEMS mailing list
+ * or raise a bug report:
+ *
+ * https://www.rtems.org/bugs.html
+ *
+ * For information on updating and regenerating please refer to the How-To
+ * section in the Software Requirements Engineering chapter of the
+ * RTEMS Software Engineering manual.  The manual is provided as a part of
+ * a release.  For development sources please refer to the online
+ * documentation at:
+ *
+ * https://docs.rtems.org
+ */
+
+/* Generated from spec:/dev/grlib/if/grpci2-header */
+
+#ifndef _DEV_GRLIB_GRPCI2_H
+#define _DEV_GRLIB_GRPCI2_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Generated from spec:/dev/grlib/if/grpci2 */
+
+/**
+ * @defgroup DevGrlibIfGrpci2 GRPCI2
+ *
+ * @ingroup RTEMSDeviceGRLIB
+ *
+ * @brief This group contains the GRPCI2 interfaces.
+ *
+ * @{
+ */
+
+/**
+ * @defgroup DevGrlibIfGrpci2CTRL CTRL
+ *
+ * @brief Control register
+ *
+ * @{
+ */
+
+#define GRPCI2_CTRL_RE 0x80000000U
+
+#define GRPCI2_CTRL_MR 0x40000000U
+
+#define GRPCI2_CTRL_TR 0x20000000U
+
+#define GRPCI2_CTRL_SI 0x8000000U
+
+#define GRPCI2_CTRL_PE 0x4000000U
+
+#define GRPCI2_CTRL_ER 0x2000000U
+
+#define GRPCI2_CTRL_EI 0x1000000U
+
+#define GRPCI2_CTRL_BUS_NUMBER_SHIFT 16
+#define GRPCI2_CTRL_BUS_NUMBER_MASK 0xff0000U
+#define GRPCI2_CTRL_BUS_NUMBER_GET( _reg ) \
+  ( ( ( _reg ) >> 16 ) & 0xffU )
+#define GRPCI2_CTRL_BUS_NUMBER( _val ) ( ( _val ) << 16 )
+
+#define GRPCI2_CTRL_DFA 0x800U
+
+#define GRPCI2_CTRL_IB 0x400U
+
+#define GRPCI2_CTRL_CB 0x200U
+
+#define GRPCI2_CTRL_DIF 0x100U
+
+#define GRPCI2_CTRL_DEVICE_INT_MASK_SHIFT 4
+#define GRPCI2_CTRL_DEVICE_INT_MASK_MASK 0xf0U
+#define GRPCI2_CTRL_DEVICE_INT_MASK_GET( _reg ) \
+  ( ( ( _reg ) >> 4 ) & 0xfU )
+#define GRPCI2_CTRL_DEVICE_INT_MASK( _val ) ( ( _val ) << 4 )
+
+#define GRPCI2_CTRL_HOST_INT_MASK_SHIFT 0
+#define GRPCI2_CTRL_HOST_INT_MASK_MASK 0xfU
+#define GRPCI2_CTRL_HOST_INT_MASK_GET( _reg ) \
+  ( ( ( _reg ) >> 0 ) & 0xfU )
+#define GRPCI2_CTRL_HOST_INT_MASK( _val ) ( ( _val ) << 0 )
+
+/** @} */
+
+/**
+ * @defgroup DevGrlibIfGrpci2STATCAP STATCAP
+ *
+ * @brief Status and Capability register
+ *
+ * @{
+ */
+
+#define GRPCI2_STATCAP_HOST 0x80000000U
+
+#define GRPCI2_STATCAP_MST 0x40000000U
+
+#define GRPCI2_STATCAP_TAR 0x20000000U
+
+#define GRPCI2_STATCAP_DMA 0x10000000U
+
+#define GRPCI2_STATCAP_DI 0x8000000U
+
+#define GRPCI2_STATCAP_HI 0x4000000U
+
+#define GRPCI2_STATCAP_IRQ_MODE_SHIFT 24
+#define GRPCI2_STATCAP_IRQ_MODE_MASK 0x3000000U
+#define GRPCI2_STATCAP_IRQ_MODE_GET( _reg ) \
+  ( ( ( _reg ) >> 24 ) & 0x3U )
+#define GRPCI2_STATCAP_IRQ_MODE( _val ) ( ( _val ) << 24 )
+
+#define GRPCI2_STATCAP_TRACE 0x800000U
+
+#define GRPCI2_STATCAP_CFGDO 0x100000U
+
+#define GRPCI2_STATCAP_CFGER 0x80000U
+
+#define GRPCI2_STATCAP_CORE_INT_STATUS_SHIFT 12
+#define GRPCI2_STATCAP_CORE_INT_STATUS_MASK 0x7f000U
+#define GRPCI2_STATCAP_CORE_INT_STATUS_GET( _reg ) \
+  ( ( ( _reg ) >> 12 ) & 0x7fU )
+#define GRPCI2_STATCAP_CORE_INT_STATUS( _val ) ( ( _val ) << 12 )
+
+#define GRPCI2_STATCAP_HOST_INT_STATUS_SHIFT 8
+#define GRPCI2_STATCAP_HOST_INT_STATUS_MASK 0xf00U
+#define GRPCI2_STATCAP_HOST_INT_STATUS_GET( _reg ) \
+  ( ( ( _reg ) >> 8 ) & 0xfU )
+#define GRPCI2_STATCAP_HOST_INT_STATUS( _val ) ( ( _val ) << 8 )
+
+#define GRPCI2_STATCAP_FDEPTH_SHIFT 2
+#define GRPCI2_STATCAP_FDEPTH_MASK 0x1cU
+#define GRPCI2_STATCAP_FDEPTH_GET( _reg ) \
+  ( ( ( _reg ) >> 2 ) & 0x7U )
+#define GRPCI2_STATCAP_FDEPTH( _val ) ( ( _val ) << 2 )
+
+#define GRPCI2_STATCAP_FNUM_SHIFT 0
+#define GRPCI2_STATCAP_FNUM_MASK 0x3U
+#define GRPCI2_STATCAP_FNUM_GET( _reg ) \
+  ( ( ( _reg ) >> 0 ) & 0x3U )
+#define GRPCI2_STATCAP_FNUM( _val ) ( ( _val ) << 0 )
+
+/** @} */
+
+/**
+ * @defgroup DevGrlibIfGrpci2BCIM BCIM
+ *
+ * @brief PCI master prefetch burst limit
+ *
+ * @{
+ */
+
+#define GRPCI2_BCIM_AHB_MASTER_UNMASK_SHIFT 16
+#define GRPCI2_BCIM_AHB_MASTER_UNMASK_MASK 0xffff0000U
+#define GRPCI2_BCIM_AHB_MASTER_UNMASK_GET( _reg ) \
+  ( ( ( _reg ) >> 16 ) & 0xffffU )
+#define GRPCI2_BCIM_AHB_MASTER_UNMASK( _val ) ( ( _val ) << 16 )
+
+#define GRPCI2_BCIM_BURST_LENGTH_SHIFT 0
+#define GRPCI2_BCIM_BURST_LENGTH_MASK 0xffU
+#define GRPCI2_BCIM_BURST_LENGTH_GET( _reg ) \
+  ( ( ( _reg ) >> 0 ) & 0xffU )
+#define GRPCI2_BCIM_BURST_LENGTH( _val ) ( ( _val ) << 0 )
+
+/** @} */
+
+/**
+ * @defgroup DevGrlibIfGrpci2AHB2PCI AHB2PCI
+ *
+ * @brief AHB to PCI mapping for PCI IO
+ *
+ * @{
+ */
+
+#define GRPCI2_AHB2PCI_AHB_TO_PCI_IO_SHIFT 16
+#define GRPCI2_AHB2PCI_AHB_TO_PCI_IO_MASK 0xffff0000U
+#define GRPCI2_AHB2PCI_AHB_TO_PCI_IO_GET( _reg ) \
+  ( ( ( _reg ) >> 16 ) & 0xffffU )
+#define GRPCI2_AHB2PCI_AHB_TO_PCI_IO( _val ) ( ( _val ) << 16 )
+
+/** @} */
+
+/**
+ * @defgroup DevGrlibIfGrpci2DMACTRL DMACTRL
+ *
+ * @brief DMA control and status register
+ *
+ * @{
+ */
+
+#define GRPCI2_DMACTRL_SAFE 0x80000000U
+
+#define GRPCI2_DMACTRL_CHIRQ_SHIFT 12
+#define GRPCI2_DMACTRL_CHIRQ_MASK 0xff000U
+#define GRPCI2_DMACTRL_CHIRQ_GET( _reg ) \
+  ( ( ( _reg ) >> 12 ) & 0xffU )
+#define GRPCI2_DMACTRL_CHIRQ( _val ) ( ( _val ) << 12 )
+
+#define GRPCI2_DMACTRL_MA 0x800U
+
+#define GRPCI2_DMACTRL_TA 0x400U
+
+#define GRPCI2_DMACTRL_PE 0x200U
+
+#define GRPCI2_DMACTRL_AE 0x100U
+
+#define GRPCI2_DMACTRL_DE 0x80U
+
+#define GRPCI2_DMACTRL_NUMCH_SHIFT 4
+#define GRPCI2_DMACTRL_NUMCH_MASK 0x70U
+#define GRPCI2_DMACTRL_NUMCH_GET( _reg ) \
+  ( ( ( _reg ) >> 4 ) & 0x7U )
+#define GRPCI2_DMACTRL_NUMCH( _val ) ( ( _val ) << 4 )
+
+#define GRPCI2_DMACTRL_ACTIVE 0x8U
+
+#define GRPCI2_DMACTRL_DIS 0x4U
+
+#define GRPCI2_DMACTRL_IE 0x2U
+
+#define GRPCI2_DMACTRL_EN 0x1U
+
+/** @} */
+
+/**
+ * @defgroup DevGrlibIfGrpci2DMABASE DMABASE
+ *
+ * @brief DMA descriptor base address register
+ *
+ * @{
+ */
+
+#define GRPCI2_DMABASE_BASE_SHIFT 0
+#define GRPCI2_DMABASE_BASE_MASK 0xffffffffU
+#define GRPCI2_DMABASE_BASE_GET( _reg ) \
+  ( ( ( _reg ) >> 0 ) & 0xffffffffU )
+#define GRPCI2_DMABASE_BASE( _val ) ( ( _val ) << 0 )
+
+/** @} */
+
+/**
+ * @defgroup DevGrlibIfGrpci2DMACHAN DMACHAN
+ *
+ * @brief DMA channel active register
+ *
+ * @{
+ */
+
+#define GRPCI2_DMACHAN_CHAN_SHIFT 0
+#define GRPCI2_DMACHAN_CHAN_MASK 0xffffffffU
+#define GRPCI2_DMACHAN_CHAN_GET( _reg ) \
+  ( ( ( _reg ) >> 0 ) & 0xffffffffU )
+#define GRPCI2_DMACHAN_CHAN( _val ) ( ( _val ) << 0 )
+
+/** @} */
+
+/**
+ * @defgroup DevGrlibIfGrpci2PCI2AHB PCI2AHB
+ *
+ * @brief PCI BAR to AHB address mapping register
+ *
+ * @{
+ */
+
+#define GRPCI2_PCI2AHB_ADDR_SHIFT 0
+#define GRPCI2_PCI2AHB_ADDR_MASK 0xffffffffU
+#define GRPCI2_PCI2AHB_ADDR_GET( _reg ) \
+  ( ( ( _reg ) >> 0 ) & 0xffffffffU )
+#define GRPCI2_PCI2AHB_ADDR( _val ) ( ( _val ) << 0 )
+
+/** @} */
+
+/**
+ * @defgroup DevGrlibIfGrpci2AHBM2PCI AHBM2PCI
+ *
+ * @brief AHB master to PCI memory address mapping register
+ *
+ * @{
+ */
+
+#define GRPCI2_AHBM2PCI_ADDR_SHIFT 0
+#define GRPCI2_AHBM2PCI_ADDR_MASK 0xffffffffU
+#define GRPCI2_AHBM2PCI_ADDR_GET( _reg ) \
+  ( ( ( _reg ) >> 0 ) & 0xffffffffU )
+#define GRPCI2_AHBM2PCI_ADDR( _val ) ( ( _val ) << 0 )
+
+/** @} */
+
+/**
+ * @defgroup DevGrlibIfGrpci2TCTRC TCTRC
+ *
+ * @brief PCI trace Control and Status register
+ *
+ * @{
+ */
+
+#define GRPCI2_TCTRC_TRIG_INDEX_SHIFT 16
+#define GRPCI2_TCTRC_TRIG_INDEX_MASK 0xffff0000U
+#define GRPCI2_TCTRC_TRIG_INDEX_GET( _reg ) \
+  ( ( ( _reg ) >> 16 ) & 0xffffU )
+#define GRPCI2_TCTRC_TRIG_INDEX( _val ) ( ( _val ) << 16 )
+
+#define GRPCI2_TCTRC_AR 0x8000U
+
+#define GRPCI2_TCTRC_EN 0x4000U
+
+#define GRPCI2_TCTRC_DEPTH_SHIFT 4
+#define GRPCI2_TCTRC_DEPTH_MASK 0xff0U
+#define GRPCI2_TCTRC_DEPTH_GET( _reg ) \
+  ( ( ( _reg ) >> 4 ) & 0xffU )
+#define GRPCI2_TCTRC_DEPTH( _val ) ( ( _val ) << 4 )
+
+#define GRPCI2_TCTRC_SO 0x2U
+
+#define GRPCI2_TCTRC_SA 0x1U
+
+/** @} */
+
+/**
+ * @defgroup DevGrlibIfGrpci2TMODE TMODE
+ *
+ * @brief PCI trace counter and mode register
+ *
+ * @{
+ */
+
+#define GRPCI2_TMODE_TRACING_MODE_SHIFT 24
+#define GRPCI2_TMODE_TRACING_MODE_MASK 0xf000000U
+#define GRPCI2_TMODE_TRACING_MODE_GET( _reg ) \
+  ( ( ( _reg ) >> 24 ) & 0xfU )
+#define GRPCI2_TMODE_TRACING_MODE( _val ) ( ( _val ) << 24 )
+
+#define GRPCI2_TMODE_TRIG_COUNT_SHIFT 16
+#define GRPCI2_TMODE_TRIG_COUNT_MASK 0xff0000U
+#define GRPCI2_TMODE_TRIG_COUNT_GET( _reg ) \
+  ( ( ( _reg ) >> 16 ) & 0xffU )
+#define GRPCI2_TMODE_TRIG_COUNT( _val ) ( ( _val ) << 16 )
+
+#define GRPCI2_TMODE_DELAYED_STOP_SHIFT 0
+#define GRPCI2_TMODE_DELAYED_STOP_MASK 0xffffU
+#define GRPCI2_TMODE_DELAYED_STOP_GET( _reg ) \
+  ( ( ( _reg ) >> 0 ) & 0xffffU )
+#define GRPCI2_TMODE_DELAYED_STOP( _val ) ( ( _val ) << 0 )
+
+/** @} */
+
+/**
+ * @defgroup DevGrlibIfGrpci2TADP TADP
+ *
+ * @brief PCI trace AD pattern register
+ *
+ * @{
+ */
+
+#define GRPCI2_TADP_PATTERN_SHIFT 0
+#define GRPCI2_TADP_PATTERN_MASK 0xffffffffU
+#define GRPCI2_TADP_PATTERN_GET( _reg ) \
+  ( ( ( _reg ) >> 0 ) & 0xffffffffU )
+#define GRPCI2_TADP_PATTERN( _val ) ( ( _val ) << 0 )
+
+/** @} */
+
+/**
+ * @defgroup DevGrlibIfGrpci2TADM TADM
+ *
+ * @brief PCI trace AD mask register
+ *
+ * @{
+ */
+
+#define GRPCI2_TADM_MASK_SHIFT 0
+#define GRPCI2_TADM_MASK_MASK 0xffffffffU
+#define GRPCI2_TADM_MASK_GET( _reg ) \
+  ( ( ( _reg ) >> 0 ) & 0xffffffffU )
+#define GRPCI2_TADM_MASK( _val ) ( ( _val ) << 0 )
+
+/** @} */
+
+/**
+ * @defgroup DevGrlibIfGrpci2TCP TCP
+ *
+ * @brief PCI trace Ctrl signal pattern register
+ *
+ * @{
+ */
+
+#define GRPCI2_TCP_CBE_3_0_SHIFT 16
+#define GRPCI2_TCP_CBE_3_0_MASK 0xf0000U
+#define GRPCI2_TCP_CBE_3_0_GET( _reg ) \
+  ( ( ( _reg ) >> 16 ) & 0xfU )
+#define GRPCI2_TCP_CBE_3_0( _val ) ( ( _val ) << 16 )
+
+#define GRPCI2_TCP_FRAME 0x8000U
+
+#define GRPCI2_TCP_IRDY 0x4000U
+
+#define GRPCI2_TCP_TRDY 0x2000U
+
+#define GRPCI2_TCP_STOP 0x1000U
+
+#define GRPCI2_TCP_DEVSEL 0x800U
+
+#define GRPCI2_TCP_PAR 0x400U
+
+#define GRPCI2_TCP_PERR 0x200U
+
+#define GRPCI2_TCP_SERR 0x100U
+
+#define GRPCI2_TCP_IDSEL 0x80U
+
+#define GRPCI2_TCP_REQ 0x40U
+
+#define GRPCI2_TCP_GNT 0x20U
+
+#define GRPCI2_TCP_LOCK 0x10U
+
+#define GRPCI2_TCP_RST 0x8U
+
+/** @} */
+
+/**
+ * @defgroup DevGrlibIfGrpci2TCM TCM
+ *
+ * @brief PCI trace Ctrl signal mask register
+ *
+ * @{
+ */
+
+#define GRPCI2_TCM_CBE_3_0_SHIFT 16
+#define GRPCI2_TCM_CBE_3_0_MASK 0xf0000U
+#define GRPCI2_TCM_CBE_3_0_GET( _reg ) \
+  ( ( ( _reg ) >> 16 ) & 0xfU )
+#define GRPCI2_TCM_CBE_3_0( _val ) ( ( _val ) << 16 )
+
+#define GRPCI2_TCM_FRAME 0x8000U
+
+#define GRPCI2_TCM_IRDY 0x4000U
+
+#define GRPCI2_TCM_TRDY 0x2000U
+
+#define GRPCI2_TCM_STOP 0x1000U
+
+#define GRPCI2_TCM_DEVSEL 0x800U
+
+#define GRPCI2_TCM_PAR 0x400U
+
+#define GRPCI2_TCM_PERR 0x200U
+
+#define GRPCI2_TCM_SERR 0x100U
+
+#define GRPCI2_TCM_IDSEL 0x80U
+
+#define GRPCI2_TCM_REQ 0x40U
+
+#define GRPCI2_TCM_GNT 0x20U
+
+#define GRPCI2_TCM_LOCK 0x10U
+
+#define GRPCI2_TCM_RST 0x8U
+
+/** @} */
+
+/**
+ * @defgroup DevGrlibIfGrpci2TADS TADS
+ *
+ * @brief PCI trace PCI AD state register
+ *
+ * @{
+ */
+
+#define GRPCI2_TADS_SIGNAL_SHIFT 0
+#define GRPCI2_TADS_SIGNAL_MASK 0xffffffffU
+#define GRPCI2_TADS_SIGNAL_GET( _reg ) \
+  ( ( ( _reg ) >> 0 ) & 0xffffffffU )
+#define GRPCI2_TADS_SIGNAL( _val ) ( ( _val ) << 0 )
+
+/** @} */
+
+/**
+ * @defgroup DevGrlibIfGrpci2TCS TCS
+ *
+ * @brief PCI trace PCI Ctrl signal state register
+ *
+ * @{
+ */
+
+#define GRPCI2_TCS_CBE_3_0_SHIFT 16
+#define GRPCI2_TCS_CBE_3_0_MASK 0xf0000U
+#define GRPCI2_TCS_CBE_3_0_GET( _reg ) \
+  ( ( ( _reg ) >> 16 ) & 0xfU )
+#define GRPCI2_TCS_CBE_3_0( _val ) ( ( _val ) << 16 )
+
+#define GRPCI2_TCS_FRAME 0x8000U
+
+#define GRPCI2_TCS_IRDY 0x4000U
+
+#define GRPCI2_TCS_TRDY 0x2000U
+
+#define GRPCI2_TCS_STOP 0x1000U
+
+#define GRPCI2_TCS_DEVSEL 0x800U
+
+#define GRPCI2_TCS_PAR 0x400U
+
+#define GRPCI2_TCS_PERR 0x200U
+
+#define GRPCI2_TCS_SERR 0x100U
+
+#define GRPCI2_TCS_IDSEL 0x80U
+
+#define GRPCI2_TCS_REQ 0x40U
+
+#define GRPCI2_TCS_GNT 0x20U
+
+#define GRPCI2_TCS_LOCK 0x10U
+
+#define GRPCI2_TCS_RST 0x8U
+
+/** @} */
+
+/**
+ * @brief This structure defines the GRPCI2 register block memory map.
+ */
+typedef struct {
+  /**
+   * @brief See @ref DevGrlibIfGrpci2CTRL.
+   */
+  uint32_t ctrl;
+
+  /**
+   * @brief See @ref DevGrlibIfGrpci2STATCAP.
+   */
+  uint32_t statcap;
+
+  /**
+   * @brief See @ref DevGrlibIfGrpci2BCIM.
+   */
+  uint32_t bcim;
+
+  /**
+   * @brief See @ref DevGrlibIfGrpci2AHB2PCI.
+   */
+  uint32_t ahb2pci;
+
+  /**
+   * @brief See @ref DevGrlibIfGrpci2DMACTRL.
+   */
+  uint32_t dmactrl;
+
+  /**
+   * @brief See @ref DevGrlibIfGrpci2DMABASE.
+   */
+  uint32_t dmabase;
+
+  /**
+   * @brief See @ref DevGrlibIfGrpci2DMACHAN.
+   */
+  uint32_t dmachan;
+
+  uint32_t reserved_1c_20;
+
+  /**
+   * @brief See @ref DevGrlibIfGrpci2PCI2AHB.
+   */
+  uint32_t pci2ahb_0;
+
+  uint32_t reserved_24_34[ 4 ];
+
+  /**
+   * @brief See @ref DevGrlibIfGrpci2PCI2AHB.
+   */
+  uint32_t pci2ahb_1;
+
+  uint32_t reserved_38_40[ 2 ];
+
+  /**
+   * @brief See @ref DevGrlibIfGrpci2AHBM2PCI.
+   */
+  uint32_t ahbm2pci_0;
+
+  uint32_t reserved_44_7c[ 14 ];
+
+  /**
+   * @brief See @ref DevGrlibIfGrpci2AHBM2PCI.
+   */
+  uint32_t ahbm2pci_1;
+
+  /**
+   * @brief See @ref DevGrlibIfGrpci2TCTRC.
+   */
+  uint32_t tctrc;
+
+  /**
+   * @brief See @ref DevGrlibIfGrpci2TMODE.
+   */
+  uint32_t tmode;
+
+  /**
+   * @brief See @ref DevGrlibIfGrpci2TADP.
+   */
+  uint32_t tadp;
+
+  /**
+   * @brief See @ref DevGrlibIfGrpci2TADM.
+   */
+  uint32_t tadm;
+
+  /**
+   * @brief See @ref DevGrlibIfGrpci2TCP.
+   */
+  uint32_t tcp;
+
+  /**
+   * @brief See @ref DevGrlibIfGrpci2TCM.
+   */
+  uint32_t tcm;
+
+  /**
+   * @brief See @ref DevGrlibIfGrpci2TADS.
+   */
+  uint32_t tads;
+
+  /**
+   * @brief See @ref DevGrlibIfGrpci2TCS.
+   */
+  uint32_t tcs;
+} grpci2;
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DEV_GRLIB_GRPCI2_H */