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Diffstat (limited to 'bsps/include/dev/grlib/griommu.h')
| -rw-r--r-- | bsps/include/dev/grlib/griommu.h | 647 |
1 files changed, 647 insertions, 0 deletions
diff --git a/bsps/include/dev/grlib/griommu.h b/bsps/include/dev/grlib/griommu.h new file mode 100644 index 0000000000..cbe4c8b6af --- /dev/null +++ b/bsps/include/dev/grlib/griommu.h @@ -0,0 +1,647 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSDeviceGRLIB + * + * @brief This header file defines the GRIOMMU register block interface. + */ + +/* + * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file is part of the RTEMS quality process and was automatically + * generated. If you find something that needs to be fixed or + * worded better please post a report or patch to an RTEMS mailing list + * or raise a bug report: + * + * https://www.rtems.org/bugs.html + * + * For information on updating and regenerating please refer to the How-To + * section in the Software Requirements Engineering chapter of the + * RTEMS Software Engineering manual. The manual is provided as a part of + * a release. For development sources please refer to the online + * documentation at: + * + * https://docs.rtems.org + */ + +/* Generated from spec:/dev/grlib/if/griommu-header */ + +#ifndef _DEV_GRLIB_GRIOMMU_H +#define _DEV_GRLIB_GRIOMMU_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Generated from spec:/dev/grlib/if/griommu */ + +/** + * @defgroup DevGrlibIfGriommu GRIOMMU + * + * @ingroup RTEMSDeviceGRLIB + * + * @brief This group contains the GRIOMMU interfaces. + * + * @{ + */ + +/** + * @defgroup DevGrlibIfGriommuCAP0 CAP0 + * + * @brief Capability register 0 + * + * @{ + */ + +#define GRIOMMU_CAP0_A 0x80000000U + +#define GRIOMMU_CAP0_AC 0x40000000U + +#define GRIOMMU_CAP0_CA 0x20000000U + +#define GRIOMMU_CAP0_CP 0x10000000U + +#define GRIOMMU_CAP0_NARB_SHIFT 20 +#define GRIOMMU_CAP0_NARB_MASK 0xf00000U +#define GRIOMMU_CAP0_NARB_GET( _reg ) \ + ( ( ( _reg ) >> 20 ) & 0xfU ) +#define GRIOMMU_CAP0_NARB( _val ) ( ( _val ) << 20 ) + +#define GRIOMMU_CAP0_CS 0x80000U + +#define GRIOMMU_CAP0_FT_SHIFT 17 +#define GRIOMMU_CAP0_FT_MASK 0x60000U +#define GRIOMMU_CAP0_FT_GET( _reg ) \ + ( ( ( _reg ) >> 17 ) & 0x3U ) +#define GRIOMMU_CAP0_FT( _val ) ( ( _val ) << 17 ) + +#define GRIOMMU_CAP0_ST 0x10000U + +#define GRIOMMU_CAP0_I 0x8000U + +#define GRIOMMU_CAP0_IT 0x4000U + +#define GRIOMMU_CAP0_IA 0x2000U + +#define GRIOMMU_CAP0_IP 0x1000U + +#define GRIOMMU_CAP0_MB 0x100U + +#define GRIOMMU_CAP0_GRPS_SHIFT 4 +#define GRIOMMU_CAP0_GRPS_MASK 0xf0U +#define GRIOMMU_CAP0_GRPS_GET( _reg ) \ + ( ( ( _reg ) >> 4 ) & 0xfU ) +#define GRIOMMU_CAP0_GRPS( _val ) ( ( _val ) << 4 ) + +#define GRIOMMU_CAP0_MSTS_SHIFT 0 +#define GRIOMMU_CAP0_MSTS_MASK 0xfU +#define GRIOMMU_CAP0_MSTS_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xfU ) +#define GRIOMMU_CAP0_MSTS( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup DevGrlibIfGriommuCAP1 CAP1 + * + * @brief Capability register 1 + * + * @{ + */ + +#define GRIOMMU_CAP1_CADDR_SHIFT 20 +#define GRIOMMU_CAP1_CADDR_MASK 0xfff00000U +#define GRIOMMU_CAP1_CADDR_GET( _reg ) \ + ( ( ( _reg ) >> 20 ) & 0xfffU ) +#define GRIOMMU_CAP1_CADDR( _val ) ( ( _val ) << 20 ) + +#define GRIOMMU_CAP1_CMASK_SHIFT 16 +#define GRIOMMU_CAP1_CMASK_MASK 0xf0000U +#define GRIOMMU_CAP1_CMASK_GET( _reg ) \ + ( ( ( _reg ) >> 16 ) & 0xfU ) +#define GRIOMMU_CAP1_CMASK( _val ) ( ( _val ) << 16 ) + +#define GRIOMMU_CAP1_CTAGBITS_SHIFT 8 +#define GRIOMMU_CAP1_CTAGBITS_MASK 0xff00U +#define GRIOMMU_CAP1_CTAGBITS_GET( _reg ) \ + ( ( ( _reg ) >> 8 ) & 0xffU ) +#define GRIOMMU_CAP1_CTAGBITS( _val ) ( ( _val ) << 8 ) + +#define GRIOMMU_CAP1_CISIZE_SHIFT 5 +#define GRIOMMU_CAP1_CISIZE_MASK 0xe0U +#define GRIOMMU_CAP1_CISIZE_GET( _reg ) \ + ( ( ( _reg ) >> 5 ) & 0x7U ) +#define GRIOMMU_CAP1_CISIZE( _val ) ( ( _val ) << 5 ) + +#define GRIOMMU_CAP1_CLINES_SHIFT 0 +#define GRIOMMU_CAP1_CLINES_MASK 0x1fU +#define GRIOMMU_CAP1_CLINES_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0x1fU ) +#define GRIOMMU_CAP1_CLINES( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup DevGrlibIfGriommuCAP2 CAP2 + * + * @brief Capability register 2 + * + * @{ + */ + +#define GRIOMMU_CAP2_TMASK_SHIFT 24 +#define GRIOMMU_CAP2_TMASK_MASK 0xff000000U +#define GRIOMMU_CAP2_TMASK_GET( _reg ) \ + ( ( ( _reg ) >> 24 ) & 0xffU ) +#define GRIOMMU_CAP2_TMASK( _val ) ( ( _val ) << 24 ) + +#define GRIOMMU_CAP2_MTYPE_SHIFT 18 +#define GRIOMMU_CAP2_MTYPE_MASK 0xc0000U +#define GRIOMMU_CAP2_MTYPE_GET( _reg ) \ + ( ( ( _reg ) >> 18 ) & 0x3U ) +#define GRIOMMU_CAP2_MTYPE( _val ) ( ( _val ) << 18 ) + +#define GRIOMMU_CAP2_TTYPE_SHIFT 16 +#define GRIOMMU_CAP2_TTYPE_MASK 0x30000U +#define GRIOMMU_CAP2_TTYPE_GET( _reg ) \ + ( ( ( _reg ) >> 16 ) & 0x3U ) +#define GRIOMMU_CAP2_TTYPE( _val ) ( ( _val ) << 16 ) + +#define GRIOMMU_CAP2_TTAGBITS_SHIFT 8 +#define GRIOMMU_CAP2_TTAGBITS_MASK 0xff00U +#define GRIOMMU_CAP2_TTAGBITS_GET( _reg ) \ + ( ( ( _reg ) >> 8 ) & 0xffU ) +#define GRIOMMU_CAP2_TTAGBITS( _val ) ( ( _val ) << 8 ) + +#define GRIOMMU_CAP2_ISIZE_SHIFT 5 +#define GRIOMMU_CAP2_ISIZE_MASK 0xe0U +#define GRIOMMU_CAP2_ISIZE_GET( _reg ) \ + ( ( ( _reg ) >> 5 ) & 0x7U ) +#define GRIOMMU_CAP2_ISIZE( _val ) ( ( _val ) << 5 ) + +#define GRIOMMU_CAP2_TLBENT_SHIFT 0 +#define GRIOMMU_CAP2_TLBENT_MASK 0x1fU +#define GRIOMMU_CAP2_TLBENT_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0x1fU ) +#define GRIOMMU_CAP2_TLBENT( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup DevGrlibIfGriommuCTRL CTRL + * + * @brief Control register + * + * @{ + */ + +#define GRIOMMU_CTRL_PGSZ_SHIFT 18 +#define GRIOMMU_CTRL_PGSZ_MASK 0x1c0000U +#define GRIOMMU_CTRL_PGSZ_GET( _reg ) \ + ( ( ( _reg ) >> 18 ) & 0x7U ) +#define GRIOMMU_CTRL_PGSZ( _val ) ( ( _val ) << 18 ) + +#define GRIOMMU_CTRL_LB 0x20000U + +#define GRIOMMU_CTRL_SP 0x10000U + +#define GRIOMMU_CTRL_ITR_SHIFT 12 +#define GRIOMMU_CTRL_ITR_MASK 0xf000U +#define GRIOMMU_CTRL_ITR_GET( _reg ) \ + ( ( ( _reg ) >> 12 ) & 0xfU ) +#define GRIOMMU_CTRL_ITR( _val ) ( ( _val ) << 12 ) + +#define GRIOMMU_CTRL_DP 0x800U + +#define GRIOMMU_CTRL_SIV 0x400U + +#define GRIOMMU_CTRL_HPROT_SHIFT 8 +#define GRIOMMU_CTRL_HPROT_MASK 0x300U +#define GRIOMMU_CTRL_HPROT_GET( _reg ) \ + ( ( ( _reg ) >> 8 ) & 0x3U ) +#define GRIOMMU_CTRL_HPROT( _val ) ( ( _val ) << 8 ) + +#define GRIOMMU_CTRL_AU 0x80U + +#define GRIOMMU_CTRL_WP 0x40U + +#define GRIOMMU_CTRL_DM 0x20U + +#define GRIOMMU_CTRL_GS 0x10U + +#define GRIOMMU_CTRL_CE 0x8U + +#define GRIOMMU_CTRL_PM_SHIFT 1 +#define GRIOMMU_CTRL_PM_MASK 0x6U +#define GRIOMMU_CTRL_PM_GET( _reg ) \ + ( ( ( _reg ) >> 1 ) & 0x3U ) +#define GRIOMMU_CTRL_PM( _val ) ( ( _val ) << 1 ) + +#define GRIOMMU_CTRL_EN 0x1U + +/** @} */ + +/** + * @defgroup DevGrlibIfGriommuFLUSH FLUSH + * + * @brief TLB/cache flush register + * + * @{ + */ + +#define GRIOMMU_FLUSH_FGRP_SHIFT 4 +#define GRIOMMU_FLUSH_FGRP_MASK 0xf0U +#define GRIOMMU_FLUSH_FGRP_GET( _reg ) \ + ( ( ( _reg ) >> 4 ) & 0xfU ) +#define GRIOMMU_FLUSH_FGRP( _val ) ( ( _val ) << 4 ) + +#define GRIOMMU_FLUSH_GF 0x2U + +#define GRIOMMU_FLUSH_F 0x1U + +/** @} */ + +/** + * @defgroup DevGrlibIfGriommuSTATUS STATUS + * + * @brief Status register + * + * @{ + */ + +#define GRIOMMU_STATUS_PE 0x20U + +#define GRIOMMU_STATUS_DE 0x10U + +#define GRIOMMU_STATUS_FC 0x8U + +#define GRIOMMU_STATUS_FL 0x4U + +#define GRIOMMU_STATUS_AD 0x2U + +#define GRIOMMU_STATUS_TE 0x1U + +/** @} */ + +/** + * @defgroup DevGrlibIfGriommuIMASK IMASK + * + * @brief Interrupt mask register + * + * @{ + */ + +#define GRIOMMU_IMASK_PEI 0x20U + +#define GRIOMMU_IMASK_FCI 0x8U + +#define GRIOMMU_IMASK_FLI 0x4U + +#define GRIOMMU_IMASK_ADI 0x2U + +#define GRIOMMU_IMASK_TEI 0x1U + +/** @} */ + +/** + * @defgroup DevGrlibIfGriommuAHBFAS AHBFAS + * + * @brief AHB failing access register + * + * @{ + */ + +#define GRIOMMU_AHBFAS_FADDR_31_5_SHIFT 5 +#define GRIOMMU_AHBFAS_FADDR_31_5_MASK 0xffffffe0U +#define GRIOMMU_AHBFAS_FADDR_31_5_GET( _reg ) \ + ( ( ( _reg ) >> 5 ) & 0x7ffffffU ) +#define GRIOMMU_AHBFAS_FADDR_31_5( _val ) ( ( _val ) << 5 ) + +#define GRIOMMU_AHBFAS_FW 0x10U + +#define GRIOMMU_AHBFAS_FMASTER_SHIFT 0 +#define GRIOMMU_AHBFAS_FMASTER_MASK 0xfU +#define GRIOMMU_AHBFAS_FMASTER_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xfU ) +#define GRIOMMU_AHBFAS_FMASTER( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup DevGrlibIfGriommuMSTCFG MSTCFG + * + * @brief Master configuration register 0 - 9 + * + * @{ + */ + +#define GRIOMMU_MSTCFG_VENDOR_SHIFT 24 +#define GRIOMMU_MSTCFG_VENDOR_MASK 0xff000000U +#define GRIOMMU_MSTCFG_VENDOR_GET( _reg ) \ + ( ( ( _reg ) >> 24 ) & 0xffU ) +#define GRIOMMU_MSTCFG_VENDOR( _val ) ( ( _val ) << 24 ) + +#define GRIOMMU_MSTCFG_DEVICE_SHIFT 12 +#define GRIOMMU_MSTCFG_DEVICE_MASK 0xfff000U +#define GRIOMMU_MSTCFG_DEVICE_GET( _reg ) \ + ( ( ( _reg ) >> 12 ) & 0xfffU ) +#define GRIOMMU_MSTCFG_DEVICE( _val ) ( ( _val ) << 12 ) + +#define GRIOMMU_MSTCFG_BS 0x10U + +#define GRIOMMU_MSTCFG_GROUP_SHIFT 0 +#define GRIOMMU_MSTCFG_GROUP_MASK 0xfU +#define GRIOMMU_MSTCFG_GROUP_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xfU ) +#define GRIOMMU_MSTCFG_GROUP( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup DevGrlibIfGriommuGRPCTRL GRPCTRL + * + * @brief Group control register 0 - 7 + * + * @{ + */ + +#define GRIOMMU_GRPCTRL_BASE_31_4_SHIFT 4 +#define GRIOMMU_GRPCTRL_BASE_31_4_MASK 0xfffffff0U +#define GRIOMMU_GRPCTRL_BASE_31_4_GET( _reg ) \ + ( ( ( _reg ) >> 4 ) & 0xfffffffU ) +#define GRIOMMU_GRPCTRL_BASE_31_4( _val ) ( ( _val ) << 4 ) + +#define GRIOMMU_GRPCTRL_P 0x2U + +#define GRIOMMU_GRPCTRL_AG 0x1U + +/** @} */ + +/** + * @defgroup DevGrlibIfGriommuDIAGCTRL DIAGCTRL + * + * @brief Diagnostic cache access register + * + * @{ + */ + +#define GRIOMMU_DIAGCTRL_DA 0x80000000U + +#define GRIOMMU_DIAGCTRL_RW 0x40000000U + +#define GRIOMMU_DIAGCTRL_DP 0x200000U + +#define GRIOMMU_DIAGCTRL_TP 0x100000U + +#define GRIOMMU_DIAGCTRL_SETADDR_SHIFT 0 +#define GRIOMMU_DIAGCTRL_SETADDR_MASK 0x7ffffU +#define GRIOMMU_DIAGCTRL_SETADDR_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0x7ffffU ) +#define GRIOMMU_DIAGCTRL_SETADDR( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup DevGrlibIfGriommuDIAGD DIAGD + * + * @brief Diagnostic cache access data register 0 - 7 + * + * @{ + */ + +#define GRIOMMU_DIAGD_CDATAN_SHIFT 0 +#define GRIOMMU_DIAGD_CDATAN_MASK 0xffffffffU +#define GRIOMMU_DIAGD_CDATAN_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define GRIOMMU_DIAGD_CDATAN( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup DevGrlibIfGriommuDIAGT DIAGT + * + * @brief Diagnostic cache access tag register + * + * @{ + */ + +#define GRIOMMU_DIAGT_TAG_SHIFT 1 +#define GRIOMMU_DIAGT_TAG_MASK 0xfffffffeU +#define GRIOMMU_DIAGT_TAG_GET( _reg ) \ + ( ( ( _reg ) >> 1 ) & 0x7fffffffU ) +#define GRIOMMU_DIAGT_TAG( _val ) ( ( _val ) << 1 ) + +#define GRIOMMU_DIAGT_V 0x1U + +/** @} */ + +/** + * @defgroup DevGrlibIfGriommuDERRI DERRI + * + * @brief Data RAM error injection register + * + * @{ + */ + +#define GRIOMMU_DERRI_DPERRINJ_SHIFT 0 +#define GRIOMMU_DERRI_DPERRINJ_MASK 0xffffffffU +#define GRIOMMU_DERRI_DPERRINJ_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define GRIOMMU_DERRI_DPERRINJ( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup DevGrlibIfGriommuTERRI TERRI + * + * @brief Tag RAM error injection register + * + * @{ + */ + +#define GRIOMMU_TERRI_TPERRINJ_SHIFT 0 +#define GRIOMMU_TERRI_TPERRINJ_MASK 0xffffffffU +#define GRIOMMU_TERRI_TPERRINJ_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffffffU ) +#define GRIOMMU_TERRI_TPERRINJ( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @defgroup DevGrlibIfGriommuASMPCTRL ASMPCTRL + * + * @brief ASMP access control registers 0 - 3 + * + * @{ + */ + +#define GRIOMMU_ASMPCTRL_FC 0x40000U + +#define GRIOMMU_ASMPCTRL_SC 0x20000U + +#define GRIOMMU_ASMPCTRL_MC 0x10000U + +#define GRIOMMU_ASMPCTRL_GRPACCSZCTRL_SHIFT 0 +#define GRIOMMU_ASMPCTRL_GRPACCSZCTRL_MASK 0xffffU +#define GRIOMMU_ASMPCTRL_GRPACCSZCTRL_GET( _reg ) \ + ( ( ( _reg ) >> 0 ) & 0xffffU ) +#define GRIOMMU_ASMPCTRL_GRPACCSZCTRL( _val ) ( ( _val ) << 0 ) + +/** @} */ + +/** + * @brief This structure defines the GRIOMMU register block memory map. + */ +typedef struct { + /** + * @brief See @ref DevGrlibIfGriommuCAP0. + */ + uint32_t cap0; + + /** + * @brief See @ref DevGrlibIfGriommuCAP1. + */ + uint32_t cap1; + + /** + * @brief See @ref DevGrlibIfGriommuCAP2. + */ + uint32_t cap2; + + uint32_t reserved_c_10; + + /** + * @brief See @ref DevGrlibIfGriommuCTRL. + */ + uint32_t ctrl; + + /** + * @brief See @ref DevGrlibIfGriommuFLUSH. + */ + uint32_t flush; + + /** + * @brief See @ref DevGrlibIfGriommuSTATUS. + */ + uint32_t status; + + /** + * @brief See @ref DevGrlibIfGriommuIMASK. + */ + uint32_t imask; + + /** + * @brief See @ref DevGrlibIfGriommuAHBFAS. + */ + uint32_t ahbfas; + + uint32_t reserved_24_40[ 7 ]; + + /** + * @brief See @ref DevGrlibIfGriommuMSTCFG. + */ + uint32_t mstcfg_0; + + uint32_t reserved_44_64[ 8 ]; + + /** + * @brief See @ref DevGrlibIfGriommuMSTCFG. + */ + uint32_t mstcfg_1; + + uint32_t reserved_68_80[ 6 ]; + + /** + * @brief See @ref DevGrlibIfGriommuGRPCTRL. + */ + uint32_t grpctrl_0; + + uint32_t reserved_84_9c[ 6 ]; + + /** + * @brief See @ref DevGrlibIfGriommuGRPCTRL. + */ + uint32_t grpctrl_1; + + uint32_t reserved_a0_c0[ 8 ]; + + /** + * @brief See @ref DevGrlibIfGriommuDIAGCTRL. + */ + uint32_t diagctrl; + + /** + * @brief See @ref DevGrlibIfGriommuDIAGD. + */ + uint32_t diagd_0; + + uint32_t reserved_c8_e0[ 6 ]; + + /** + * @brief See @ref DevGrlibIfGriommuDIAGD. + */ + uint32_t diagd_1; + + /** + * @brief See @ref DevGrlibIfGriommuDIAGT. + */ + uint32_t diagt; + + /** + * @brief See @ref DevGrlibIfGriommuDERRI. + */ + uint32_t derri; + + /** + * @brief See @ref DevGrlibIfGriommuTERRI. + */ + uint32_t terri; + + uint32_t reserved_f0_100[ 4 ]; + + /** + * @brief See @ref DevGrlibIfGriommuASMPCTRL. + */ + uint32_t asmpctrl_0; + + uint32_t reserved_104_10c[ 2 ]; + + /** + * @brief See @ref DevGrlibIfGriommuASMPCTRL. + */ + uint32_t asmpctrl_1; +} griommu; + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _DEV_GRLIB_GRIOMMU_H */ |